diff options
Diffstat (limited to 'cpukit/score/cpu/riscv/include/rtems/score')
4 files changed, 92 insertions, 65 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 3f3c8de74c..e342e7d4af 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -4,7 +4,7 @@ */ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> @@ -152,7 +152,10 @@ static inline uint32_t riscv_interrupt_disable( void ) unsigned long mstatus; __asm__ volatile ( - "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) : + ".option push\n" + ".option arch, +zicsr\n" + "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n" + ".option pop" : "=&r" ( mstatus ) ); @@ -161,7 +164,14 @@ static inline uint32_t riscv_interrupt_disable( void ) static inline void riscv_interrupt_enable( uint32_t level ) { - __asm__ volatile ( "csrrs zero, mstatus, %0" : : "r" ( level ) ); + __asm__ volatile ( + ".option push\n" + ".option arch, +zicsr\n" + "csrrs zero, mstatus, %0\n" + ".option pop" : + : + "r" ( level ) + ); } #define _CPU_ISR_Disable( _level ) \ @@ -176,22 +186,26 @@ static inline void riscv_interrupt_enable( uint32_t level ) riscv_interrupt_disable(); \ } while(0) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level ) +static inline bool _CPU_ISR_Is_enabled( unsigned long level ) { return ( level & RISCV_MSTATUS_MIE ) != 0; } -RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level( uint32_t level ) +static inline void _CPU_ISR_Set_level( uint32_t level ) { - if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) { - __asm__ volatile ( - "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) - ); - } else { - __asm__ volatile ( - "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) - ); - } + /* + * Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported + * interrupt level allowed to set is 0 (interrupts enabled). This constraint + * is enforced by the API level functions which return an error status for + * other interrupt levels. + */ + (void) level; + __asm__ volatile ( + ".option push\n" + ".option arch, +zicsr\n" + "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n" + ".option pop" + ); } uint32_t _CPU_ISR_Get_level( void ); @@ -443,14 +457,6 @@ extern volatile uint32_t * const _RISCV_Counter; CPU_Counter_ticks _CPU_Counter_read( void ); -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - #ifdef RTEMS_SMP uint32_t _CPU_SMP_Initialize( void ); @@ -465,9 +471,15 @@ static inline uint32_t _CPU_SMP_Get_current_processor( void ) { unsigned long mhartid; - __asm__ volatile ( "csrr %0, mhartid" : "=&r" ( mhartid ) ); + __asm__ volatile ( + ".option push\n" + ".option arch, +zicsr\n" + "csrr %0, mhartid\n" + ".option pop" : + "=&r" ( mhartid ) + ); - return (uint32_t) mhartid; + return (uint32_t) mhartid - RISCV_BOOT_HARTID; } void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); @@ -487,6 +499,10 @@ static inline void _CPU_Context_Set_is_executing( context->is_executing = is_executing; } +RTEMS_NO_RETURN void _RISCV_Start_multitasking( Context_Control *heir ); + +#define _CPU_Start_multitasking( _heir ) _RISCV_Start_multitasking( _heir ) + #endif /* RTEMS_SMP */ /** Type that can store a 32-bit integer or a pointer. */ diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuatomic.h deleted file mode 100644 index 8ee9606b44..0000000000 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuatomic.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include <rtems/score/cpustdatomic.h> - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index eee6ad7328..13fd60ed8c 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -5,7 +5,7 @@ */ /* - * Copyright (c) 2013, 2018 embedded brains GmbH + * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -54,6 +54,8 @@ #define CPU_PER_CPU_CONTROL_SIZE 16 #endif +#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10 + #ifdef RTEMS_SMP #define RISCV_CONTEXT_IS_EXECUTING 0 #endif @@ -296,6 +298,16 @@ extern "C" { #endif +static inline uint32_t _RISCV_Map_hardid_to_cpu_index( uint32_t hardid ) +{ + return hardid - RISCV_BOOT_HARTID; +} + +static inline uint32_t _RISCV_Map_cpu_index_to_hardid( uint32_t cpu_index ) +{ + return cpu_index + RISCV_BOOT_HARTID; +} + /* Core Local Interruptor (CLINT) */ typedef union { @@ -325,7 +337,7 @@ typedef struct { uint32_t priority[RISCV_PLIC_MAX_INTERRUPTS]; uint32_t pending[1024]; uint32_t enable[16320][32]; - RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS]; + RISCV_PLIC_hart_regs harts[CPU_MAXIMUM_PROCESSORS + RISCV_BOOT_HARTID]; } RISCV_PLIC_regs; typedef struct { @@ -399,7 +411,13 @@ static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void ) { struct Per_CPU_Control *cpu_self; - __asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) ); + __asm__ volatile ( + ".option push\n" + ".option arch, +zicsr\n" + "csrr %0, mscratch\n" + ".option pop" : + "=r" ( cpu_self ) + ); return cpu_self; } @@ -414,16 +432,35 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern ); void _CPU_Context_validate( uintptr_t pattern ); -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( "unimp" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } +static inline void _CPU_Use_thread_local_storage( + const Context_Control *context +) +{ + register uintptr_t tp __asm__( "tp" ); + + tp = context->tp; + + /* Make sure that the register assignment is not optimized away */ + __asm__ volatile ( "" : : "r" ( tp ) ); +} + +static inline void *_CPU_Get_TLS_thread_pointer( + const Context_Control *context +) +{ + return (void *) context->tp; +} + #ifdef __cplusplus } #endif diff --git a/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h b/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h index dc4836bee2..1cfcf8dbad 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h @@ -247,22 +247,27 @@ typedef enum { #ifdef __GNUC__ #define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + asm volatile (".option push\n.option arch, +zicsr\n" \ + "csrr %0, " #reg "\n.option pop ": "=r"(__tmp)); \ __tmp; }) #define write_csr(reg, val) ({ \ - asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + asm volatile (".option push\n.option arch, +zicsr\n" \ + "csrw " #reg ", %0\n.option pop" :: "rK"(val)); }) #define swap_csr(reg, val) ({ unsigned long __tmp; \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + asm volatile (".option push\n.option arch, +zicsr\n" \ + "csrrw %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(val)); \ __tmp; }) #define set_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + asm volatile (".option push\n.option arch, +zicsr\nc" \ + "srrs %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) #define clear_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + asm volatile (".option push\n.option arch, +zicsr\n" \ + "csrrc %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) #define rdtime() read_csr(time) |