diff options
Diffstat (limited to 'cpukit/score/cpu/riscv/include/rtems/score/riscv.h')
-rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/riscv.h | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/riscv.h b/cpukit/score/cpu/riscv/include/rtems/score/riscv.h new file mode 100644 index 0000000000..6e7f1370c6 --- /dev/null +++ b/cpukit/score/cpu/riscv/include/rtems/score/riscv.h @@ -0,0 +1,66 @@ +/** + * @file rtems/score/riscv.h + */ + +/* + * This file contains information pertaining to the riscv32 processor. + * + * COPYRIGHT (c) 2014 Hesham Almatary <heshamelmatary@gmail.com> + * + * Based on code with the following copyright... + * COPYRIGHT (c) 1989-1999, 2010. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_RISCV_H +#define _RTEMS_SCORE_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the RISCV family. + * It does this by setting variables to indicate which + * implementation dependent features are present in a particular + * member of the family. + * + * This is a good place to list all the known CPU models + * that this port supports and which RTEMS CPU model they correspond + * to. + */ + +/* +* Define the name of the CPU family and specific model. +*/ + +#define CPU_NAME "RISCV" +#define CPU_MODEL_NAME "RISCV" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_RISCV_H */ |