diff options
Diffstat (limited to 'cpukit/score/cpu/riscv/include/rtems/score/cpu.h')
-rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 64 |
1 files changed, 40 insertions, 24 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 3f3c8de74c..e342e7d4af 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -4,7 +4,7 @@ */ /* - * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> @@ -152,7 +152,10 @@ static inline uint32_t riscv_interrupt_disable( void ) unsigned long mstatus; __asm__ volatile ( - "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) : + ".option push\n" + ".option arch, +zicsr\n" + "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n" + ".option pop" : "=&r" ( mstatus ) ); @@ -161,7 +164,14 @@ static inline uint32_t riscv_interrupt_disable( void ) static inline void riscv_interrupt_enable( uint32_t level ) { - __asm__ volatile ( "csrrs zero, mstatus, %0" : : "r" ( level ) ); + __asm__ volatile ( + ".option push\n" + ".option arch, +zicsr\n" + "csrrs zero, mstatus, %0\n" + ".option pop" : + : + "r" ( level ) + ); } #define _CPU_ISR_Disable( _level ) \ @@ -176,22 +186,26 @@ static inline void riscv_interrupt_enable( uint32_t level ) riscv_interrupt_disable(); \ } while(0) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( unsigned long level ) +static inline bool _CPU_ISR_Is_enabled( unsigned long level ) { return ( level & RISCV_MSTATUS_MIE ) != 0; } -RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level( uint32_t level ) +static inline void _CPU_ISR_Set_level( uint32_t level ) { - if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) { - __asm__ volatile ( - "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) - ); - } else { - __asm__ volatile ( - "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) - ); - } + /* + * Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported + * interrupt level allowed to set is 0 (interrupts enabled). This constraint + * is enforced by the API level functions which return an error status for + * other interrupt levels. + */ + (void) level; + __asm__ volatile ( + ".option push\n" + ".option arch, +zicsr\n" + "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n" + ".option pop" + ); } uint32_t _CPU_ISR_Get_level( void ); @@ -443,14 +457,6 @@ extern volatile uint32_t * const _RISCV_Counter; CPU_Counter_ticks _CPU_Counter_read( void ); -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - #ifdef RTEMS_SMP uint32_t _CPU_SMP_Initialize( void ); @@ -465,9 +471,15 @@ static inline uint32_t _CPU_SMP_Get_current_processor( void ) { unsigned long mhartid; - __asm__ volatile ( "csrr %0, mhartid" : "=&r" ( mhartid ) ); + __asm__ volatile ( + ".option push\n" + ".option arch, +zicsr\n" + "csrr %0, mhartid\n" + ".option pop" : + "=&r" ( mhartid ) + ); - return (uint32_t) mhartid; + return (uint32_t) mhartid - RISCV_BOOT_HARTID; } void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); @@ -487,6 +499,10 @@ static inline void _CPU_Context_Set_is_executing( context->is_executing = is_executing; } +RTEMS_NO_RETURN void _RISCV_Start_multitasking( Context_Control *heir ); + +#define _CPU_Start_multitasking( _heir ) _RISCV_Start_multitasking( _heir ) + #endif /* RTEMS_SMP */ /** Type that can store a 32-bit integer or a pointer. */ |