diff options
Diffstat (limited to 'cpukit/score/cpu/powerpc/rtems')
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/asm.h | 310 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/powerpc/registers.h | 774 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/cpu.h | 1257 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/cpuatomic.h | 14 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h | 247 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/powerpc.h | 187 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/types.h | 62 |
7 files changed, 0 insertions, 2851 deletions
diff --git a/cpukit/score/cpu/powerpc/rtems/asm.h b/cpukit/score/cpu/powerpc/rtems/asm.h deleted file mode 100644 index 2fddf56e6d..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/asm.h +++ /dev/null @@ -1,310 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1995. - * i-cubed ltd. - * - * COPYRIGHT (c) 1994. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/powerpc.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#ifndef __FLOAT_REGISTER_PREFIX__ -#define __FLOAT_REGISTER_PREFIX__ __REGISTER_PREFIX__ -#endif - -#ifndef __PROC_LABEL_PREFIX__ -#define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for procedure labels. */ - -#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* Use the right prefix for floating point registers. */ - -#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG(0) -#define r1 REG(1) -#define r2 REG(2) -#define r3 REG(3) -#define r4 REG(4) -#define r5 REG(5) -#define r6 REG(6) -#define r7 REG(7) -#define r8 REG(8) -#define r9 REG(9) -#define r10 REG(10) -#define r11 REG(11) -#define r12 REG(12) -#define r13 REG(13) -#define r14 REG(14) -#define r15 REG(15) -#define r16 REG(16) -#define r17 REG(17) -#define r18 REG(18) -#define r19 REG(19) -#define r20 REG(20) -#define r21 REG(21) -#define r22 REG(22) -#define r23 REG(23) -#define r24 REG(24) -#define r25 REG(25) -#define r26 REG(26) -#define r27 REG(27) -#define r28 REG(28) -#define r29 REG(29) -#define r30 REG(30) -#define r31 REG(31) -#define f0 FREG(0) -#define f1 FREG(1) -#define f2 FREG(2) -#define f3 FREG(3) -#define f4 FREG(4) -#define f5 FREG(5) -#define f6 FREG(6) -#define f7 FREG(7) -#define f8 FREG(8) -#define f9 FREG(9) -#define f10 FREG(10) -#define f11 FREG(11) -#define f12 FREG(12) -#define f13 FREG(13) -#define f14 FREG(14) -#define f15 FREG(15) -#define f16 FREG(16) -#define f17 FREG(17) -#define f18 FREG(18) -#define f19 FREG(19) -#define f20 FREG(20) -#define f21 FREG(21) -#define f22 FREG(22) -#define f23 FREG(23) -#define f24 FREG(24) -#define f25 FREG(25) -#define f26 FREG(26) -#define f27 FREG(27) -#define f28 FREG(28) -#define f29 FREG(29) -#define f30 FREG(30) -#define f31 FREG(31) -#define v0 0 -#define v1 1 -#define v2 2 -#define v3 3 -#define v4 4 -#define v5 5 -#define v6 6 -#define v7 7 -#define v8 8 -#define v9 9 -#define v10 10 -#define v11 11 -#define v12 12 -#define v13 13 -#define v14 14 -#define v15 15 -#define v16 16 -#define v17 17 -#define v18 18 -#define v19 19 -#define v20 20 -#define v21 21 -#define v22 22 -#define v23 23 -#define v24 24 -#define v25 25 -#define v26 26 -#define v27 27 -#define v28 28 -#define v29 29 -#define v30 30 -#define v31 31 - -/* - * Some special purpose registers (SPRs). - */ -#define srr0 0x01a -#define srr1 0x01b -#define srr2 0x3de /* IBM 400 series only */ -#define srr3 0x3df /* IBM 400 series only */ -#define csrr0 58 /* Book E */ -#define csrr1 59 /* Book E */ -#define mcsrr0 570 /* e500 */ -#define mcsrr1 571 /* e500 */ -#define dsrr0 574 /* e200 */ -#define dsrr1 575 /* e200 */ - -#define sprg0 0x110 -#define sprg1 0x111 -#define sprg2 0x112 -#define sprg3 0x113 -#define sprg4 276 -#define sprg5 277 -#define sprg6 278 -#define sprg7 279 - -#define usprg0 256 - -#define dar 0x013 /* Data Address Register */ -#define dec 0x016 /* Decrementer Register */ - -#if defined(ppc403) || defined(ppc405) -/* the following SPR/DCR registers exist only in IBM 400 series */ -#define dear 0x3d5 -#define evpr 0x3d6 /* SPR: exception vector prefix register */ -#define iccr 0x3fb /* SPR: instruction cache control reg. */ -#define dccr 0x3fa /* SPR: data cache control reg. */ - -#if defined (ppc403) -#define exisr 0x040 /* DCR: external interrupt status register */ -#define exier 0x042 /* DCR: external interrupt enable register */ -#endif /* ppc403 */ -#if defined(ppc405) -#define exisr 0x0C0 /* DCR: external interrupt status register */ -#define exier 0x0C2 /* DCR: external interrupt enable register */ -#endif /* ppc405 */ - -#define br0 0x080 /* DCR: memory bank register 0 */ -#define br1 0x081 /* DCR: memory bank register 1 */ -#define br2 0x082 /* DCR: memory bank register 2 */ -#define br3 0x083 /* DCR: memory bank register 3 */ -#define br4 0x084 /* DCR: memory bank register 4 */ -#define br5 0x085 /* DCR: memory bank register 5 */ -#define br6 0x086 /* DCR: memory bank register 6 */ -#define br7 0x087 /* DCR: memory bank register 7 */ - -/* end of IBM400 series register definitions */ - -#elif defined(mpc555) -/* The following registers are for the MPC5xx */ -#define eie 0x050 /* External Interrupt Enable Register */ -#define eid 0x051 /* External Interrupt Disable Register */ -#define nri 0x052 /* Non-Recoverable Interrupt Register */ - -#elif defined(mpc860) || defined(mpc821) -/* The following registers are for the MPC8x0 */ -#define der 0x095 /* Debug Enable Register */ -#define ictrl 0x09E /* Instruction Support Control Register */ -#define immr 0x27E /* Internal Memory Map Register */ -/* end of MPC8x0 registers */ -#endif - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC_VAR(sym) .globl SYM (sym) -#define EXTERN_VAR(sym) .extern SYM (sym) -#define PUBLIC_PROC(sym) .globl PROC (sym) -#define EXTERN_PROC(sym) .extern PROC (sym) - -/* Other potentially assembler specific operations */ -#if PPC_ASM == PPC_ASM_ELF -#define ALIGN(n,p) .align p -#define DESCRIPTOR(x) \ - .section .descriptors,"aw"; \ - PUBLIC_VAR (x); \ -SYM (x):; \ - .long PROC (x); \ - .long s.got; \ - .long 0 - -#define EXT_SYM_REF(x) .long x -#define EXT_PROC_REF(x) .long x - -/* - * Define macros to handle section beginning and ends. - */ - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -#else -#error "PPC_ASM_TYPE is not properly defined" -#endif -#ifndef PPC_ASM -#error "PPC_ASM_TYPE is not properly defined" -#endif - -#if defined(__powerpc64__) -#define PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE nop -#else -#define PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE -#endif - -#endif diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h deleted file mode 100644 index 4d9350324e..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h +++ /dev/null @@ -1,774 +0,0 @@ -/** - * @file - * - * @brief PowerPc MSR and Registers Access Definitions - * - * This file contains some powerpc MSR and registers access definitions. - */ - -/* - * COPYRIGHT (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk> - * Surrey Satellite Technology Limited - * - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_POWERPC_REGISTERS_H -#define _RTEMS_POWERPC_REGISTERS_H - -/* Bit encodings for Machine State Register (MSR) */ -#define MSR_CM (1<<31) /* Computation mode */ -#define MSR_GS (1<<28) /* Guest state */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ -#define MSR_VE (1<<25) /* Alti-Vec enable (7400+) */ -#define MSR_SPE (1<<25) /* SPE enable (e500) */ -#define MSR_AP (1<<25) /* Auxiliary processor available */ -#define MSR_APE (1<<19) /* APU exception enable */ -#define MSR_POW (1<<18) /* Enable Power Management */ -#define MSR_WE (1<<18) /* Wait state enable (e500, 4xx) */ -#define MSR_TGPR (1<<17) /* TLB Update registers in use */ -#define MSR_CE (1<<17) /* BookE critical interrupt */ -#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */ -#define MSR_EE (1<<15) /* External Interrupt enable */ -#define MSR_PR (1<<14) /* Supervisor/User privilege */ -#define MSR_FP (1<<13) /* Floating Point enable */ -#define MSR_ME (1<<12) /* Machine Check enable */ -#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ -#define MSR_SE (1<<10) /* Single Step */ -#define MSR_UBLE (1<<10) /* User-mode BTB lock enable (e500) */ -#define MSR_DWE (1<<10) /* Debug wait enable (4xx) */ -#define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* BookE debug exception */ -#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ -#define MSR_E300_CE (1<<7) /* e300 critical interrupt */ -#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction MMU enable */ -#define MSR_DR (1<<4) /* Data MMU enable */ -#define MSR_IS (1<<5) /* Instruction address space */ -#define MSR_DS (1<<4) /* Data address space */ -#define MSR_PMM (1<<2) /* Performance monitor mark */ -#define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little-Endian enable */ - -/* Bit encodings for Hardware Implementation Register (HID0) - on PowerPC 603, 604, etc. processors (not 601). */ - -/* WARNING: HID0/HID1 are *truely* implementation dependent! - * you *cannot* rely on the same bits to be present, - * at the same place or even in the same register - * on different CPU familys. - * E.g., EMCP isHID0_DOZE is HID0_HI_BAT_EN on the - * on the 7450s. IFFT is XBSEN on 7450 and so on... - */ -#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ -#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ -#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ -#define HID0_SBCLK (1<<27) -#define HID0_TBEN (1<<26) /* 7455:this bit must be set - * and TBEN signal must be asserted - * to enable the time base and - * decrementer. - */ -#define HID0_EICE (1<<26) -#define HID0_ECLK (1<<25) -#define HID0_PAR (1<<24) -#define HID0_DOZE (1<<23) -/* this HI_BAT_EN only on 7445, 7447, 7448, 7455 & 7457 !! */ -#define HID0_7455_HIGH_BAT_EN (1<<23) - -#define HID0_NAP (1<<22) -#define HID0_SLEEP (1<<21) -#define HID0_DPM (1<<20) -#define HID0_ICE (1<<15) /* Instruction Cache Enable */ -#define HID0_DCE (1<<14) /* Data Cache Enable */ -#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ -#define HID0_DLOCK (1<<12) /* Data Cache Lock */ -#define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */ -#define HID0_DCI (1<<10) /* Data Cache Invalidate */ -/* this bit is XSBSEN (xtended block size enable) on 7447, 7448, 7455 and 7457 only */ -#define HID0_7455_XBSEN (1<<8) -#define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */ -#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache [Enable] */ -/* S.K. Feng 10/03, added for MPC7455 */ -#define HID0_LRSTK (1<<4) /* Link register stack enable (7455) */ -#define HID0_FOLD (1<<3) /* Branch folding enable (7455) */ - -#define HID0_BHTE (1<<2) /* Branch History Table Enable */ -#define HID0_BTCD (1<<1) /* Branch target cache disable */ - -/* fpscr settings */ -#define FPSCR_FX (1<<31) -#define FPSCR_FEX (1<<30) - -#define _MACH_prep 1 -#define _MACH_Pmac 2 /* pmac or pmac clone (non-chrp) */ -#define _MACH_chrp 4 /* chrp machine */ -#define _MACH_mbx 8 /* Motorola MBX board */ -#define _MACH_apus 16 /* amiga with phase5 powerup */ -#define _MACH_fads 32 /* Motorola FADS board */ - -/* see residual.h for these */ -#define _PREP_Motorola 0x01 /* motorola prep */ -#define _PREP_Firm 0x02 /* firmworks prep */ -#define _PREP_IBM 0x00 /* ibm prep */ -#define _PREP_Bull 0x03 /* bull prep */ - -/* these are arbitrary */ -#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ -#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ - -#define _GLOBAL(n)\ - .globl n;\ -n: - -#define TBRU 269 /* Time base Upper/Lower (Reading) */ -#define TBRL 268 -#define TBWU 285 /* Time base Upper/Lower (Writing) */ -#define TBWL 284 -#define PPC_XER 1 -#define PPC_LR 8 -#define PPC_CTR 9 -#define HID0 1008 /* Hardware Implementation 0 */ -#define HID1 1009 /* Hardware Implementation 1 */ -#define HID2 1011 /* Hardware Implementation 2 */ -#define DABR 1013 /* Data Access Breakpoint */ -#define PPC_PVR 287 /* Processor Version */ -#define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */ -#define IBAT0L 529 -#define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */ -#define IBAT1L 531 -#define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */ -#define IBAT2L 533 -#define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */ -#define IBAT3L 535 - -/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */ -#define IBAT4U 560 /* Instruction BAT #4 Upper/Lower */ -#define IBAT4L 561 -#define IBAT5U 562 /* Instruction BAT #5 Upper/Lower */ -#define IBAT5L 563 -#define IBAT6U 564 /* Instruction BAT #6 Upper/Lower */ -#define IBAT6L 565 -#define IBAT7U 566 /* Instruction BAT #7 Upper/Lower */ -#define IBAT7L 567 - -#define DBAT0U 536 /* Data BAT #0 Upper/Lower */ -#define DBAT0L 537 -#define DBAT1U 538 /* Data BAT #1 Upper/Lower */ -#define DBAT1L 539 -#define DBAT2U 540 /* Data BAT #2 Upper/Lower */ -#define DBAT2L 541 -#define DBAT3U 542 /* Data BAT #3 Upper/Lower */ -#define DBAT3L 543 - -/* Only present on 7445, 7447, 7448, 7455 and 7457 (if HID0[HIGH_BAT_EN]) */ -#define DBAT4U 568 /* Instruction BAT #4 Upper/Lower */ -#define DBAT4L 569 -#define DBAT5U 570 /* Instruction BAT #5 Upper/Lower */ -#define DBAT5L 571 -#define DBAT6U 572 /* Instruction BAT #6 Upper/Lower */ -#define DBAT6L 573 -#define DBAT7U 574 /* Instruction BAT #7 Upper/Lower */ -#define DBAT7L 575 - -#define DMISS 976 /* TLB Lookup/Refresh registers */ -#define DCMP 977 -#define HASH1 978 -#define HASH2 979 -#define IMISS 980 -#define ICMP 981 -#define PPC_RPA 982 -#define SDR1 25 /* MMU hash base register */ -#define PPC_DAR 19 /* Data Address Register */ -#define DEAR_BOOKE 61 -#define DEAR_405 981 -#define SPR0 272 /* Supervisor Private Registers */ -#define SPRG0 272 -#define SPR1 273 -#define SPRG1 273 -#define SPR2 274 -#define SPRG2 274 -#define SPR3 275 -#define SPRG3 275 -#define SPRG4 276 -#define SPRG5 277 -#define SPRG6 278 -#define SPRG7 279 -#define USPRG0 256 -#define DSISR 18 -#define SRR0 26 /* Saved Registers (exception) */ -#define SRR1 27 -#define IABR 1010 /* Instruction Address Breakpoint */ -#define PPC_DEC 22 /* Decrementer */ -#define PPC_EAR 282 /* External Address Register */ - -#define MSSCR0 1014 /* Memory Subsystem Control Register */ - -#define L2CR 1017 /* PPC 750 and 74xx L2 control register */ - -#define L2CR_L2E (1<<31) /* enable */ -#define L2CR_L2I (1<<21) /* global invalidate */ - -/* watch out L2IO and L2DO are different between 745x and 7400/7410 */ -/* Oddly, the following L2CR bit defintions in 745x - * is different from that of 7400 and 7410. - * Though not used in 7400 and 7410, it is appeded with _745x just - * to be clarified. - */ -#define L2CR_L2IO_745x 0x100000 /* (1<<20) L2 Instruction-Only */ -#define L2CR_L2DO_745x 0x10000 /* (1<<16) L2 Data-Only */ -#define L2CR_LOCK_745x (L2CR_L2IO_745x|L2CR_L2DO_745x) -#define L2CR_L3OH0 0x00080000 /* 12:L3 output hold 0 */ - -#define L3CR 1018 /* PPC 7450/7455 L3 control register */ -#define L3CR_L3IO_745x 0x400000 /* (1<<22) L3 Instruction-Only */ -#define L3CR_L3DO_745x 0x40 /* (1<<6) L3 Data-Only */ - -#define L3CR_LOCK_745x (L3CR_L3IO_745x|L3CR_L3DO_745x) - -#define L3CR_RESERVED 0x0438003a /* Reserved bits in L3CR */ -#define L3CR_L3E 0x80000000 /* 0: L3 enable */ -#define L3CR_L3PE 0x40000000 /* 1: L3 data parity checking enable */ -#define L3CR_L3APE 0x20000000 /* 2: L3 address parity checking enable */ -#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ -#define L3SIZ_1M 0x00000000 -#define L3SIZ_2M 0x10000000 -#define L3CR_L3CLKEN 0x08000000 /* 4: Enables the L3_CLK[0:1] signals */ -#define L3CR_L3CLK 0x03800000 /* 6-8: L3 clock ratio */ -#define L3CLK_60 0x00000000 /* core clock / 6 */ -#define L3CLK_20 0x01000000 /* / 2 */ -#define L3CLK_25 0x01800000 /* / 2.5 */ -#define L3CLK_30 0x02000000 /* / 3 */ -#define L3CLK_35 0x02800000 /* / 3.5 */ -#define L3CLK_40 0x03000000 /* / 4 */ -#define L3CLK_50 0x03800000 /* / 5 */ -#define L3CR_L3IO 0x00400000 /* 9: L3 instruction-only mode */ -#define L3CR_L3SPO 0x00040000 /* 13: L3 sample point override */ -#define L3CR_L3CKSP 0x00030000 /* 14-15: L3 clock sample point */ -#define L3CKSP_2 0x00000000 /* 2 clocks */ -#define L3CKSP_3 0x00010000 /* 3 clocks */ -#define L3CKSP_4 0x00020000 /* 4 clocks */ -#define L3CKSP_5 0x00030000 /* 5 clocks */ -#define L3CR_L3PSP 0x0000e000 /* 16-18: L3 P-clock sample point */ -#define L3PSP_0 0x00000000 /* 0 clocks */ -#define L3PSP_1 0x00002000 /* 1 clocks */ -#define L3PSP_2 0x00004000 /* 2 clocks */ -#define L3PSP_3 0x00006000 /* 3 clocks */ -#define L3PSP_4 0x00008000 /* 4 clocks */ -#define L3PSP_5 0x0000a000 /* 5 clocks */ -#define L3CR_L3REP 0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */ -#define L3CR_L3HWF 0x00000800 /* 20: L3 hardware flush */ -#define L3CR_L3I 0x00000400 /* 21: L3 global invaregisters.h.orig -lidate */ -#define L3CR_L3RT 0x00000300 /* 22-23: L3 SRAM type */ -#define L3RT_MSUG2_DDR 0x00000000 /* MSUG2 DDR SRAM */ -#define L3RT_PIPELINE_LATE 0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */ -#define L3RT_PB2_SRAM 0x00000300 /* PB2 SRAM */ -#define L3CR_L3NIRCA 0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */ -#define L3CR_L3DO 0x00000040 /* 25: L3 data-only mode */ -#define L3CR_PMEN 0x00000004 /* 29: Private memory enable */ -#define L3CR_PMSIZ 0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */ - -#define THRM1 1020 -#define THRM2 1021 -#define THRM3 1022 -#define THRM1_TIN (1<<(31-0)) -#define THRM1_TIV (1<<(31-1)) -#define THRM1_THRES (0x7f<<(31-8)) -#define THRM1_TID (1<<(31-29)) -#define THRM1_TIE (1<<(31-30)) -#define THRM1_V (1<<(31-31)) -#define THRM3_SITV (0x1fff << (31-30)) -#define THRM3_E (1<<(31-31)) - -/* Segment Registers */ -#define PPC_SR0 0 -#define PPC_SR1 1 -#define PPC_SR2 2 -#define PPC_SR3 3 -#define PPC_SR4 4 -#define PPC_SR5 5 -#define PPC_SR6 6 -#define PPC_SR7 7 -#define PPC_SR8 8 -#define PPC_SR9 9 -#define PPC_SR10 10 -#define PPC_SR11 11 -#define PPC_SR12 12 -#define PPC_SR13 13 -#define PPC_SR14 14 -#define PPC_SR15 15 - -#define BOOKE_DECAR 54 - -#define PPC405_MCSR 0x23C -#define PPC405_ESR 0x3D4 -#define PPC405_DEAR 0x3D5 -#define BOOKE_DEAR 61 - -#define PPC405_TSR 0x3D8 -#define BOOKE_TSR 336 -#define BOOKE_TSR_ENW (1<<31) -#define BOOKE_TSR_WIS (1<<30) -#define BOOKE_TSR_DIS (1<<27) -#define BOOKE_TSR_FIS (1<<26) - -#define PPC405_TCR 0x3DA -#define BOOKE_TCR 340 -#define BOOKE_TCR_WP(x) (((x)&3)<<30) -#define BOOKE_TCR_WP_MASK (3<<30) -#define BOOKE_TCR_WRC(x) (((x)&3)<<28) -#define BOOKE_TCR_WRC_MASK (3<<28) -#define BOOKE_TCR_WIE (1<<27) -#define BOOKE_TCR_DIE (1<<26) -#define BOOKE_TCR_FP(x) (((x)&3)<<24) -#define BOOKE_TCR_FIE (1<<23) -#define BOOKE_TCR_ARE (1<<22) -#define BOOKE_TCR_WPEXT(x) (((x)&0xf)<<17) -#define BOOKE_TCR_WPEXT_MASK (0xf<<17) -#define BOOKE_TCR_FPEXT(x) (((x)&0xf)<<13) -#define BOOKE_TCR_FPEXT_MASK (0xf<<13) - -#define BOOKE_PID 48 /* Process ID */ -#define BOOKE_CSRR0 58 /* Critical Save/Restore Register 0 */ -#define BOOKE_CSRR1 59 /* Critical Save/Restore Register 1 */ -#define BOOKE_ESR 62 /* Exception Syndrome Register */ -#define BOOKE_IVPR 63 /* Interrupt Vector Prefix Register */ -#define BOOKE_SPRG4_W 260 /* Special Purpose Register General 4 (WO) */ -#define BOOKE_SPRG5_W 261 /* Special Purpose Register General 5 (WO) */ -#define BOOKE_SPRG6_W 262 /* Special Purpose Register General 6 (WO) */ -#define BOOKE_SPRG7_W 263 /* Special Purpose Register General 7 (WO) */ -#define BOOKE_PIR 286 /* Processor ID Register */ -#define BOOKE_DBSR 304 /* Debug Status Register */ - -#define BOOKE_EPCR 307 /* Embedded Processor Control Register */ -#define BOOKE_EPCR_EXTGS (1 << 31) -#define BOOKE_EPCR_DTLBGS (1 << 30) -#define BOOKE_EPCR_ITLBGS (1 << 29) -#define BOOKE_EPCR_DSIGS (1 << 28) -#define BOOKE_EPCR_ISIGS (1 << 27) -#define BOOKE_EPCR_DUVD (1 << 26) -#define BOOKE_EPCR_ICM (1 << 25) -#define BOOKE_EPCR_GICM (1 << 24) -#define BOOKE_EPCR_DGTMI (1 << 23) -#define BOOKE_EPCR_DMIUH (1 << 22) -#define BOOKE_EPCR_PMGS (1 << 21) - -#define BOOKE_DBCR0 308 /* Debug Control Register 0 */ -#define BOOKE_DBCR1 309 /* Debug Control Register 1 */ -#define BOOKE_DBCR2 310 /* Debug Control Register 2 */ -#define BOOKE_IAC1 312 /* Instruction Address Compare 1 */ -#define BOOKE_IAC2 313 /* Instruction Address Compare 2 */ -#define BOOKE_IAC3 314 /* Instruction Address Compare 3 */ -#define BOOKE_IAC4 315 /* Instruction Address Compare 4 */ -#define BOOKE_DAC1 316 /* Data Address Compare 1 */ -#define BOOKE_DAC2 317 /* Data Address Compare 2 */ -#define BOOKE_DVC1 318 /* Data Value Compare 1 */ -#define BOOKE_DVC2 319 /* Data Value Compare 2 */ -#define BOOKE_GSRR0 378 /* Guest Save/Restore Register 0 */ -#define BOOKE_GSRR1 379 /* Guest Save/Restore Register 1 */ -#define BOOKE_GEPR 380 /* Guest External Proxy Register */ -#define BOOKE_GDEAR 381 /* Guest Data Exception Address Register */ -#define BOOKE_GPIR 382 /* Guest Processor ID Register */ -#define BOOKE_GESR 383 /* Guest Exception Syndrome Register */ -#define BOOKE_IVOR0 400 /* Interrupt Vector Offset Register 0 */ -#define BOOKE_IVOR1 401 /* Interrupt Vector Offset Register 1 */ -#define BOOKE_IVOR2 402 /* Interrupt Vector Offset Register 2 */ -#define BOOKE_IVOR3 403 /* Interrupt Vector Offset Register 3 */ -#define BOOKE_IVOR4 404 /* Interrupt Vector Offset Register 4 */ -#define BOOKE_IVOR5 405 /* Interrupt Vector Offset Register 5 */ -#define BOOKE_IVOR6 406 /* Interrupt Vector Offset Register 6 */ -#define BOOKE_IVOR7 407 /* Interrupt Vector Offset Register 7 */ -#define BOOKE_IVOR8 408 /* Interrupt Vector Offset Register 8 */ -#define BOOKE_IVOR9 409 /* Interrupt Vector Offset Register 9 */ -#define BOOKE_IVOR10 410 /* Interrupt Vector Offset Register 10 */ -#define BOOKE_IVOR11 411 /* Interrupt Vector Offset Register 11 */ -#define BOOKE_IVOR12 412 /* Interrupt Vector Offset Register 12 */ -#define BOOKE_IVOR13 413 /* Interrupt Vector Offset Register 13 */ -#define BOOKE_IVOR14 414 /* Interrupt Vector Offset Register 14 */ -#define BOOKE_IVOR15 415 /* Interrupt Vector Offset Register 15 */ -#define BOOKE_IVOR42 436 /* Interrupt Vector Offset Register 42 */ -#define BOOKE_IVOR32 528 /* Interrupt Vector Offset Register 32 */ -#define BOOKE_IVOR33 529 /* Interrupt Vector Offset Register 33 */ -#define BOOKE_IVOR34 530 /* Interrupt Vector Offset Register 34 */ -#define BOOKE_IVOR35 531 /* Interrupt Vector Offset Register 35 */ -#define BOOKE_IVOR36 532 /* Interrupt Vector Offset Register 36 */ -#define BOOKE_IVOR37 533 /* Interrupt Vector Offset Register 37 */ -#define BOOKE_IVOR38 432 /* Interrupt Vector Offset Register 38 */ -#define BOOKE_IVOR39 433 /* Interrupt Vector Offset Register 39 */ -#define BOOKE_IVOR40 434 /* Interrupt Vector Offset Register 40 */ -#define BOOKE_IVOR41 435 /* Interrupt Vector Offset Register 41 */ -#define BOOKE_GIVOR2 440 /* Guest Interrupt Vector Offset Register 2 */ -#define BOOKE_GIVOR3 441 /* Guest Interrupt Vector Offset Register 3 */ -#define BOOKE_GIVOR4 442 /* Guest Interrupt Vector Offset Register 4 */ -#define BOOKE_GIVOR8 443 /* Guest Interrupt Vector Offset Register 8 */ -#define BOOKE_GIVOR13 444 /* Guest Interrupt Vector Offset Register 13 */ -#define BOOKE_GIVOR14 445 /* Guest Interrupt Vector Offset Register 14 */ -#define BOOKE_GIVPR 446 /* Guest Interrupt Vector Prefix Register */ -#define BOOKE_MCSRR0 570 /* Machine Check Save/Restore Register 0 */ -#define BOOKE_MCSRR1 571 /* Machine Check Save/Restore Register 1 */ -#define BOOKE_MCSR 572 /* Machine Check Status Register */ -#define BOOKE_DSRR0 574 /* Debug Save/Restore Register 0 */ -#define BOOKE_DSRR1 575 /* Debug Save/Restore Register 1 */ - -#define PPC440_INV0 880 /* Instruction Cache Normal Victim 0 */ -#define PPC440_INV1 881 /* Instruction Cache Normal Victim 1 */ -#define PPC440_INV2 882 /* Instruction Cache Normal Victim 2 */ -#define PPC440_INV3 883 /* Instruction Cache Normal Victim 3 */ -#define PPC440_ITV0 884 /* Instruction Cache Transient Victim 0 */ -#define PPC440_ITV1 885 /* Instruction Cache Transient Victim 1 */ -#define PPC440_ITV2 886 /* Instruction Cache Transient Victim 2 */ -#define PPC440_ITV3 887 /* Instruction Cache Transient Victim 3 */ -#define PPC440_CCR1 888 /* Core Configuration Register 1 */ -#define PPC440_DNV0 912 /* Data Cache Normal Victim 0 */ -#define PPC440_DNV1 913 /* Data Cache Normal Victim 1 */ -#define PPC440_DNV2 914 /* Data Cache Normal Victim 2 */ -#define PPC440_DNV3 915 /* Data Cache Normal Victim 3 */ -#define PPC440_DTV0 916 /* Data Cache Transient Victim 0 */ -#define PPC440_DTV1 917 /* Data Cache Transient Victim 1 */ -#define PPC440_DTV2 918 /* Data Cache Transient Victim 2 */ -#define PPC440_DTV3 919 /* Data Cache Transient Victim 3 */ -#define PPC440_DVLIM 920 /* Data Cache Victim Limit */ -#define PPC440_IVLIM 921 /* Instruction Cache Victim Limit */ -#define PPC440_RSTCFG 923 /* Reset Configuration */ -#define PPC440_DCDBTRL 924 /* Data Cache Debug Tag Register Low */ -#define PPC440_DCDBTRH 925 /* Data Cache Debug Tag Register High */ -#define PPC440_ICDBTRL 926 /* Instruction Cache Debug Tag Register Low */ -#define PPC440_ICDBTRH 927 /* Instruction Cache Debug Tag Register High */ -#define PPC440_MMUCR 946 /* Memory Management Unit Control Register */ -#define PPC440_CCR0 947 /* Core Configuration Register 0 */ -#define PPC440_ICDBDR 979 /* Instruction Cache Debug Data Register */ -#define PPC440_DBDR 1011 /* Debug Data Register */ - -#define PPC440_TLB0_EPN(n) ( (((1<<22)-1)&(n)) << (31-21)) /* Etended Page Number */ -#define PPC440_TLB0_EPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1)) -#define PPC440_TLB0_V ( 1 << (31-22)) /* Entry valid */ -#define PPC440_TLB0_TS ( 1 << (31-23)) /* Translation space */ -#define PPC440_TLB0_TSIZE(n) ( (0xf & (n)) << (31-27)) /* Page size */ -#define PPC440_TLB0_TSIZE_GET(n) ( ((n) >> (31-27)) & 0xf) -#define PPC440_TLB0_TPAR(n) ( (0xf & (n)) << (31-31)) /* Tag Parity */ -#define PPC440_TLB0_TPAR_GET(n) ( ((n) >> (31-31)) & 0xf) - -#define PPC440_PID_TID(n) ( (0xff & (n)) << (31-31)) /* Translation ID */ -#define PPC440_PID_TID_GET(n) ( ((n) >> (31-31)) & 0xff) - -#define PPC440_TLB1_RPN(n) ( (((1<<22)-1)&(n)) << (31-21)) /* Real Page Number */ -#define PPC440_TLB1_RPN_GET(n) ( ((n) >> (31-21)) & ((1<<22)-1)) -#define PPC440_TLB1_PAR1(n) ( (0x3 & (n)) << (31-23)) /* Parity for TLB word 1 */ -#define PPC440_TLB1_PAR1_GET(n) ( ((n) >> (31-23)) & 0x3) -#define PPC440_TLB1_ERPN(n) ( (0xf & (n)) << (31-31)) /* Extended Real Page No. */ -#define PPC440_TLB1_ERPN_GET(n) ( ((n) >> (31-31)) & 0xf) - -#define PPC440_TLB2_PAR2(n) ( (0x3 & (n)) << (31- 1)) /* Parity for TLB word 2 */ -#define PPC440_TLB2_PAR2_GET(n) ( ((n) >> (31- 1)) & 0x3) -#define PPC440_TLB2_U0 ( 1 << (31-16)) /* User attr. 0 */ -#define PPC440_TLB2_U1 ( 1 << (31-17)) /* User attr. 1 */ -#define PPC440_TLB2_U2 ( 1 << (31-18)) /* User attr. 2 */ -#define PPC440_TLB2_U3 ( 1 << (31-19)) /* User attr. 3 */ -#define PPC440_TLB2_W ( 1 << (31-20)) /* Write-through */ -#define PPC440_TLB2_I ( 1 << (31-21)) /* Cache-inhibited */ -#define PPC440_TLB2_M ( 1 << (31-22)) /* Memory-coherence req. */ -#define PPC440_TLB2_G ( 1 << (31-23)) /* Guarded */ -#define PPC440_TLB2_E ( 1 << (31-24)) /* Little-endian */ -#define PPC440_TLB2_UX ( 1 << (31-26)) /* User exec. */ -#define PPC440_TLB2_UW ( 1 << (31-27)) /* User write */ -#define PPC440_TLB2_UR ( 1 << (31-28)) /* User read */ -#define PPC440_TLB2_SX ( 1 << (31-29)) /* Super exec. */ -#define PPC440_TLB2_SW ( 1 << (31-30)) /* Super write */ -#define PPC440_TLB2_SR ( 1 << (31-31)) /* Super read */ - -#define PPC440_TLB2_ATTR(x) ( ((x) & 0x1ff) << 7 ) -#define PPC440_TLB2_ATTR_GET(x) ( ((x) >> 7) & 0x1ff ) - -#define PPC440_TLB2_PERM(n) ( (n) & 0x3f ) -#define PPC440_TLB2_PERM_GET(n) ( (n) & 0x3f ) - -/* Freescale Book E Implementation Standards (EIS): Branch Operations */ - -#define FSL_EIS_BUCSR 1013 -#define FSL_EIS_BUCSR_STAC_EN (1 << (63 - 39)) -#define FSL_EIS_BUCSR_LS_EN (1 << (63 - 41)) -#define FSL_EIS_BUCSR_BBFI (1 << (63 - 54)) -#define FSL_EIS_BUCSR_BALLOC_ALL (0x0 << (63 - 59)) -#define FSL_EIS_BUCSR_BALLOC_FORWARD (0x1 << (63 - 59)) -#define FSL_EIS_BUCSR_BALLOC_BACKWARD (0x2 << (63 - 59)) -#define FSL_EIS_BUCSR_BALLOC_NONE (0x3 << (63 - 59)) -#define FSL_EIS_BUCSR_BPRED_TAKEN (0x0 << (63 - 61)) -#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_FORWARD (0x1 << (63 - 62)) -#define FSL_EIS_BUCSR_BPRED_TAKEN_ONLY_BACKWARD (0x2 << (63 - 62)) -#define FSL_EIS_BUCSR_BPRED_NOT_TAKEN (0x3 << (63 - 62)) -#define FSL_EIS_BUCSR_BPEN (1 << (63 - 63)) - -/* Freescale Book E Implementation Standards (EIS): Hardware Implementation-Dependent Registers */ - -#define FSL_EIS_SVR 1023 - -/* Freescale Book E Implementation Standards (EIS): Thread Management and Control Registers */ - -#define FSL_EIS_TENSR 437 -#define FSL_EIS_TENS 438 -#define FSL_EIS_TENC 439 -#define FSL_EIS_PPR32 898 - -/* Freescale Book E Implementation Standards (EIS): MMU Control and Status */ - -#define FSL_EIS_MAS0 624 -#define FSL_EIS_MAS0_TLBSEL (1 << (63 - 35)) -#define FSL_EIS_MAS0_ESEL(n) ((0xf & (n)) << (63 - 47)) -#define FSL_EIS_MAS0_ESEL_GET(m) (((m) >> (63 - 47)) & 0xf) -#define FSL_EIS_MAS0_NV (1 << (63 - 63)) - -#define FSL_EIS_MAS1 625 -#define FSL_EIS_MAS1_V (1 << (63 - 32)) -#define FSL_EIS_MAS1_IPROT (1 << (63 - 33)) -#define FSL_EIS_MAS1_TID(n) ((0xff & (n)) << (63 - 47)) -#define FSL_EIS_MAS1_TID_GET(n) (((n) >> (63 - 47)) & 0xfff) -#define FSL_EIS_MAS1_TS (1 << (63 - 51)) -#define FSL_EIS_MAS1_TSIZE(n) ((0xf & (n)) << (63 - 55)) -#define FSL_EIS_MAS1_TSIZE_GET(n) (((n)>>(63 - 55)) & 0xf) - -#define FSL_EIS_MAS2 626 -#define FSL_EIS_MAS2_EPN(n) ((((1 << 21) - 1)&(n)) << (63-51)) -#define FSL_EIS_MAS2_EPN_GET(n) (((n) >> (63 - 51)) & 0xfffff) -#define FSL_EIS_MAS2_EA(n) FSL_EIS_MAS2_EPN((n) >> 12) -#define FSL_EIS_MAS2_EA_GET(n) (FSL_EIS_MAS2_EPN_GET(n) << 12) -#define FSL_EIS_MAS2_X0 (1 << (63 - 57)) -#define FSL_EIS_MAS2_X1 (1 << (63 - 58)) -#define FSL_EIS_MAS2_W (1 << (63 - 59)) -#define FSL_EIS_MAS2_I (1 << (63 - 60)) -#define FSL_EIS_MAS2_M (1 << (63 - 61)) -#define FSL_EIS_MAS2_G (1 << (63 - 62)) -#define FSL_EIS_MAS2_E (1 << (63 - 63)) -#define FSL_EIS_MAS2_ATTR(x) ((x) & 0x7f) -#define FSL_EIS_MAS2_ATTR_GET(x) ((x) & 0x7f) - -#define FSL_EIS_MAS3 627 -#define FSL_EIS_MAS3_RPN(n) ((((1 << 21) - 1) & (n)) << (63-51)) -#define FSL_EIS_MAS3_RPN_GET(n) (((n)>>(63 - 51)) & 0xfffff) -#define FSL_EIS_MAS3_RA(n) FSL_EIS_MAS3_RPN((n) >> 12) -#define FSL_EIS_MAS3_RA_GET(n) (FSL_EIS_MAS3_RPN_GET(n) << 12) -#define FSL_EIS_MAS3_U0 (1 << (63 - 54)) -#define FSL_EIS_MAS3_U1 (1 << (63 - 55)) -#define FSL_EIS_MAS3_U2 (1 << (63 - 56)) -#define FSL_EIS_MAS3_U3 (1 << (63 - 57)) -#define FSL_EIS_MAS3_UX (1 << (63 - 58)) -#define FSL_EIS_MAS3_SX (1 << (63 - 59)) -#define FSL_EIS_MAS3_UW (1 << (63 - 60)) -#define FSL_EIS_MAS3_SW (1 << (63 - 61)) -#define FSL_EIS_MAS3_UR (1 << (63 - 62)) -#define FSL_EIS_MAS3_SR (1 << (63 - 63)) -#define FSL_EIS_MAS3_PERM(n) ((n) & 0x3ff) -#define FSL_EIS_MAS3_PERM_GET(n) ((n) & 0x3ff) - -#define FSL_EIS_MAS4 628 -#define FSL_EIS_MAS4_TLBSELD (1 << (63 - 35)) -#define FSL_EIS_MAS4_TIDSELD(n) ((0x3 & (n)) << (63 - 47)) -#define FSL_EIS_MAS4_TSIZED(n) ((0xf & (n)) << (63 - 55)) -#define FSL_EIS_MAS4_X0D FSL_EIS_MAS2_X0 -#define FSL_EIS_MAS4_X1D FSL_EIS_MAS2_X1 -#define FSL_EIS_MAS4_WD FSL_EIS_MAS2_W -#define FSL_EIS_MAS4_ID FSL_EIS_MAS2_I -#define FSL_EIS_MAS4_MD FSL_EIS_MAS2_M -#define FSL_EIS_MAS4_GD FSL_EIS_MAS2_G -#define FSL_EIS_MAS4_ED FSL_EIS_MAS2_E - -#define FSL_EIS_MAS5 629 - -#define FSL_EIS_MAS6 630 -#define FSL_EIS_MAS6_SPID0(n) ((0xff & (n)) << (63 - 55)) -#define FSL_EIS_MAS6_SAS (1 << (63 - 63)) - -#define FSL_EIS_MAS7 944 - -#define FSL_EIS_MAS8 341 - -#define FSL_EIS_MMUCFG 1015 -#define FSL_EIS_MMUCSR0 1012 -#define FSL_EIS_PID0 48 -#define FSL_EIS_PID1 633 -#define FSL_EIS_PID2 634 -#define FSL_EIS_TLB0CFG 688 -#define FSL_EIS_TLB1CFG 689 - -/* Freescale Book E Implementation Standards (EIS): L1 Cache */ - -#define FSL_EIS_L1CFG0 515 -#define FSL_EIS_L1CFG1 516 -#define FSL_EIS_L1CSR0 1010 -#define FSL_EIS_L1CSR0_CFI (1 << (63 - 62)) -#define FSL_EIS_L1CSR1 1011 -#define FSL_EIS_L1CSR1_ICFI (1 << (63 - 62)) - -/* Freescale Book E Implementation Standards (EIS): L2 Cache */ - -#define FSL_EIS_L2CFG0 519 -#define FSL_EIS_L2CSR0 1017 -#define FSL_EIS_L2CSR0_L2FI (1 << (63 - 42)) -#define FSL_EIS_L2CSR0_L2FL (1 << (63 - 52)) -#define FSL_EIS_L2CSR1 1018 - -/* Freescale Book E Implementation Standards (EIS): Timer */ - -#define FSL_EIS_ATBL 526 -#define FSL_EIS_ATBU 527 - -/* Freescale Book E Implementation Standards (EIS): Interrupt */ - -#define FSL_EIS_MCAR 573 -#define FSL_EIS_DSRR0 574 -#define FSL_EIS_DSRR1 575 -#define FSL_EIS_EPR 702 - -/* Freescale Book E Implementation Standards (EIS): Signal Processing Engine (SPE) */ - -#define FSL_EIS_SPEFSCR 512 - -/* Freescale Book E Implementation Standards (EIS): Software-Use SPRs */ - -#define FSL_EIS_SPRG8 604 -#define FSL_EIS_SPRG9 605 - -/* Freescale Book E Implementation Standards (EIS): Debug */ - -#define FSL_EIS_DBCR3 561 -#define FSL_EIS_DBCR4 563 -#define FSL_EIS_DBCR5 564 -#define FSL_EIS_DBCR6 603 -#define FSL_EIS_DBCNT 562 - -/** - * @brief Default value for the interrupt disable mask. - * - * The interrupt disable mask is stored in the global symbol - * _PPC_INTERRUPT_DISABLE_MASK. - */ -#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE - -#ifndef ASM - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define _CPU_MSR_GET( _msr_value ) \ - do { \ - _msr_value = 0; \ - __asm__ volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ - } while (0) - -#define _CPU_MSR_SET( _msr_value ) \ -{ __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } - -/** - * @brief A global symbol used to disable interrupts in the MSR. - * - * A one bit means that this bit should be cleared. - */ -extern char _PPC_INTERRUPT_DISABLE_MASK[]; - -static inline uint32_t ppc_interrupt_get_disable_mask( void ) -{ - return (uint32_t) (uintptr_t) _PPC_INTERRUPT_DISABLE_MASK; -} - -static inline uint32_t ppc_interrupt_disable( void ) -{ - uint32_t level; - -#if defined(__PPC_CPU_E6500__) - __asm__ volatile ( - "mfmsr %0;" - "wrteei 0" - : "=r" (level) - ); -#else - uint32_t mask; - - __asm__ volatile ( - "mfmsr %0;" - "lis %1, _PPC_INTERRUPT_DISABLE_MASK@h;" - "ori %1, %1, _PPC_INTERRUPT_DISABLE_MASK@l;" - "andc %1, %0, %1;" - "mtmsr %1" - : "=r" (level), "=r" (mask) - ); -#endif - - return level; -} - -static inline void ppc_interrupt_enable( uint32_t level ) -{ -#if defined(__PPC_CPU_E6500__) - __asm__ volatile ( - "wrtee %0" - : - : "r" (level) - ); -#else - __asm__ volatile ( - "mtmsr %0" - : - : "r" (level) - ); -#endif -} - -static inline void ppc_interrupt_flash( uint32_t level ) -{ - uint32_t current_level; - - __asm__ volatile ( - "mfmsr %0;" - "mtmsr %1;" - "mtmsr %0" - : "=&r" (current_level) - : "r" (level) - ); -} - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - _isr_cookie = ppc_interrupt_disable(); \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _isr_cookie is not modified. - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - ppc_interrupt_enable(_isr_cookie) - -/* - * This temporarily restores the interrupt to _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _isr_cookie is not - * modified. - * - * NOTE: The version being used is not very optimized but it does - * not trip a problem in gcc where the disable mask does not - * get loaded. Check this for future (post 10/97 gcc versions. - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - ppc_interrupt_flash(_isr_cookie) - -/* end of ISR handler macros */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* _RTEMS_POWERPC_REGISTERS_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h deleted file mode 100644 index 8c0f200641..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h +++ /dev/null @@ -1,1257 +0,0 @@ -/** - * @file - * - * @brief PowerPC CPU Department Source - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * COPYRIGHT (c) 1995 i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>. - * - * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL). - * - * Copyright (c) 2010, 2017 embedded brains GmbH. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#include <rtems/score/types.h> -#include <rtems/score/powerpc.h> -#include <rtems/powerpc/registers.h> - -#ifndef ASM - #include <string.h> /* for memset() */ -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/* conditional compilation parameters */ - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -#define CPU_CACHE_LINE_BYTES PPC_STRUCTURE_ALIGNMENT - -#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "PPC_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( PPC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#else -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * PowerPC Note: It appears the GCC can implicitly generate FPU - * and Altivec instructions when you least expect them. So make - * all tasks floating point. - */ - -#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * Processor defined structures required for cpukit/score. - */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -#ifndef __SPE__ - #define PPC_GPR_TYPE uintptr_t - #if defined(__powerpc64__) - #define PPC_GPR_SIZE 8 - #define PPC_GPR_LOAD ld - #define PPC_GPR_STORE std - #else - #define PPC_GPR_SIZE 4 - #define PPC_GPR_LOAD lwz - #define PPC_GPR_STORE stw - #endif -#else - #define PPC_GPR_TYPE uint64_t - #define PPC_GPR_SIZE 8 - #define PPC_GPR_LOAD evldd - #define PPC_GPR_STORE evstdd -#endif - -#if defined(__powerpc64__) - #define PPC_REG_SIZE 8 - #define PPC_REG_LOAD ld - #define PPC_REG_STORE std - #define PPC_REG_STORE_UPDATE stdu - #define PPC_REG_CMP cmpd -#else - #define PPC_REG_SIZE 4 - #define PPC_REG_LOAD lwz - #define PPC_REG_STORE stw - #define PPC_REG_STORE_UPDATE stwu - #define PPC_REG_CMP cmpw -#endif - -#ifndef ASM - -/* - * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according - * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 - - * Linux and Embedded") - */ -typedef struct { - uint32_t msr; - uint32_t cr; - uintptr_t gpr1; - uintptr_t lr; - PPC_GPR_TYPE gpr14; - PPC_GPR_TYPE gpr15; - PPC_GPR_TYPE gpr16; - PPC_GPR_TYPE gpr17; - PPC_GPR_TYPE gpr18; - PPC_GPR_TYPE gpr19; - PPC_GPR_TYPE gpr20; - PPC_GPR_TYPE gpr21; - PPC_GPR_TYPE gpr22; - PPC_GPR_TYPE gpr23; - PPC_GPR_TYPE gpr24; - PPC_GPR_TYPE gpr25; - PPC_GPR_TYPE gpr26; - PPC_GPR_TYPE gpr27; - PPC_GPR_TYPE gpr28; - PPC_GPR_TYPE gpr29; - PPC_GPR_TYPE gpr30; - PPC_GPR_TYPE gpr31; - uint32_t isr_dispatch_disable; - uint32_t reserved_for_alignment; - #if defined(PPC_MULTILIB_ALTIVEC) - uint8_t v20[16]; - uint8_t v21[16]; - uint8_t v22[16]; - uint8_t v23[16]; - uint8_t v24[16]; - uint8_t v25[16]; - uint8_t v26[16]; - uint8_t v27[16]; - uint8_t v28[16]; - uint8_t v29[16]; - uint8_t v30[16]; - uint8_t v31[16]; - uint32_t vrsave; - #elif defined(__ALTIVEC__) - /* - * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave - * and padding to ensure cache-alignment. Unfortunately, we can't verify - * the cache line size here in the cpukit but altivec support code will - * produce an error if this is ever different from 32 bytes. - * - * Note: it is the BSP/CPU-support's responsibility to save/restore - * volatile vregs across interrupts and exceptions. - */ - uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE]; - #endif - #if defined(PPC_MULTILIB_FPU) - double f14; - double f15; - double f16; - double f17; - double f18; - double f19; - double f20; - double f21; - double f22; - double f23; - double f24; - double f25; - double f26; - double f27; - double f28; - double f29; - double f30; - double f31; - #endif - /* - * The following items are at the structure end, so that we can use dcbz for - * the previous items to optimize the context switch. We must not set the - * following items to zero via the dcbz. - */ - uintptr_t tp; - #if defined(RTEMS_SMP) - volatile uint32_t is_executing; - #endif -} ppc_context; - -typedef struct { - uint8_t context [ - PPC_DEFAULT_CACHE_LINE_SIZE - + sizeof(ppc_context) - + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0 - ? 0 - : PPC_DEFAULT_CACHE_LINE_SIZE - - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE) - ]; -} Context_Control; - -static inline ppc_context *ppc_get_context( const Context_Control *context ) -{ - uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE; - uintptr_t mask = clsz - 1; - uintptr_t addr = (uintptr_t) context; - - return (ppc_context *) ((addr & ~mask) + clsz); -} - -#define _CPU_Context_Get_SP( _context ) \ - ppc_get_context(_context)->gpr1 - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return ppc_get_context(context)->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - ppc_get_context(context)->is_executing = is_executing; - } -#endif -#endif /* ASM */ - -#define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE) -#define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) -#define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 8) -#define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + PPC_REG_SIZE + 8) - -#define PPC_CONTEXT_GPR_OFFSET( gpr ) \ - (((gpr) - 14) * PPC_GPR_SIZE + \ - PPC_DEFAULT_CACHE_LINE_SIZE + 8 + 2 * PPC_REG_SIZE) - -#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) -#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) -#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 ) -#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 ) -#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 ) -#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 ) -#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 ) -#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 ) -#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 ) -#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 ) -#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 ) -#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 ) -#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 ) -#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 ) -#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 ) -#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 ) -#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 ) -#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 ) -#define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE PPC_CONTEXT_GPR_OFFSET( 32 ) - -#ifdef PPC_MULTILIB_ALTIVEC - #define PPC_CONTEXT_OFFSET_V( v ) \ - ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8) - #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 ) - #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 ) - #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 ) - #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 ) - #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 ) - #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 ) - #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 ) - #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 ) - #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 ) - #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 ) - #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 ) - #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 ) - #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 ) - #define PPC_CONTEXT_OFFSET_F( f ) \ - ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_VRSAVE + 8 ) -#else - #define PPC_CONTEXT_OFFSET_F( f ) \ - ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 ) -#endif - -#ifdef PPC_MULTILIB_FPU - #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 ) - #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 ) - #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 ) - #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 ) - #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 ) - #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 ) - #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 ) - #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 ) - #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 ) - #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 ) - #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 ) - #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 ) - #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 ) - #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 ) - #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 ) - #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 ) - #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 ) - #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 ) -#endif - -#if defined(PPC_MULTILIB_FPU) - #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 ) -#elif defined(PPC_MULTILIB_ALTIVEC) - #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4) -#elif defined(__ALTIVEC__) - #define PPC_CONTEXT_VOLATILE_SIZE \ - (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8 \ - + 16 * 12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE) -#else - #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8) -#endif - -#define PPC_CONTEXT_OFFSET_TP PPC_CONTEXT_VOLATILE_SIZE - -#ifdef RTEMS_SMP - #define PPC_CONTEXT_OFFSET_IS_EXECUTING \ - (PPC_CONTEXT_OFFSET_TP + PPC_REG_SIZE) -#endif - -#ifndef ASM -typedef struct { -#if (PPC_HAS_FPU == 1) - /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over - * procedure calls. However, this would mean that the interrupt - * frame had to hold f0-f13, and the fpscr. And as the majority - * of tasks will not have an FP context, we will save the whole - * context here. - */ -#if (PPC_HAS_DOUBLE == 1) - double f[32]; - uint64_t fpscr; -#else - float f[32]; - uint32_t fpscr; -#endif -#endif /* (PPC_HAS_FPU == 1) */ -} Context_Control_fp; - -#endif /* ASM */ - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * PowerPC Specific Information: - * - * The PowerPC and x86 were the first to use the PIC interrupt model. - * They do not use the simple vectored interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Note, however that compilers may use floating point registers/ - * instructions for optimization or they may save/restore FP registers - * on the stack. You must not use deferred switching in these cases - * and on the PowerPC attempting to do so will raise a "FP unavailable" - * exception. - */ -/* - * ACB Note: This could make debugging tricky.. - */ - -/* conservative setting (FALSE); probably doesn't affect performance too much */ -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/* - * Processor defined structures required for cpukit/score. - */ - -#ifndef ASM - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -/* EXTERN Context_Control_fp _CPU_Null_fp_context; */ - -#endif /* ndef ASM */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * (Optional) # of bytes for libmisc/stackchk to check - * If not specifed, then it defaults to something reasonable - * for most architectures. - */ - -#define CPU_STACK_CHECK_PATTERN_INITIALIZER \ - { 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ - 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06 } - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. Note that - * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level - * being maintained (e.g. watchdog queues). - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * ISR handler macros - */ - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _isr_cookie. - */ - -#ifndef ASM - -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return ( level & MSR_EE ) != 0; -} - -static inline uint32_t _CPU_ISR_Get_level( void ) -{ - register unsigned int msr; - _CPU_MSR_GET(msr); - if (msr & MSR_EE) return 0; - else return 1; -} - -static inline void _CPU_ISR_Set_level( uint32_t level ) -{ - register unsigned int msr; - _CPU_MSR_GET(msr); - if (!(level & CPU_MODES_INTERRUPT_MASK)) { - msr |= ppc_interrupt_get_disable_mask(); - } - else { - msr &= ~ppc_interrupt_get_disable_mask(); - } - _CPU_MSR_SET(msr); -} - -#endif /* ASM */ - -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - ppc_interrupt_disable(); \ - __asm__ volatile ( \ - "mr 3, %0\n" \ - "mr 4, %1\n" \ - "1:\n" \ - "b 1b\n" \ - : \ - : "r" (_source), "r" (_error) \ - : "memory" \ - ); \ - } while ( 0 ) - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#if defined(__powerpc64__) -#define CPU_SIZEOF_POINTER 8 -#else -#define CPU_SIZEOF_POINTER 4 -#endif - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) - -#ifndef ASM -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t swapped; - - __asm__ volatile("rlwimi %0,%1,8,24,31;" - "rlwimi %0,%1,24,16,23;" - "rlwimi %0,%1,8,8,15;" - "rlwimi %0,%1,24,0,7;" : - "=&r" ((swapped)) : "r" ((value))); - - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -static inline CPU_Counter_ticks _CPU_Counter_read( void ) -{ - CPU_Counter_ticks value; - -#if defined(__PPC_CPU_E6500__) - /* Use Alternate Time Base */ - __asm__ volatile( "mfspr %0, 526" : "=r" (value) ); -#else - __asm__ volatile( "mfspr %0, 268" : "=r" (value) ); -#endif - - return value; -} - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - - -#ifndef ASM -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_base, - size_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - memset( *(_destination), 0, sizeof( **(_destination) ) ) - -/* end of Context handler macros */ -#endif /* ASM */ - -#ifndef ASM -/* Bitfield handler macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_Bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ - "1" ((_value))); \ - (_output) = (_output) - 16; \ - } - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x8000u >> (_bit_number) ) - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ -#endif /* ASM */ - -/* functions */ - -#ifndef ASM - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -#ifdef RTEMS_SMP - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - uint32_t pir; - - /* Use Book E Processor ID Register (PIR) */ - __asm__ volatile ( - "mfspr %[pir], 286" - : [pir] "=&r" (pir) - ); - - return pir; - } - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } -#endif - -typedef struct { - uintptr_t EXC_SRR0; - uintptr_t EXC_SRR1; - uint32_t _EXC_number; - uint32_t RESERVED_FOR_ALIGNMENT_0; - uint32_t EXC_CR; - uint32_t EXC_XER; - uintptr_t EXC_CTR; - uintptr_t EXC_LR; - uintptr_t RESERVED_FOR_ALIGNMENT_1; - #ifdef __SPE__ - uint32_t EXC_SPEFSCR; - uint64_t EXC_ACC; - #endif - PPC_GPR_TYPE GPR0; - PPC_GPR_TYPE GPR1; - PPC_GPR_TYPE GPR2; - PPC_GPR_TYPE GPR3; - PPC_GPR_TYPE GPR4; - PPC_GPR_TYPE GPR5; - PPC_GPR_TYPE GPR6; - PPC_GPR_TYPE GPR7; - PPC_GPR_TYPE GPR8; - PPC_GPR_TYPE GPR9; - PPC_GPR_TYPE GPR10; - PPC_GPR_TYPE GPR11; - PPC_GPR_TYPE GPR12; - PPC_GPR_TYPE GPR13; - PPC_GPR_TYPE GPR14; - PPC_GPR_TYPE GPR15; - PPC_GPR_TYPE GPR16; - PPC_GPR_TYPE GPR17; - PPC_GPR_TYPE GPR18; - PPC_GPR_TYPE GPR19; - PPC_GPR_TYPE GPR20; - PPC_GPR_TYPE GPR21; - PPC_GPR_TYPE GPR22; - PPC_GPR_TYPE GPR23; - PPC_GPR_TYPE GPR24; - PPC_GPR_TYPE GPR25; - PPC_GPR_TYPE GPR26; - PPC_GPR_TYPE GPR27; - PPC_GPR_TYPE GPR28; - PPC_GPR_TYPE GPR29; - PPC_GPR_TYPE GPR30; - PPC_GPR_TYPE GPR31; - uintptr_t RESERVED_FOR_ALIGNMENT_2; - #ifdef PPC_MULTILIB_ALTIVEC - uint32_t VRSAVE; - uint32_t RESERVED_FOR_ALIGNMENT_3[3]; - - /* This field must take stvewx/lvewx requirements into account */ - uint32_t RESERVED_FOR_ALIGNMENT_4[3]; - uint32_t VSCR; - - uint8_t V0[16]; - uint8_t V1[16]; - uint8_t V2[16]; - uint8_t V3[16]; - uint8_t V4[16]; - uint8_t V5[16]; - uint8_t V6[16]; - uint8_t V7[16]; - uint8_t V8[16]; - uint8_t V9[16]; - uint8_t V10[16]; - uint8_t V11[16]; - uint8_t V12[16]; - uint8_t V13[16]; - uint8_t V14[16]; - uint8_t V15[16]; - uint8_t V16[16]; - uint8_t V17[16]; - uint8_t V18[16]; - uint8_t V19[16]; - uint8_t V20[16]; - uint8_t V21[16]; - uint8_t V22[16]; - uint8_t V23[16]; - uint8_t V24[16]; - uint8_t V25[16]; - uint8_t V26[16]; - uint8_t V27[16]; - uint8_t V28[16]; - uint8_t V29[16]; - uint8_t V30[16]; - uint8_t V31[16]; - #endif - #ifdef PPC_MULTILIB_FPU - double F0; - double F1; - double F2; - double F3; - double F4; - double F5; - double F6; - double F7; - double F8; - double F9; - double F10; - double F11; - double F12; - double F13; - double F14; - double F15; - double F16; - double F17; - double F18; - double F19; - double F20; - double F21; - double F22; - double F23; - double F24; - double F25; - double F26; - double F27; - double F28; - double F29; - double F30; - double F31; - uint64_t FPSCR; - uint64_t RESERVED_FOR_ALIGNMENT_5; - #endif -} CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* - * _CPU_Initialize_altivec() - * - * Global altivec-related initialization. - */ -void -_CPU_Initialize_altivec(void); - -/* - * _CPU_Context_switch_altivec - * - * This routine switches the altivec contexts passed to it. - */ - -void -_CPU_Context_switch_altivec( - ppc_context *from, - ppc_context *to -); - -/* - * _CPU_Context_restore_altivec - * - * This routine restores the altivec context passed to it. - */ - -void -_CPU_Context_restore_altivec( - ppc_context *ctxt -); - -/* - * _CPU_Context_initialize_altivec - * - * This routine initializes the altivec context passed to it. - */ - -void -_CPU_Context_initialize_altivec( - ppc_context *ctxt -); - -void _CPU_Fatal_error( - uint32_t _error -); - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpuatomic.h b/cpukit/score/cpu/powerpc/rtems/score/cpuatomic.h deleted file mode 100644 index 598ee76b20..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/cpuatomic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include <rtems/score/cpustdatomic.h> - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h b/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h deleted file mode 100644 index 792a8111ad..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h +++ /dev/null @@ -1,247 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> - * - * Copyright (c) 2009, 2017 embedded brains GmbH - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include <rtems/score/cpu.h> - -/* Exception stack frame -> BSP_Exception_frame */ -#ifdef __powerpc64__ - #define FRAME_LINK_SPACE 32 -#else - #define FRAME_LINK_SPACE 8 -#endif - -#define SRR0_FRAME_OFFSET FRAME_LINK_SPACE -#define SRR1_FRAME_OFFSET (SRR0_FRAME_OFFSET + PPC_REG_SIZE) -#define EXCEPTION_NUMBER_OFFSET (SRR1_FRAME_OFFSET + PPC_REG_SIZE) -#define PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET (EXCEPTION_NUMBER_OFFSET + 4) -#define EXC_CR_OFFSET (EXCEPTION_NUMBER_OFFSET + 8) -#define EXC_XER_OFFSET (EXC_CR_OFFSET + 4) -#define EXC_CTR_OFFSET (EXC_XER_OFFSET + 4) -#define EXC_LR_OFFSET (EXC_CTR_OFFSET + PPC_REG_SIZE) -#define PPC_EXC_INTERRUPT_FRAME_OFFSET (EXC_LR_OFFSET + PPC_REG_SIZE) - -#ifndef __SPE__ - #define PPC_EXC_GPR_OFFSET(gpr) \ - ((gpr) * PPC_GPR_SIZE + PPC_EXC_INTERRUPT_FRAME_OFFSET + PPC_REG_SIZE) - #define PPC_EXC_GPR3_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(3) - #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU) - #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) - #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) - #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4) - #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_VR_OFFSET(32)) - #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32) - #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34) - #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12) - #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4) - #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_MIN_VR_OFFSET(20)) - #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14) - #define CPU_INTERRUPT_FRAME_SIZE \ - (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE) - #elif defined(PPC_MULTILIB_ALTIVEC) - #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) - #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) - #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4) - #define PPC_EXC_FRAME_SIZE PPC_EXC_VR_OFFSET(32) - #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12) - #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4) - #define CPU_INTERRUPT_FRAME_SIZE \ - (PPC_EXC_MIN_VR_OFFSET(20) + PPC_STACK_RED_ZONE_SIZE) - #elif defined(PPC_MULTILIB_FPU) - #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(33)) - #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32) - #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34) - #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(13)) - #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14) - #define CPU_INTERRUPT_FRAME_SIZE \ - (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE) - #else - #define PPC_EXC_FRAME_SIZE PPC_EXC_GPR_OFFSET(33) - #define CPU_INTERRUPT_FRAME_SIZE \ - (PPC_EXC_GPR_OFFSET(13) + PPC_STACK_RED_ZONE_SIZE) - #endif -#else - #define PPC_EXC_SPEFSCR_OFFSET 44 - #define PPC_EXC_ACC_OFFSET 48 - #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 56) - #define PPC_EXC_GPR3_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(3) + 4) - #define CPU_INTERRUPT_FRAME_SIZE (160 + PPC_STACK_RED_ZONE_SIZE) - #define PPC_EXC_FRAME_SIZE 320 -#endif - -#define GPR0_OFFSET PPC_EXC_GPR_OFFSET(0) -#define GPR1_OFFSET PPC_EXC_GPR_OFFSET(1) -#define GPR2_OFFSET PPC_EXC_GPR_OFFSET(2) -#define GPR3_OFFSET PPC_EXC_GPR_OFFSET(3) -#define GPR4_OFFSET PPC_EXC_GPR_OFFSET(4) -#define GPR5_OFFSET PPC_EXC_GPR_OFFSET(5) -#define GPR6_OFFSET PPC_EXC_GPR_OFFSET(6) -#define GPR7_OFFSET PPC_EXC_GPR_OFFSET(7) -#define GPR8_OFFSET PPC_EXC_GPR_OFFSET(8) -#define GPR9_OFFSET PPC_EXC_GPR_OFFSET(9) -#define GPR10_OFFSET PPC_EXC_GPR_OFFSET(10) -#define GPR11_OFFSET PPC_EXC_GPR_OFFSET(11) -#define GPR12_OFFSET PPC_EXC_GPR_OFFSET(12) -#define GPR13_OFFSET PPC_EXC_GPR_OFFSET(13) -#define GPR14_OFFSET PPC_EXC_GPR_OFFSET(14) -#define GPR15_OFFSET PPC_EXC_GPR_OFFSET(15) -#define GPR16_OFFSET PPC_EXC_GPR_OFFSET(16) -#define GPR17_OFFSET PPC_EXC_GPR_OFFSET(17) -#define GPR18_OFFSET PPC_EXC_GPR_OFFSET(18) -#define GPR19_OFFSET PPC_EXC_GPR_OFFSET(19) -#define GPR20_OFFSET PPC_EXC_GPR_OFFSET(20) -#define GPR21_OFFSET PPC_EXC_GPR_OFFSET(21) -#define GPR22_OFFSET PPC_EXC_GPR_OFFSET(22) -#define GPR23_OFFSET PPC_EXC_GPR_OFFSET(23) -#define GPR24_OFFSET PPC_EXC_GPR_OFFSET(24) -#define GPR25_OFFSET PPC_EXC_GPR_OFFSET(25) -#define GPR26_OFFSET PPC_EXC_GPR_OFFSET(26) -#define GPR27_OFFSET PPC_EXC_GPR_OFFSET(27) -#define GPR28_OFFSET PPC_EXC_GPR_OFFSET(28) -#define GPR29_OFFSET PPC_EXC_GPR_OFFSET(29) -#define GPR30_OFFSET PPC_EXC_GPR_OFFSET(30) -#define GPR31_OFFSET PPC_EXC_GPR_OFFSET(31) - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifdef RTEMS_SMP - -/* Use SPRG0 for the per-CPU control of the current processor */ -#define PPC_PER_CPU_CONTROL_REGISTER 272 - -#endif /* RTEMS_SMP */ - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - uintptr_t FRAME_SP; - #ifdef __powerpc64__ - uint32_t FRAME_CR; - uint32_t FRAME_RESERVED; - #endif - uintptr_t FRAME_LR; - #ifdef __powerpc64__ - uintptr_t FRAME_TOC; - #endif - uintptr_t EXC_SRR0; - uintptr_t EXC_SRR1; - uint32_t RESERVED_FOR_ALIGNMENT_0; - uint32_t EXC_INTERRUPT_ENTRY_INSTANT; - uint32_t EXC_CR; - uint32_t EXC_XER; - uintptr_t EXC_CTR; - uintptr_t EXC_LR; - uintptr_t EXC_INTERRUPT_FRAME; - #ifdef __SPE__ - uint32_t EXC_SPEFSCR; - uint64_t EXC_ACC; - #endif - PPC_GPR_TYPE GPR0; - PPC_GPR_TYPE GPR1; - PPC_GPR_TYPE GPR2; - PPC_GPR_TYPE GPR3; - PPC_GPR_TYPE GPR4; - PPC_GPR_TYPE GPR5; - PPC_GPR_TYPE GPR6; - PPC_GPR_TYPE GPR7; - PPC_GPR_TYPE GPR8; - PPC_GPR_TYPE GPR9; - PPC_GPR_TYPE GPR10; - PPC_GPR_TYPE GPR11; - PPC_GPR_TYPE GPR12; - #ifdef PPC_MULTILIB_ALTIVEC - /* This field must take stvewx/lvewx requirements into account */ - uint32_t RESERVED_FOR_ALIGNMENT_3[3]; - uint32_t VSCR; - - uint8_t V0[16]; - uint8_t V1[16]; - uint8_t V2[16]; - uint8_t V3[16]; - uint8_t V4[16]; - uint8_t V5[16]; - uint8_t V6[16]; - uint8_t V7[16]; - uint8_t V8[16]; - uint8_t V9[16]; - uint8_t V10[16]; - uint8_t V11[16]; - uint8_t V12[16]; - uint8_t V13[16]; - uint8_t V14[16]; - uint8_t V15[16]; - uint8_t V16[16]; - uint8_t V17[16]; - uint8_t V18[16]; - uint8_t V19[16]; - #endif - #ifdef PPC_MULTILIB_FPU - double F0; - double F1; - double F2; - double F3; - double F4; - double F5; - double F6; - double F7; - double F8; - double F9; - double F10; - double F11; - double F12; - double F13; - uint64_t FPSCR; - uint64_t RESERVED_FOR_ALIGNMENT_4; - #endif - #if PPC_STACK_RED_ZONE_SIZE > 0 - uint8_t RED_ZONE[ PPC_STACK_RED_ZONE_SIZE ]; - #endif -} CPU_Interrupt_frame; - -#ifdef RTEMS_SMP - -static inline struct Per_CPU_Control *_PPC_Get_current_per_CPU_control( void ) -{ - struct Per_CPU_Control *cpu_self; - - __asm__ volatile ( - "mfspr %0, " RTEMS_XSTRING( PPC_PER_CPU_CONTROL_REGISTER ) - : "=r" ( cpu_self ) - ); - - return cpu_self; -} - -#define _CPU_Get_current_per_CPU_control() _PPC_Get_current_per_CPU_control() - -#endif /* RTEMS_SMP */ - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/powerpc.h b/cpukit/score/cpu/powerpc/rtems/score/powerpc.h deleted file mode 100644 index 88ee0020e6..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/powerpc.h +++ /dev/null @@ -1,187 +0,0 @@ -/** - * @file - * - * @brief IBM/Motorola Power Pc Definitions - * - * This file contains definitions for the IBM/Motorola PowerPC - * family members. - */ - -/* - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> - * MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk> - * Surrey Satellite Technology Limited - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - */ - - -#ifndef _RTEMS_SCORE_POWERPC_H -#define _RTEMS_SCORE_POWERPC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "PowerPC" - -/* - * This file contains the information required to build - * RTEMS for the PowerPC family. - */ - -/* Generic ppc */ - -#ifdef _SOFT_FLOAT -#define CPU_MODEL_NAME "Generic (no FPU)" -#elif defined(__NO_FPRS__) || defined(__SPE__) -#define CPU_MODEL_NAME "Generic (E500/float-gprs/SPE)" -#else -#define CPU_MODEL_NAME "Generic (classic FPU)" -#endif - -#ifdef __PPC_CPU_E6500__ -#define PPC_DEFAULT_CACHE_LINE_POWER 6 -#else -#define PPC_DEFAULT_CACHE_LINE_POWER 5 -#endif - -#define PPC_DEFAULT_CACHE_LINE_SIZE (1 << PPC_DEFAULT_CACHE_LINE_POWER) - -#define PPC_STRUCTURE_ALIGNMENT PPC_DEFAULT_CACHE_LINE_SIZE - -/* - * Application binary interfaces. - * - * PPC_ABI MUST be defined as one of these. - * Only big endian is currently supported. - */ - -/* - * SVR4 ABI - */ -#define PPC_ABI_SVR4 2 -/* - * Embedded ABI - */ -#define PPC_ABI_EABI 3 - -/* - * Default to the EABI used by current GNU tools - */ - -#ifndef PPC_ABI -#define PPC_ABI PPC_ABI_EABI -#endif - -/* - * Use worst case stack alignment. For the EABI an 8-byte alignment would be - * sufficient. - */ - -#define PPC_STACK_ALIGN_POWER 4 -#define PPC_STACK_ALIGNMENT (1 << PPC_STACK_ALIGN_POWER) - -/* - * Assume PPC_HAS_FPU to be a synonym for _SOFT_FLOAT. - */ - -#if defined(_SOFT_FLOAT) \ - || defined(__NO_FPRS__) /* e500 has unified integer/FP registers */ \ - || defined(__PPC_CPU_E6500__) -#define PPC_HAS_FPU 0 -#else -#define PPC_HAS_FPU 1 -#endif - -#if defined(__PPC_CPU_E6500__) && defined(__ALTIVEC__) -#define PPC_MULTILIB_ALTIVEC -#endif - -#if defined(__PPC_CPU_E6500__) && !defined(_SOFT_FLOAT) -#define PPC_MULTILIB_FPU -#endif - -#ifdef PPC_MULTILIB_ALTIVEC -#define PPC_ALIGNMENT 16 -#else -#define PPC_ALIGNMENT 8 -#endif - -#ifdef __powerpc64__ -#define PPC_STACK_RED_ZONE_SIZE 512 -#else -#define PPC_STACK_RED_ZONE_SIZE 0 -#endif - -/* - * Unless specified above, If the model has FP support, it is assumed to - * support doubles (8-byte floating point numbers). - * - * If the model does NOT have FP support, then the model does - * NOT have double length FP registers. - */ - -#if (PPC_HAS_FPU) -#define PPC_HAS_DOUBLE 1 -#else -#define PPC_HAS_DOUBLE 0 -#endif - -/* - * Assemblers. - * PPC_ASM MUST be defined as one of these. - * - * PPC_ASM_ELF: ELF assembler. Currently used for all ABIs. - * - * NOTE: Only PPC_ABI_ELF is currently fully supported. - * - * Also NOTE: cpukit doesn't need this but asm.h which is defined - * in cpukit for consistency with other ports does. - */ - -#define PPC_ASM_ELF 0 - -/* - * Default to the assembler format used by the current GNU tools. - */ -#define PPC_ASM PPC_ASM_ELF - - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_POWERPC_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/types.h b/cpukit/score/cpu/powerpc/rtems/score/types.h deleted file mode 100644 index cdab30234d..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/types.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file - * - * @brief PowerPC CPU Type Definitions - * - * This include file contains type definitions pertaining to the PowerPC - * processor family. - */ - -/* - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cputypes.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef void ppc_isr; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif |