diff options
Diffstat (limited to 'cpukit/score/cpu/or1k/include/rtems')
4 files changed, 27 insertions, 51 deletions
diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h index 83d46010ba..ce1aa301b3 100644 --- a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h @@ -316,7 +316,7 @@ static inline void or1k_interrupt_enable(uint32_t level) _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \ } while(0) -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return ( level & CPU_OR1K_SPR_SR ) != 0; } @@ -468,7 +468,7 @@ void _CPU_ISR_install_raw_handler( typedef void ( *CPU_ISR_handler )( uint32_t ); -RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector( +static inline void _CPU_ISR_install_vector( uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler @@ -578,14 +578,6 @@ uint32_t _CPU_Counter_frequency( void ); CPU_Counter_ticks _CPU_Counter_read( void ); -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - /** Type that can store a 32-bit integer or a pointer. */ typedef uintptr_t CPU_Uint32ptr; diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/or1k/include/rtems/score/cpuatomic.h deleted file mode 100644 index 01bb99cda3..0000000000 --- a/cpukit/score/cpu/or1k/include/rtems/score/cpuatomic.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * COPYRIGHT (c) 2012-2013 Deng Hengyi. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H -#define _RTEMS_SCORE_ATOMIC_CPU_H - -#include <rtems/score/cpustdatomic.h> - -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h index 37cd1db436..9b58b1b77a 100644 --- a/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/or1k/include/rtems/score/cpuimpl.h @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2013 embedded brains GmbH + * Copyright (c) 2013 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -48,6 +48,8 @@ #define CPU_PER_CPU_CONTROL_SIZE 0 +#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10 + #ifndef ASM #ifdef __cplusplus @@ -60,16 +62,31 @@ void _CPU_Context_volatile_clobber( uintptr_t pattern ); void _CPU_Context_validate( uintptr_t pattern ); -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "l.nop" ); } +static inline void _CPU_Use_thread_local_storage( + const Context_Control *context +) +{ + (void) context; +} + +static inline void *_CPU_Get_TLS_thread_pointer( + const Context_Control *context +) +{ + (void) context; + return NULL; +} + #ifdef __cplusplus } #endif diff --git a/cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h b/cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h index c7618c9355..58db24fbbd 100644 --- a/cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h +++ b/cpukit/score/cpu/or1k/include/rtems/score/or1k-utility.h @@ -345,7 +345,7 @@ static inline uint32_t _OR1K_mfspr(uint32_t reg) { uint32_t spr_value; - asm volatile ( + __asm__ volatile ( "l.mfspr %0, %1, 0;\n\t" : "=r" (spr_value) : "r" (reg)); @@ -354,7 +354,7 @@ static inline uint32_t _OR1K_mfspr(uint32_t reg) static inline void _OR1K_mtspr(uint32_t reg, uint32_t value) { - asm volatile ( + __asm__ volatile ( "l.mtspr %1, %0, 0;\n\t" :: "r" (value), "r" (reg) ); @@ -386,12 +386,12 @@ static inline void _OR1K_mtspr(uint32_t reg, uint32_t value) static inline void _OR1K_Sync_mem( void ) { - asm volatile("l.msync"); + __asm__ volatile("l.msync"); } static inline void _OR1K_Sync_pipeline( void ) { - asm volatile("l.psync"); + __asm__ volatile("l.psync"); } /** @@ -402,7 +402,7 @@ static inline void _OR1K_Sync_pipeline( void ) * */ #define _OR1KSIM_CPU_Halt() \ - asm volatile ("l.nop 0xc") + __asm__ volatile ("l.nop 0xc") #ifdef __cplusplus } |