diff options
Diffstat (limited to 'cpukit/score/cpu/no_cpu')
-rw-r--r-- | cpukit/score/cpu/no_cpu/cpucounterfrequency.c | 2 | ||||
-rw-r--r-- | cpukit/score/cpu/no_cpu/cpucounterread.c | 2 | ||||
-rw-r--r-- | cpukit/score/cpu/no_cpu/cpuidle.c | 18 | ||||
-rw-r--r-- | cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h | 44 | ||||
-rw-r--r-- | cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h | 42 |
5 files changed, 71 insertions, 37 deletions
diff --git a/cpukit/score/cpu/no_cpu/cpucounterfrequency.c b/cpukit/score/cpu/no_cpu/cpucounterfrequency.c index fcc4cdbc33..96a4078889 100644 --- a/cpukit/score/cpu/no_cpu/cpucounterfrequency.c +++ b/cpukit/score/cpu/no_cpu/cpucounterfrequency.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2018 embedded brains GmbH. All rights reserved. + * Copyright (c) 2018 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/no_cpu/cpucounterread.c b/cpukit/score/cpu/no_cpu/cpucounterread.c index f27784f9a7..f4e6e77fc1 100644 --- a/cpukit/score/cpu/no_cpu/cpucounterread.c +++ b/cpukit/score/cpu/no_cpu/cpucounterread.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2014 embedded brains GmbH. All rights reserved. + * Copyright (c) 2014 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/cpukit/score/cpu/no_cpu/cpuidle.c b/cpukit/score/cpu/no_cpu/cpuidle.c index 85ca01b7ca..dbaf109905 100644 --- a/cpukit/score/cpu/no_cpu/cpuidle.c +++ b/cpukit/score/cpu/no_cpu/cpuidle.c @@ -1,7 +1,16 @@ /* SPDX-License-Identifier: BSD-2-Clause */ +/** + * @file + * + * @ingroup RTEMSScoreCPU + * + * @brief This source file contains the implementation of the + * _CPU_Thread_Idle_body(). + */ + /* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -33,6 +42,13 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored ) { + /* + * This is a workaround for: + * + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108658 + */ + __asm__ volatile (""); + while ( true ) { /* Do nothing */ } diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h index 5403cc8a10..9ef6f43eb9 100644 --- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h @@ -554,7 +554,8 @@ extern Context_Control_fp _CPU_Null_fp_context; * @addtogroup RTEMSScoreCPUExampleContext * * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. + * that a "reasonable" small application should not have any problems. The + * size shall be a power of two. * * Port Specific Information: * @@ -695,7 +696,7 @@ extern Context_Control_fp _CPU_Null_fp_context; * @retval true Interrupts are enabled in the ISR level. * @retval false Otherwise. */ -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { return false; } @@ -1293,44 +1294,27 @@ static inline uint32_t CPU_swap_u32( typedef uint32_t CPU_Counter_ticks; /** - * @brief Returns the current CPU counter frequency in Hz. + * @brief Gets the current CPU counter frequency in Hz. * - * @return The current CPU counter frequency in Hz. + * @return Returns the current CPU counter frequency in Hz. */ uint32_t _CPU_Counter_frequency( void ); /** - * @brief Returns the current CPU counter value. + * @brief Gets the current CPU counter value. * - * A CPU counter is some free-running counter. It ticks usually with a - * frequency close to the CPU or system bus clock. The board support package - * must ensure that this function works before the RTEMS initialization. - * Otherwise invalid profiling statistics will be gathered. + * A CPU counter should be some monotonically increasing free-running counter. + * It ticks usually with a frequency close to the CPU or system bus clock. The + * counter should not be affected by power saving states so that it can be used + * for timestamps. The CPU counter should be initialized at the + * RTEMS_SYSINIT_CPU_COUNTER initialization step if necessary. If + * RTEMS_PROFILING is enabled, the CPU counter may have to work very early in + * the system initialization to avoid invalid profiling statistics. * - * @return The current CPU counter value. + * @return Returns the current CPU counter value. */ CPU_Counter_ticks _CPU_Counter_read( void ); -/** - * @brief Returns the difference between the second and first CPU counter - * value. - * - * This operation may be carried out as a modulo operation depending on the - * range of the CPU counter device. - * - * @param[in] second The second CPU counter value. - * @param[in] first The first CPU counter value. - * - * @return Returns second minus first modulo counter period. - */ -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - #ifdef RTEMS_SMP /** * @brief Performs CPU specific SMP initialization in the context of the boot diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h index 1eec4e6b7a..61f1ab7ba5 100644 --- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2013, 2016 embedded brains GmbH + * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -54,6 +54,24 @@ */ #define CPU_PER_CPU_CONTROL_SIZE 0 +/** + * @brief Defines the thread-local storage (TLS) variant. + * + * Use one of the following values: + * + * 10: The architecture uses Variant I and the TLS offsets emitted by the + * linker neglect the TCB (examples: nios2, m68k, microblaze, powerpc, + * riscv). The thread pointer directly references the thread-local data + * area. + * + * 11: The architecture uses Variant I and the TLS offsets emitted by the + * linker take the TCB into account (examples: arm, aarch64). + * The thread pointer references the TCB. + * + * 20: The architecture uses Variant II (examples: i386, sparc). + */ +#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10 + #ifndef ASM #ifdef __cplusplus @@ -151,7 +169,7 @@ void _CPU_Context_validate( uintptr_t pattern ); * * This function is used only in test sptests/spfatal26. */ -RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +static inline void _CPU_Instruction_illegal( void ) { __asm__ volatile ( ".word 0" ); } @@ -161,7 +179,7 @@ RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) * * This function is used only in test sptests/spcache01. */ -RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +static inline void _CPU_Instruction_no_operation( void ) { __asm__ volatile ( "nop" ); } @@ -176,11 +194,27 @@ RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) * @param context is the processor context defining the thread-local storage * area to use. */ -RTEMS_INLINE_ROUTINE void _CPU_Use_thread_local_storage( +static inline void _CPU_Use_thread_local_storage( + const Context_Control *context +) +{ + (void) context; +} + +/** + * @brief Gets the thread pointer of the context. + * + * The thread pointer is used to get the address of thread-local storage + * objects associated with a thread. + * + * @param context is the processor context containing the thread pointer. + */ +static inline void *_CPU_Get_TLS_thread_pointer( const Context_Control *context ) { (void) context; + return NULL; } #ifdef __cplusplus |