1 files changed, 90 insertions, 7 deletions
diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
index c8c86f4ec7..61f1ab7ba5 100644
--- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
 /**
  * @file
  *
@@ -5,11 +7,28 @@
  */
 
 /*
- * Copyright (c) 2013, 2016 embedded brains GmbH
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef _RTEMS_SCORE_CPUIMPL_H
@@ -35,6 +54,24 @@
  */
 #define CPU_PER_CPU_CONTROL_SIZE 0
 
+/**
+ * @brief Defines the thread-local storage (TLS) variant.
+ *
+ * Use one of the following values:
+ *
+ * 10: The architecture uses Variant I and the TLS offsets emitted by the
+ *     linker neglect the TCB (examples: nios2, m68k, microblaze, powerpc,
+ *     riscv).  The thread pointer directly references the thread-local data
+ *     area.
+ *
+ * 11: The architecture uses Variant I and the TLS offsets emitted by the
+ *     linker take the TCB into account (examples: arm, aarch64).
+ *     The thread pointer references the TCB.
+ *
+ * 20: The architecture uses Variant II (examples: i386, sparc).
+ */
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
 #ifndef ASM
 
 #ifdef __cplusplus
@@ -84,6 +121,19 @@ register struct Per_CPU_Control *_CPU_Per_CPU_current asm( "rX" );
 #define _CPU_Get_thread_executing() ( _CPU_Per_CPU_current->executing )
 
 /**
+ * This routine copies _error into a known place -- typically a stack
+ * location or a register, optionally disables interrupts, and
+ * halts/stops the CPU.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
+ */
+RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
+
+/* end of Fatal Error manager macros */
+
+/**
  * @addtogroup RTEMSScoreCPUExampleContext
  *
  * @brief Clobbers all volatile registers with values derived from the pattern
@@ -119,7 +169,7 @@ void _CPU_Context_validate( uintptr_t pattern );
  *
  * This function is used only in test sptests/spfatal26.
  */
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
 {
   __asm__ volatile ( ".word 0" );
 }
@@ -129,11 +179,44 @@ RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
  *
  * This function is used only in test sptests/spcache01.
  */
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
 {
   __asm__ volatile ( "nop" );
 }
 
+/**
+ * @brief Uses the thread-local storage area of the context.
+ *
+ * Some architectures may use dedicated registers to reference the thread-local
+ * storage area of the associated thread.  This function should set these
+ * registers to the values defined by the specified processor context.
+ *
+ * @param context is the processor context defining the thread-local storage
+ *   area to use.
+ */
+static inline void _CPU_Use_thread_local_storage(
+  const Context_Control *context
+)
+{
+  (void) context;
+}
+
+/**
+ * @brief Gets the thread pointer of the context.
+ *
+ * The thread pointer is used to get the address of thread-local storage
+ * objects associated with a thread.
+ *
+ * @param context is the processor context containing the thread pointer.
+ */
+static inline void *_CPU_Get_TLS_thread_pointer(
+  const Context_Control *context
+)
+{
+  (void) context;
+  return NULL;
+}
+
 #ifdef __cplusplus
 }
 #endif