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-rw-r--r--cpukit/score/cpu/lm32/ChangeLog5
-rw-r--r--cpukit/score/cpu/lm32/cpu.c9
2 files changed, 11 insertions, 3 deletions
diff --git a/cpukit/score/cpu/lm32/ChangeLog b/cpukit/score/cpu/lm32/ChangeLog
index ac385510e3..ae62c598f5 100644
--- a/cpukit/score/cpu/lm32/ChangeLog
+++ b/cpukit/score/cpu/lm32/ChangeLog
@@ -1,3 +1,8 @@
+2010-03-02 Michael Walle <michael@walle.cc>
+
+ * cpu.c: Provide body for CPU specific Idle thread. This halts on qemu
+ but is just a nop on a real cpu.
+
2009-05-05 Michael Walle <michael@walle.cc>
* cpu_asm.S, irq.c, rtems/score/cpu.h: Add lm32 gdb stub support.
diff --git a/cpukit/score/cpu/lm32/cpu.c b/cpukit/score/cpu/lm32/cpu.c
index b796b6a1e6..245019e4b7 100644
--- a/cpukit/score/cpu/lm32/cpu.c
+++ b/cpukit/score/cpu/lm32/cpu.c
@@ -161,7 +161,10 @@ void _CPU_Install_interrupt_stack( void )
void *_CPU_Thread_Idle_body( uintptr_t ignored )
{
-
- for( ; ; )
- /* insert your "halt" instruction here */ ;
+ for( ; ; ) {
+ /* The LM32 softcore itself hasn't any HLT instruction. But the
+ * LM32 qemu target interprets this nop instruction as HLT.
+ */
+ asm volatile("and r0, r0, r0");
+ }
}