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-rw-r--r--cpukit/score/cpu/bfin/cpu.c3
-rw-r--r--cpukit/score/cpu/bfin/rtems/score/cpu.h4
2 files changed, 5 insertions, 2 deletions
diff --git a/cpukit/score/cpu/bfin/cpu.c b/cpukit/score/cpu/bfin/cpu.c
index 05b9243513..268848e02b 100644
--- a/cpukit/score/cpu/bfin/cpu.c
+++ b/cpukit/score/cpu/bfin/cpu.c
@@ -186,7 +186,8 @@ void _CPU_Context_Initialize(
uint32_t size,
uint32_t new_level,
void *entry_point,
- bool is_fp
+ bool is_fp,
+ void *tls_area
)
{
uint32_t stack_high; /* highest "stack aligned" address */
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h
index 1af3f81f81..a8c60a5c44 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h
@@ -817,6 +817,7 @@ uint32_t _CPU_ISR_Get_level( void );
* point thread. This is typically only used on CPUs where the
* FPU may be easily disabled by software such as on the SPARC
* where the PSR contains an enable FPU bit.
+ * @param[in] tls_area is the thread-local storage (TLS) area
*
* Port Specific Information:
*
@@ -828,7 +829,8 @@ void _CPU_Context_Initialize(
uint32_t size,
uint32_t new_level,
void *entry_point,
- bool is_fp
+ bool is_fp,
+ void *tls_area
);
/**