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-rw-r--r--cpukit/score/cpu/bfin/include/rtems/score/cpu.h42
-rw-r--r--cpukit/score/cpu/bfin/include/rtems/score/cpuatomic.h14
-rw-r--r--cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h33
3 files changed, 29 insertions, 60 deletions
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
index d17dfbd30a..72e6d14433 100644
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h
@@ -308,15 +308,6 @@ typedef struct {
/**@{**/
/**
- * Support routine to initialize the RTEMS vector table after it is allocated.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_Initialize_vectors()
-
-/**
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in @a _isr_cookie.
*
@@ -364,7 +355,7 @@ typedef struct {
: : "d"(_level) : "R0" ); \
}
-RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+static inline bool _CPU_ISR_Is_enabled( uint32_t level )
{
return level != 0;
}
@@ -469,29 +460,6 @@ void _CPU_Context_Initialize(
/* end of Context handler macros */
-/* Fatal Error manager macros */
-
-/**
- * This routine copies _error into a known place -- typically a stack
- * location or a register, optionally disables interrupts, and
- * halts/stops the CPU.
- *
- * Port Specific Information:
- *
- * XXX document implementation including references if appropriate
- */
-#define _CPU_Fatal_halt( _source, _error ) \
- { \
- __asm__ volatile ( "cli R1; \
- R1 = %0; \
- _halt: \
- idle; \
- jump _halt;"\
- : : "r" (_error) ); \
- }
-
-/* end of Fatal Error manager macros */
-
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE
@@ -637,14 +605,6 @@ uint32_t _CPU_Counter_frequency( void );
CPU_Counter_ticks _CPU_Counter_read( void );
-static inline CPU_Counter_ticks _CPU_Counter_difference(
- CPU_Counter_ticks second,
- CPU_Counter_ticks first
-)
-{
- return second - first;
-}
-
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/bfin/include/rtems/score/cpuatomic.h
deleted file mode 100644
index 598ee76b20..0000000000
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
index 2140487fc3..5a445d9420 100644
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
@@ -5,7 +5,7 @@
*/
/*
- * Copyright (c) 2013 embedded brains GmbH
+ * Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -29,34 +29,57 @@
#define CPU_PER_CPU_CONTROL_SIZE 0
+#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
+
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
-RTEMS_INLINE_ROUTINE void _CPU_Context_volatile_clobber( uintptr_t pattern )
+RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
+
+static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
{
+ (void) pattern;
+
/* TODO */
}
-RTEMS_INLINE_ROUTINE void _CPU_Context_validate( uintptr_t pattern )
+static inline void _CPU_Context_validate( uintptr_t pattern )
{
+ (void) pattern;
+
while (1) {
/* TODO */
}
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void )
+static inline void _CPU_Instruction_illegal( void )
{
__asm__ volatile ( ".word 0" );
}
-RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void )
+static inline void _CPU_Instruction_no_operation( void )
{
__asm__ volatile ( "nop" );
}
+static inline void _CPU_Use_thread_local_storage(
+ const Context_Control *context
+)
+{
+ (void) context;
+}
+
+static inline void *_CPU_Get_TLS_thread_pointer(
+ const Context_Control *context
+)
+{
+ (void) context;
+ return NULL;
+}
+
#ifdef __cplusplus
}
#endif