diff options
Diffstat (limited to 'cpukit/score/cpu/aarch64/cpu.c')
-rw-r--r-- | cpukit/score/cpu/aarch64/cpu.c | 58 |
1 files changed, 27 insertions, 31 deletions
diff --git a/cpukit/score/cpu/aarch64/cpu.c b/cpukit/score/cpu/aarch64/cpu.c index 75b1125cf7..207508302b 100644 --- a/cpukit/score/cpu/aarch64/cpu.c +++ b/cpukit/score/cpu/aarch64/cpu.c @@ -38,8 +38,7 @@ #include "config.h" #endif -#include <rtems/score/assert.h> -#include <rtems/score/cpu.h> +#include <rtems/score/cpuimpl.h> #include <rtems/score/thread.h> #include <rtems/score/tls.h> @@ -143,21 +142,27 @@ void _CPU_Context_Initialize( the_context->thread_id = (uintptr_t) tls_area; if ( tls_area != NULL ) { - _TLS_TCB_at_area_begin_initialize( tls_area ); + the_context->thread_id = (uintptr_t) _TLS_Initialize_area( tls_area ); } } -void _CPU_ISR_Set_level( uint64_t level ) +void _CPU_ISR_Set_level( uint32_t level ) { /* Set the mask bit if interrupts are disabled */ - level = level ? AARCH64_PSTATE_I : 0; - __asm__ volatile ( - "msr DAIF, %[level]\n" - : : [level] "r" (level) - ); + if ( level ) { + __asm__ volatile ( + "msr DAIFSet, #0x2\n" + : : [level] "r" (level) + ); + } else { + __asm__ volatile ( + "msr DAIFClr, #0x2\n" + : : [level] "r" (level) + ); + } } -uint64_t _CPU_ISR_Get_level( void ) +uint32_t _CPU_ISR_Get_level( void ) { uint64_t level; @@ -169,29 +174,20 @@ uint64_t _CPU_ISR_Get_level( void ) return ( level & AARCH64_PSTATE_I ) != 0; } -void _CPU_ISR_install_vector( - uint32_t vector, - CPU_ISR_handler new_handler, - CPU_ISR_handler *old_handler -) +void _CPU_Initialize( void ) { - /* Redirection table starts at the end of the vector table */ - CPU_ISR_handler *table = (CPU_ISR_handler *) (MAX_EXCEPTIONS * 4); - - CPU_ISR_handler current_handler = table [vector]; - - /* The current handler is now the old one */ - if (old_handler != NULL) { - *old_handler = current_handler; - } - - /* Write only if necessary to avoid writes to a maybe read-only memory */ - if (current_handler != new_handler) { - table [vector] = new_handler; - } + /* Do nothing */ } -void _CPU_Initialize( void ) +void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ) { - /* Do nothing */ + ISR_Level level; + + _CPU_ISR_Disable( level ); + (void) level; + __asm__ volatile ("mov x0, %0\n" + : "=r" (error) + : "0" (error) + : "x0" ); + while (1); } |