diff options
Diffstat (limited to 'c/src/libchip/network')
| -rw-r--r-- | c/src/libchip/network/cs8900.h | 761 | ||||
| -rw-r--r-- | c/src/libchip/network/greth.h | 152 | ||||
| -rw-r--r-- | c/src/libchip/network/i82586var.h | 319 | ||||
| -rw-r--r-- | c/src/libchip/network/if_dcreg.h | 1120 | ||||
| -rw-r--r-- | c/src/libchip/network/if_fxpvar.h | 203 | ||||
| -rw-r--r-- | c/src/libchip/network/open_eth.h | 173 | ||||
| -rw-r--r-- | c/src/libchip/network/smc91111.h | 558 | ||||
| -rw-r--r-- | c/src/libchip/network/smc91111exp.h | 26 | ||||
| -rw-r--r-- | c/src/libchip/network/sonic.h | 458 | ||||
| -rw-r--r-- | c/src/libchip/network/wd80x3.h | 139 |
10 files changed, 0 insertions, 3909 deletions
diff --git a/c/src/libchip/network/cs8900.h b/c/src/libchip/network/cs8900.h deleted file mode 100644 index 79c943842d..0000000000 --- a/c/src/libchip/network/cs8900.h +++ /dev/null @@ -1,761 +0,0 @@ -/* - ------------------------------------------------------------------------ - - Copyright Cybertec Pty Ltd, 2000 - All rights reserved Cybertec Pty Ltd, 2000 - - Port to the DIMM PC copyright (c) 2004 Angelo Fraietta - This project has been assisted by the Commonwealth Government - through the Australia Council, its arts funding and advisory body. - - COPYRIGHT (c) 1989-1998. - On-Line Applications Research Corporation (OAR). - - The license and distribution terms for this file may be - found in the file LICENSE in this distribution or at - http://www.rtems.org/license/LICENSE. - - ------------------------------------------------------------------------ - - CS8900 RTEMS driver. - - This is a generic driver that requires a BSP backend. The BSP backend - provides the glue to the specific bus for the target hardware. It has - been tested with Coldfire processors, and the PC. These targets have - completely different bus, byte order and interrupt structures. - - An example BSP backend is provided in the pci386 BSP. - - The BSP provides the following functions: - - cs8900_io_set_reg - cs8900_io_get_reg - cs8900_mem_set_reg - cs8900_mem_get_reg - cs8900_put_data_block - cs8900_get_data_block - cs8900_tx_load - cs8900_attach_interrupt - cs8900_detach_interrupt - - The header file provides documentation for these functions. There - are four types of functions. - - The I/O set/get functions access the CS8900 I/O registers via the - I/O Mode. For example on a PC with an ISA bus you would use the - IA32 in/out port instructions. The cs8900_device structure passed - to these functions provide these functions with the I/O base - address. The BSP must provide these functions. - - The Memory set/get functions access the CS8900 internal registers - and frame buffers directly from a 4K byte block of host memory. - Memory mode provides a faster access to the CS8900. The cs8900_device - structure passed to these functions provides the memory base - address. The BSP needs to provide these functions but they do not - need to be implemented if the mem_base field is set to 0. The - driver will use I/O mode only. - - The Block transfer functions are used to read or write a block - of memory from the CS8900. This saves the driver making a number - of small calls. The BSP driver must know if I/O or Memory mode - can be used. - - The final group of functions is to handle interrupts. The BSP - must take care of save and restoring any interrupt state - information. - - The BSP declares a 'cs8900_device' structure for each device being - attached to the networking stack. It also creates a - 'struct rtems_bsdnet_ifconfig' which is used to attach the interface - to the networking stack. The following code declares the BSD config: - - static cs8900_device cs8900; - - static struct rtems_bsdnet_ifconfig cs8900_ifconfig = - { - "cs0", - cs8900_driver_attach, - NULL, - NULL, - NULL, - NULL, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 - }; - - The device linked to the BSD config structure with: - - cs8900_ifconfig.drv_ctrl = &cs8900; - - If you have a specific hardware address you should point the BSD - config structure to that address. If you do not the driver will read - the MAC address from the CS8900. This assumes the CS8900 has read - the address from an external EEPROM or has been setup by a BIOS or - boot monitor. For EEPROM less you need to supply the MAC address. - - Set the I/O and Memory base addresses. If the Memory base address - is 0 the driver will use I/O mode only. A typical initialisation - looks like: - - printf ("RTEMS BSD Network initialisation.\n"); - rtems_bsdnet_initialize_network (); - - #define ETHERNET_IO_BASE 0x300 - #define ETHERNET_MEM_BASE 0 - #define ETHERNET_IRQ_LEVEL 0 - - cs8900_device *cs = &cs8900; - - memset (cs, 0, sizeof (cs8900_device)); - - cs->dev = 0; - cs->io_base = ETHERNET_IO_BASE; - cs->mem_base = ETHERNET_MEM_BASE; - cs->irq_level = ETHERNET_IRQ_LEVEL; - cs->rx_queue_size = 30; - - cs8900_ifconfig.drv_ctrl = &cs8900; - - printf ("CS8900 initialisation\n"); - - rtems_bsdnet_attach (&cs8900_ifconfig); - - flags = IFF_UP; - if (rtems_bsdnet_ifconfig (cs8900_ifconfig.name, - SIOCSIFFLAGS, - &flags) < 0) - { - printf ("error: can't bring up %s: %s\n", - cs8900_ifconfig.name, strerror (errno)); - return; - } - - rtems_bsdnet_do_bootp_and_rootfs (); - - The IRQ level is the one documented in the CS8900 datasheet and below - in the CS8900 device structure. You need to map your target IRQ to the - CS8900 in the BSP driver. - - */ - -#if !defined(_CS8900_H_) -#define _CS8900_H_ - -#include <rtems.h> -#include <rtems/error.h> -#include <rtems/rtems_bsdnet.h> - -#include <sys/param.h> -#include <sys/mbuf.h> -#include <sys/socket.h> -#include <sys/sockio.h> - -#include <net/if.h> - -#include <netinet/in.h> -#include <netinet/if_ether.h> - -/* #include <target.h> what does this provide? joel to chris */ - -#define ET_MINLEN 60 - -/* - * CS8900 device register definitions - */ - -/* - * Crystal ESIA product id. - */ - -#define CS8900_ESIA_ID (0x630e) - -/* - * IO Registers. - */ - -#define CS8900_IO_RX_TX_DATA_PORT0 (0x0000) -#define CS8900_IO_TX_TX_DATA_PORT1 (0x0002) -#define CS8900_IO_TxCMD (0x0004) -#define CS8900_IO_TxLength (0x0006) -#define CS8900_IO_ISQ (0x0008) -#define CS8900_IO_PACKET_PAGE_PTR (0x000a) -#define CS8900_IO_PP_DATA_PORT0 (0x000c) -#define CS8900_IO_PP_DATA_PORT1 (0x000e) - -/* - * Packet Page Registers. - */ - -/* - * Bus Interface Registers. - */ - -#define CS8900_PP_PROD_ID (0x0000) -#define CS8900_PP_IO_BASE (0x0020) -#define CS8900_PP_INT (0x0022) -#define CS8900_PP_DMA_CHANNEL (0x0024) -#define CS8900_PP_DMA_SOF (0x0026) -#define CS8900_PP_DMA_FRM_CNT (0x0028) -#define CS8900_PP_DMA_RX_BCNT (0x002a) -#define CS8900_PP_MEM_BASE (0x002c) -#define CS8900_PP_BPROM_BASE (0x0030) -#define CS8900_PP_BPROM_AMASK (0x0034) -#define CS8900_PP_EEPROM_CMD (0x0040) -#define CS8900_PP_EEPROM_DATA (0x0042) -#define CS8900_PP_RX_FRAME_BCNT (0x0050) - -/* - * Configuration and Control Registers. - */ - -#define CS8900_PP_RxCFG (0x0102) -#define CS8900_PP_RxCTL (0x0104) -#define CS8900_PP_TxCFG (0x0106) -#define CS8900_PP_TxCMD_READ (0x0108) -#define CS8900_PP_BufCFG (0x010a) -#define CS8900_PP_LineCFG (0x0112) -#define CS8900_PP_SelfCTL (0x0114) -#define CS8900_PP_BusCTL (0x0116) -#define CS8900_PP_TestCTL (0x0118) - -/* - * Status and Event Registers. - */ - -#define CS8900_PP_ISQ (0x0120) -#define CS8900_PP_RxEvent (0x0124) -#define CS8900_PP_TxEvent (0x0128) -#define CS8900_PP_BufEvent (0x012c) -#define CS8900_PP_RxMISS (0x0130) -#define CS8900_PP_TxCol (0x0132) -#define CS8900_PP_LineST (0x0134) -#define CS8900_PP_SelfST (0x0136) -#define CS8900_PP_BusST (0x0138) -#define CS8900_PP_TDR (0x013c) - -/* - * Initiate Transmit Registers. - */ - -#define CS8900_PP_TxCMD (0x0144) -#define CS8900_PP_TxLength (0x0146) - -/* - * Address Filter Registers. - */ - -#define CS8900_PP_LAF (0x0150) -#define CS8900_PP_IA (0x0158) - -/* - * Frame Location. - */ - -#define CS8900_PP_RxStatus (0x0400) -#define CS8900_PP_RxLength (0x0402) -#define CS8900_PP_RxFrameLoc (0x0404) -#define CS8900_PP_TxFrameLoc (0x0a00) - -/* - * Bit Definitions of Registers. - */ - -/* - * IO Packet Page Pointer. - */ - -#define CS8900_PPP_AUTO_INCREMENT (0x8000) - -/* - * Reg 3. Receiver Configuration. - */ - -#define CS8900_RX_CONFIG_SKIP_1 (1 << 6) -#define CS8900_RX_CONFIG_STREAM_ENABLE (1 << 7) -#define CS8900_RX_CONFIG_RX_OK (1 << 8) -#define CS8900_RX_CONFIG_RX_DMA (1 << 9) -#define CS8900_RX_CONFIG_RX_AUTO_DMA (1 << 10) -#define CS8900_RX_CONFIG_BUFFER_CRC (1 << 11) -#define CS8900_RX_CONFIG_CRC_ERROR (1 << 12) -#define CS8900_RX_CONFIG_RUNT (1 << 13) -#define CS8900_RX_CONFIG_EXTRA_DATA (1 << 14) - -/* - * Reg 4. Receiver Event. - */ - -#define CS8900_RX_EVENT_HASH_IA_MATCH (1 << 6) -#define CS8900_RX_EVENT_DRIBBLE_BITS (1 << 7) -#define CS8900_RX_EVENT_RX_OK (1 << 8) -#define CS8900_RX_EVENT_HASHED (1 << 9) -#define CS8900_RX_EVENT_IA (1 << 10) -#define CS8900_RX_EVENT_BROADCAST (1 << 11) -#define CS8900_RX_EVENT_CRC_ERROR (1 << 12) -#define CS8900_RX_EVENT_RUNT (1 << 13) -#define CS8900_RX_EVENT_EXTRA_DATA (1 << 14) - -/* - * Reg 5. Receiver Control. - */ - -#define CS8900_RX_CTRL_HASH_IA_MATCH (1 << 6) -#define CS8900_RX_CTRL_PROMISCUOUS (1 << 7) -#define CS8900_RX_CTRL_RX_OK (1 << 8) -#define CS8900_RX_CTRL_MULTICAST (1 << 9) -#define CS8900_RX_CTRL_INDIVIDUAL (1 << 10) -#define CS8900_RX_CTRL_BROADCAST (1 << 11) -#define CS8900_RX_CTRL_CRC_ERROR (1 << 12) -#define CS8900_RX_CTRL_RUNT (1 << 13) -#define CS8900_RX_CTRL_EXTRA_DATA (1 << 14) - -/* - * Reg 7. Transmit Configuration. - */ - -#define CS8900_TX_CONFIG_LOSS_OF_CARRIER (1 << 6) -#define CS8900_TX_CONFIG_SQ_ERROR (1 << 7) -#define CS8900_TX_CONFIG_TX_OK (1 << 8) -#define CS8900_TX_CONFIG_OUT_OF_WINDOW (1 << 9) -#define CS8900_TX_CONFIG_JABBER (1 << 10) -#define CS8900_TX_CONFIG_ANY_COLLISION (1 << 11) -#define CS8900_TX_CONFIG_16_COLLISION (1 << 15) - -/* - * Reg 8. Transmit Event. - */ - -#define CS8900_TX_EVENT_LOSS_OF_CARRIER (1 << 6) -#define CS8900_TX_EVENT_SQ_ERROR (1 << 7) -#define CS8900_TX_EVENT_TX_OK (1 << 8) -#define CS8900_TX_EVENT_OUT_OF_WINDOW (1 << 9) -#define CS8900_TX_EVENT_JABBER (1 << 10) -#define CS8900_TX_EVENT_16_COLLISIONS (1 << 15) - -/* - * Reg 9. Transmit Command Status. - */ - -#define CS8900_TX_CMD_STATUS_TX_START_5 (0 << 6) -#define CS8900_TX_CMD_STATUS_TX_START_381 (1 << 6) -#define CS8900_TX_CMD_STATUS_TX_START_1021 (2 << 6) -#define CS8900_TX_CMD_STATUS_TX_START_ENTIRE (3 << 6) -#define CS8900_TX_CMD_STATUS_FORCE (1 << 8) -#define CS8900_TX_CMD_STATUS_ONE_COLLISION (1 << 9) -#define CS8900_TX_CMD_STATUS_INHIBIT_CRC (1 << 12) -#define CS8900_TX_CMD_STATUS_TX_PAD_DISABLED (1 << 13) - -/* - * Reg B. Buffer Configuration. - */ - -#define CS8900_BUFFER_CONFIG_SW_INT (1 << 6) -#define CS8900_BUFFER_CONFIG_RX_DMA_DONE (1 << 7) -#define CS8900_BUFFER_CONFIG_RDY_FOR_TX (1 << 8) -#define CS8900_BUFFER_CONFIG_TX_UNDERRUN (1 << 9) -#define CS8900_BUFFER_CONFIG_RX_MISSED (1 << 10) -#define CS8900_BUFFER_CONFIG_RX_128_BYTES (1 << 11) -#define CS8900_BUFFER_CONFIG_TX_COL_OVF (1 << 12) -#define CS8900_BUFFER_CONFIG_RX_MISSED_OVF (1 << 13) -#define CS8900_BUFFER_CONFIG_RX_DEST_MATCH (1 << 15) - -/* - * Reg C. Buffer Event. - */ - -#define CS8900_BUFFER_EVENT_SW_INT (1 << 6) -#define CS8900_BUFFER_EVENT_RX_DMA_DONE (1 << 7) -#define CS8900_BUFFER_EVENT_RDY_FOR_TX (1 << 8) -#define CS8900_BUFFER_EVENT_TX_UNDERRUN (1 << 9) -#define CS8900_BUFFER_EVENT_RX_MISSED (1 << 10) -#define CS8900_BUFFER_EVENT_RX_128_BYTES (1 << 11) -#define CS8900_BUFFER_EVENT_RX_DEST_MATCH (1 << 15) - -/* - * Reg 13. Line Control. - */ - -#define CS8900_LINE_CTRL_RX_ON (1 << 6) -#define CS8900_LINE_CTRL_TX_ON (1 << 7) -#define CS8900_LINE_CTRL_AUI (1 << 8) -#define CS8900_LINE_CTRL_10BASET (0 << 9) -#define CS8900_LINE_CTRL_AUTO_AUI_10BASET (1 << 9) -#define CS8900_LINE_CTRL_MOD_BACKOFF (1 << 11) -#define CS8900_LINE_CTRL_POLARITY_DISABLED (1 << 12) -#define CS8900_LINE_CTRL_2_PART_DEF_DISABLED (1 << 13) -#define CS8900_LINE_CTRL_LO_RX_SQUELCH (1 << 14) - -/* - * Reg 14. Line Status. - */ - -#define CS8900_LINE_STATUS_LINK_OK (1 << 7) -#define CS8900_LINE_STATUS_AUI (1 << 8) -#define CS8900_LINE_STATUS_10_BASE_T (1 << 9) -#define CS8900_LINE_STATUS_POLARITY_OK (1 << 12) -#define CS8900_LINE_STATUS_CRS (1 << 14) - -/* - * Reg 15. Self Control. - */ - -#define CS8900_SELF_CTRL_RESET (1 << 6) -#define CS8900_SELF_CTRL_SW_SUSPEND (1 << 8) -#define CS8900_SELF_CTRL_HW_SLEEP (1 << 9) -#define CS8900_SELF_CTRL_HW_STANDBY (1 << 10) -#define CS8900_SELF_CTRL_HC0E (1 << 12) -#define CS8900_SELF_CTRL_HC1E (1 << 13) -#define CS8900_SELF_CTRL_HCB0 (1 << 14) -#define CS8900_SELF_CTRL_HCB1 (1 << 15) - -/* - * Reg 16. Self Status. - */ - -#define CS8900_SELF_STATUS_3_3_V (1 << 6) -#define CS8900_SELF_STATUS_INITD (1 << 7) -#define CS8900_SELF_STATUS_SIBUST (1 << 8) -#define CS8900_SELF_STATUS_EEPROM_PRESENT (1 << 9) -#define CS8900_SELF_STATUS_EEPROM_OK (1 << 10) -#define CS8900_SELF_STATUS_EL_PRESENT (1 << 11) -#define CS8900_SELF_STATUS_EE_SIZE (1 << 12) - -/* - * Reg 17. Bus Control. - */ - -#define CS8900_BUS_CTRL_RESET_RX_DMA (1 << 6) -#define CS8900_BUS_CTRL_USE_SA (1 << 9) -#define CS8900_BUS_CTRL_MEMORY_ENABLE (1 << 10) -#define CS8900_BUS_CTRL_DMA_BURST (1 << 11) -#define CS8900_BUS_CTRL_IOCHRDYE (1 << 12) -#define CS8900_BUS_CTRL_RX_DMA_SIZE (1 << 13) -#define CS8900_BUS_CTRL_ENABLE_INT (1 << 15) - -/* - * Reg 18. Bus Status. - */ - -#define CS8900_BUS_STATUS_TX_BID_ERROR (1 << 7) -#define CS8900_BUS_STATUS_RDY_FOR_TX_NOW (1 << 8) - -/* - * Trace for debugging the isq processing. Define to 1 to enable. - */ -#define CS8900_TRACE 0 -#define CS8900_TRACE_SIZE (400) - -/* - * The default receive queue size. If the BSP sets this field to - * 0 this default is used. - */ -#define CS8900_RX_QUEUE_SIZE (30) - -/* - * Stats, more for debugging than anything else. - */ - -typedef struct -{ - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_interrupts; /* total number of rx interrupts */ - unsigned long tx_interrupts; /* total number of tx interrupts */ - - /* detailed rx errors: */ - unsigned long rx_dropped; /* no mbufs in queue */ - unsigned long rx_no_mbufs; /* no mbufs */ - unsigned long rx_no_clusters; /* no clusters */ - unsigned long rx_oversize_errors; - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_runt_errors; - unsigned long rx_missed_errors; /* receiver missed packet */ - - /* detailed tx errors */ - unsigned long tx_ok; - unsigned long tx_collisions; - unsigned long tx_bid_errors; - unsigned long tx_wait_for_rdy4tx; - unsigned long tx_rdy4tx; - unsigned long tx_underrun_errors; - unsigned long tx_dropped; - unsigned long tx_resends; - - /* interrupt watch dog */ - unsigned long int_swint_req; - unsigned long int_swint_res; - unsigned long int_lockup; - - unsigned long interrupts; - -} eth_statistics; - -/* - * CS8900 device structure - */ - -typedef struct -{ - /* - * Device number. - */ - - int dev; - - /* - * Memory base addresses. Making mem_base 0 forces the - * driver to perform only I/O space accesses. - */ - - unsigned long io_base; - unsigned long mem_base; - - /* - * The IRQ level as defined in the datasheet for the CS8900. - * - * ISA BUS Pin Value - * IRQ10 INTRQ0 0 - * IRQ11 INTRQ1 1 - * IRQ12 INTRQ2 2 - * IRQ5 INTRQ3 3 - */ - - int irq_level; - - /* - * The MAC address. - */ - - unsigned char mac_address[6]; - - /* - * The bsdnet information structure. - */ - - struct arpcom arpcom; - - /* - * Driver state and resources. - */ - - int accept_bcast; - int tx_active; - - rtems_id rx_task; - rtems_id tx_task; - - /* - * The queues. FIXME : these should be changed to be mbuf lists. - */ - - struct mbuf *rx_ready_head; - struct mbuf *rx_ready_tail; - int rx_ready_len; - - struct mbuf *rx_loaded_head; - struct mbuf *rx_loaded_tail; - int rx_loaded_len; - - /* - * Number of mbufs queued for the interrupt handler to - * loop reading. - */ - - int rx_queue_size; - -#if CS8900_TRACE - unsigned short trace_key[CS8900_TRACE_SIZE]; - unsigned long trace_var[CS8900_TRACE_SIZE]; - unsigned long trace_time[CS8900_TRACE_SIZE]; - int trace_in; -#endif - - /** - * Standard(!) ethernet statistics - */ - - eth_statistics eth_stats; - -} cs8900_device; - -/* - * Link active returns the state of the PHY. - * - * @param cs Pointer to the device structure. - */ - -int cs8900_link_active (cs8900_device *cs); - -/** - * The RTEMS network stack driver attach function that is loaded into the - * the rtems_bsdnet_ifconfig struct. The network stack will call this - * function when attaching the driver. The BSP must load the 'drv_ctrl' - * field of the structure before calling the 'rtems_bsdnet_attach' - * function. - * - * @param config The RTEMS BSD config structure. - * - * @param attaching True is the stack is attaching the interface. - * - * @retval int Set to 1 if the device has attached. - */ - -int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, - int attaching); - -/** - * The BSP specific interrupt wrapper calls this function when a device - * interrupt occurs. - * - * @param v The RTEMS vector number that generated the interrupt. - * - * @param cs Pointer to the device structure passed to the interrupt - * catch function provided by the BSP. - * - * @retval rtems_isr The standard ISR return type. - */ - -rtems_isr cs8900_interrupt (rtems_vector_number v, void *cs); - -/** - * Get the MAC address for the interface. - * - * @param cs Pointer to the device structure. - * - * @param mac_address Pointer to the memory to load the MAC address. This - * is a 6 byte buffer so do not exceeed the bounds. - */ - -void cs8900_get_mac_addr (cs8900_device *cs, unsigned char *mac_address); - -/** - * Catch the device interrupt. When the interrupt is called call the - * function 'cs8900_interrupt'. - * - * BSP to provide this function. - * - * @param cs Pointer to the device structure. - */ - -void cs8900_attach_interrupt (cs8900_device *cs); - -/** - * Detach the device interrupt. - * - * BSP to provide this function. - * - * @param cs Pointer to the device structure. - */ - -void cs8900_detach_interrupt (cs8900_device *cs); - -/** - * Write to an IO space register. - * - * BSP to provide this function. - * - * @param cs Pointer to the device structure. - * - * @param reg Register offset from the IO base. - * - * @param data The data to be written to the register. - */ - -void cs8900_io_set_reg (cs8900_device *cs, - unsigned short reg, unsigned short data); - -/** - * Read an IO space register. - * - * BSP to provide this function. - * - * @param cs Pointer to the device structure. - * - * @param reg Register offset from the IO base. - * - * @retval unsigned short The register data. - */ - -unsigned short cs8900_io_get_reg (cs8900_device *cs, unsigned short reg); - -/** - * Write to a memory space register. Will only be called is the mem_base - * field of the 'cs' struct is not 0. - * - * BSP to provide this function. - * - * @param cs Pointer to the device structure. - * - * @param reg Register offset from the memory base. - * - * @param data The data to be written to the register. - */ - -void cs8900_mem_set_reg (cs8900_device *cs, - unsigned long reg, unsigned short data); - -/** - * Read a memory space register. Will only be called is the mem_base - * field of the 'cs' struct is not 0. - * - * BSP to provide this function. - * - * @param cs Pointer to the device structure. - * - * @param reg Register offset from the IO base. - * - * @retval unsigned short The register data. - */ - -unsigned short cs8900_mem_get_reg (cs8900_device *cs, unsigned long reg); - -/** - * Write a block of data to the interface. The BSP codes if this is an IO or - * memory space write. - * - * BSP to provide this function. - * - * @param cs Pointer to the device structure. - * - * @param len The length of data to write. - * - * @param data Pointer to the data to be written. - */ - -void cs8900_put_data_block (cs8900_device *cs, int len, unsigned char *data); - -/** - * Read a block of data from the interface. The BSP codes if this is an IO or - * memory space write. The read must not be longer than the MTU size. - * - * BSP to provide this function. - * - * @param cs Pointer to the device structure. - * - * @param data Pointer to the buffer where the data is to be written. - * - * @retval unsigned short The number of bytes read from the device. - */ - -unsigned short cs8900_get_data_block (cs8900_device *cs, unsigned char *data); - -/** - * Load a mbuf chain to the device ready for tranmission. - * - * BSP to provide this function. - * - * @param cs Pointer to the device structure. - * - * @param m Pointer to the head of an mbuf chain. - */ - -void cs8900_tx_load (cs8900_device *cs, struct mbuf *m); - -#endif diff --git a/c/src/libchip/network/greth.h b/c/src/libchip/network/greth.h deleted file mode 100644 index c6e000dbd3..0000000000 --- a/c/src/libchip/network/greth.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Gaisler Research ethernet MAC driver - * adapted from Opencores driver by Marko Isomaki - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#ifndef _GR_ETH_ -#define _GR_ETH_ - - -/* Configuration Information */ - -typedef struct { - void *base_address; - rtems_vector_number vector; - uint32_t txd_count; - uint32_t rxd_count; -} greth_configuration_t; - -/* Ethernet configuration registers */ - -typedef struct _greth_regs { - volatile uint32_t ctrl; /* Ctrl Register */ - volatile uint32_t status; /* Status Register */ - volatile uint32_t mac_addr_msb; /* Bit 47-32 of MAC address */ - volatile uint32_t mac_addr_lsb; /* Bit 31-0 of MAC address */ - volatile uint32_t mdio_ctrl; /* MDIO control and status */ - volatile uint32_t txdesc; /* Transmit descriptor pointer */ - volatile uint32_t rxdesc; /* Receive descriptor pointer */ -} greth_regs; - -#define GRETH_TOTAL_BD 128 -#define GRETH_MAXBUF_LEN 1520 - -/* Tx BD */ -#define GRETH_TXD_ENABLE 0x0800 /* Tx BD Enable */ -#define GRETH_TXD_WRAP 0x1000 /* Tx BD Wrap (last BD) */ -#define GRETH_TXD_IRQ 0x2000 /* Tx BD IRQ Enable */ -#define GRETH_TXD_MORE 0x20000 /* Tx BD More (more descs for packet) */ -#define GRETH_TXD_IPCS 0x40000 /* Tx BD insert ip chksum */ -#define GRETH_TXD_TCPCS 0x80000 /* Tx BD insert tcp chksum */ -#define GRETH_TXD_UDPCS 0x100000 /* Tx BD insert udp chksum */ - -#define GRETH_TXD_UNDERRUN 0x4000 /* Tx BD Underrun Status */ -#define GRETH_TXD_RETLIM 0x8000 /* Tx BD Retransmission Limit Status */ -#define GRETH_TXD_LATECOL 0x10000 /* Tx BD Late Collision */ - -#define GRETH_TXD_STATS (GRETH_TXD_UNDERRUN | \ - GRETH_TXD_RETLIM | \ - GRETH_TXD_LATECOL) - -#define GRETH_TXD_CS (GRETH_TXD_IPCS | \ - GRETH_TXD_TCPCS | \ - GRETH_TXD_UDPCS) - -/* Rx BD */ -#define GRETH_RXD_ENABLE 0x0800 /* Rx BD Enable */ -#define GRETH_RXD_WRAP 0x1000 /* Rx BD Wrap (last BD) */ -#define GRETH_RXD_IRQ 0x2000 /* Rx BD IRQ Enable */ - -#define GRETH_RXD_DRIBBLE 0x4000 /* Rx BD Dribble Nibble Status */ -#define GRETH_RXD_TOOLONG 0x8000 /* Rx BD Too Long Status */ -#define GRETH_RXD_CRCERR 0x10000 /* Rx BD CRC Error Status */ -#define GRETH_RXD_OVERRUN 0x20000 /* Rx BD Overrun Status */ -#define GRETH_RXD_LENERR 0x40000 /* Rx BD Length Error */ -#define GRETH_RXD_ID 0x40000 /* Rx BD IP Detected */ -#define GRETH_RXD_IR 0x40000 /* Rx BD IP Chksum Error */ -#define GRETH_RXD_UD 0x40000 /* Rx BD UDP Detected*/ -#define GRETH_RXD_UR 0x40000 /* Rx BD UDP Chksum Error */ -#define GRETH_RXD_TD 0x40000 /* Rx BD TCP Detected */ -#define GRETH_RXD_TR 0x40000 /* Rx BD TCP Chksum Error */ - - -#define GRETH_RXD_STATS (GRETH_RXD_OVERRUN | \ - GRETH_RXD_DRIBBLE | \ - GRETH_RXD_TOOLONG | \ - GRETH_RXD_CRCERR) - -/* CTRL Register */ -#define GRETH_CTRL_TXEN 0x00000001 /* Transmit Enable */ -#define GRETH_CTRL_RXEN 0x00000002 /* Receive Enable */ -#define GRETH_CTRL_TXIRQ 0x00000004 /* Transmit Enable */ -#define GRETH_CTRL_RXIRQ 0x00000008 /* Receive Enable */ -#define GRETH_CTRL_FULLD 0x00000010 /* Full Duplex */ -#define GRETH_CTRL_PRO 0x00000020 /* Promiscuous (receive all) */ -#define GRETH_CTRL_RST 0x00000040 /* Reset MAC */ - -/* Status Register */ -#define GRETH_STATUS_RXERR 0x00000001 /* Receive Error */ -#define GRETH_STATUS_TXERR 0x00000002 /* Transmit Error IRQ */ -#define GRETH_STATUS_RXIRQ 0x00000004 /* Receive Frame IRQ */ -#define GRETH_STATUS_TXIRQ 0x00000008 /* Transmit Error IRQ */ -#define GRETH_STATUS_RXAHBERR 0x00000010 /* Receiver AHB Error */ -#define GRETH_STATUS_TXAHBERR 0x00000020 /* Transmitter AHB Error */ - -/* MDIO Control */ -#define GRETH_MDIO_WRITE 0x00000001 /* MDIO Write */ -#define GRETH_MDIO_READ 0x00000002 /* MDIO Read */ -#define GRETH_MDIO_LINKFAIL 0x00000004 /* MDIO Link failed */ -#define GRETH_MDIO_BUSY 0x00000008 /* MDIO Link Busy */ -#define GRETH_MDIO_REGADR 0x000007C0 /* Register Address */ -#define GRETH_MDIO_PHYADR 0x0000F800 /* PHY address */ -#define GRETH_MDIO_DATA 0xFFFF0000 /* MDIO DATA */ - - -/* MII registers */ -#define GRETH_MII_EXTADV_1000FD 0x00000200 -#define GRETH_MII_EXTADV_1000HD 0x00000100 -#define GRETH_MII_EXTPRT_1000FD 0x00000800 -#define GRETH_MII_EXTPRT_1000HD 0x00000400 - -#define GRETH_MII_100T4 0x00000200 -#define GRETH_MII_100TXFD 0x00000100 -#define GRETH_MII_100TXHD 0x00000080 -#define GRETH_MII_10FD 0x00000040 -#define GRETH_MII_10HD 0x00000020 - - - -/* Attach routine */ - -int rtems_greth_driver_attach ( - struct rtems_bsdnet_ifconfig *config, - greth_configuration_t *chip -); - -/* PHY data */ -struct phy_device_info -{ - int vendor; - int device; - int rev; - - int adv; - int part; - - int extadv; - int extpart; -}; - -/* -#ifdef CPU_U32_FIX -void ipalign(struct mbuf *m); -#endif - -*/ -#endif - diff --git a/c/src/libchip/network/i82586var.h b/c/src/libchip/network/i82586var.h deleted file mode 100644 index c9421a6732..0000000000 --- a/c/src/libchip/network/i82586var.h +++ /dev/null @@ -1,319 +0,0 @@ -/* $NetBSD: i82586var.h,v 1.15 2001/01/22 22:28:45 bjh21 Exp $ */ - -/*- - * Copyright (c) 1998 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Paul Kranenburg and Charles M. Hannum. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the NetBSD - * Foundation, Inc. and its contributors. - * 4. Neither the name of The NetBSD Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * Copyright (c) 1992, 1993, University of Vermont and State - * Agricultural College. - * Copyright (c) 1992, 1993, Garrett A. Wollman. - * - * Portions: - * Copyright (c) 1994, 1995, Rafal K. Boni - * Copyright (c) 1990, 1991, William F. Jolitz - * Copyright (c) 1990, The Regents of the University of California - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of Vermont - * and State Agricultural College and Garrett A. Wollman, by William F. - * Jolitz, and by the University of California, Berkeley, Lawrence - * Berkeley Laboratory, and its contributors. - * 4. Neither the names of the Universities nor the names of the authors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR AUTHORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Intel 82586 Ethernet chip - * Register, bit, and structure definitions. - * - * Original StarLAN driver written by Garrett Wollman with reference to the - * Clarkson Packet Driver code for this chip written by Russ Nelson and others. - * - * BPF support code taken from hpdev/if_le.c, supplied with tcpdump. - * - * 3C507 support is loosely based on code donated to NetBSD by Rafal Boni. - * - * Majorly cleaned up and 3C507 code merged by Charles Hannum. - * - * Converted to SUN ie driver by Charles D. Cranor, - * October 1994, January 1995. - * This sun version based on i386 version 1.30. - */ - -#ifndef I82586_DEBUG -#define I82586_DEBUG 0 -#endif - -/* Debug elements */ -#define IED_RINT 0x01 -#define IED_TINT 0x02 -#define IED_RNR 0x04 -#define IED_CNA 0x08 -#define IED_READFRAME 0x10 -#define IED_ENQ 0x20 -#define IED_XMIT 0x40 -#define IED_ALL 0x7f - -#define B_PER_F 3 /* recv buffers per frame */ -#define IE_RBUF_SIZE 256 /* size of each receive buffer; - MUST BE POWER OF TWO */ -#define NTXBUF 2 /* number of transmit commands */ -#define IE_TBUF_SIZE ETHER_MAX_LEN /* length of transmit buffer */ - -#define IE_MAXMCAST (IE_TBUF_SIZE/6)/* must fit in transmit buffer */ - - -#define INTR_ENTER 0 /* intr hook called on ISR entry */ -#define INTR_EXIT 1 /* intr hook called on ISR exit */ -#define INTR_LOOP 2 /* intr hook called on ISR loop */ -#define INTR_ACK 3 /* intr hook called on ie_ack */ - -#define CHIP_PROBE 0 /* reset called from chip probe */ -#define CARD_RESET 1 /* reset called from card reset */ - -#if I82586_DEBUG -#define I82586_INTS_REQ 0 -#define I82586_INTS_IN 1 -#define I82586_INTS_LOOPS 2 -#define I82586_INTS_OUT 3 -#define I82586_RX_INT 4 -#define I82586_RX_DROP 5 -#define I82586_RX_ERR 6 -#define I82586_RX_OK 7 -#define I82586_RX_START 8 -#define I82586_START_TX 9 -#define I82586_TX_START 10 -#define I82586_TX_INT 11 -#define I82586_TX_REQ 12 -#define I82586_TX_EVT 13 -#define I82586_TX_EMIT 14 -#define I82586_TX_BAD 15 -#define I82586_TX_ACTIVE 16 -#define I82586_TRACE_CNT 17 - -#define I82586_TRACE_FLOW (10000) -#endif - -/* - * Ethernet status, per interface. - * - * The chip uses two types of pointers: 16 bit and 24 bit - * 24 bit pointers cover the board's memory. - * 16 bit pointers are offsets from the ISCP's `ie_base' - * - * The board's memory is represented by the bus handle `bh'. The MI - * i82586 driver deals exclusively with offsets relative to the - * board memory bus handle. The `ie_softc' fields below that are marked - * `MD' are in the domain of the front-end driver; they opaque to the - * MI driver part. - * - * The front-end is required to manage the SCP and ISCP structures. i.e. - * allocate room for them on the board's memory, and arrange to point the - * chip at the SCB stucture, the offset of which is passed to the MI - * driver in `sc_scb'. - * - * The following functions provide the glue necessary to deal with - * host and bus idiosyncracies: - * - * hwreset - board reset - * hwinit - board initialization - * chan_attn - get chip to look at prepared commands - * intrhook - board dependent interrupt processing - * - * All of the following shared-memory access function use an offset - * relative to the bus handle to indicate the shared memory location. - * The bus_{read/write}N function take or return offset into the - * shared memory in the host's byte-order. - * - * memcopyin - copy device memory: board to KVA - * memcopyout - copy device memory: KVA to board - * bus_read16 - read a 16-bit i82586 pointer - `offset' argument will be 16-bit aligned - * bus_write16 - write a 16-bit i82586 pointer - `offset' argument will be 16-bit aligned - * bus_write24 - write a 24-bit i82586 pointer - `offset' argument will be 32-bit aligned - * bus_barrier - perform a bus barrier operation, forcing - all outstanding reads/writes to complete - * - */ - -struct ie_softc { - struct arpcom arpcom; - - /* - * For RTEMS we run the tx and rx handlers under a task due to the - * network semaphore stuff. - */ - - rtems_id intr_task; - rtems_id tx_task; - - void *sc_iobase; /* (MD) KVA of base of 24 bit addr space */ - void *sc_maddr; /* (MD) KVA of base of chip's RAM - (16bit addr space) */ - u_int sc_msize; /* (MD) how much RAM we have/use */ - - /* Bus glue */ - void (*hwreset) (struct ie_softc *, int); - void (*hwinit) (struct ie_softc *); - void (*chan_attn) (struct ie_softc *, int); - int (*intrhook) (struct ie_softc *, int where); - - void (*memcopyin) (struct ie_softc *, void *, int, size_t); - void (*memcopyout) (struct ie_softc *, const void *, - int, size_t); - u_int16_t (*ie_bus_read16) (struct ie_softc *, int offset); - void (*ie_bus_write16) (struct ie_softc *, int offset, - u_int16_t value); - void (*ie_bus_write24) (struct ie_softc *, int offset, - int addr); - void (*ie_bus_barrier) (struct ie_softc *, int offset, - int length, int flags); - - /* Media management */ - int (*sc_mediachange) (struct ie_softc *); - /* card dependent media change */ - void (*sc_mediastatus) (struct ie_softc *, struct ifmediareq *); - /* card dependent media status */ - - /* - * Offsets (relative to bus handle) of the i82586 SYSTEM structures. - */ - int scp; /* Offset to the SCP (set by front-end) */ - int iscp; /* Offset to the ISCP (set by front-end) */ - int scb; /* Offset to SCB (set by front-end) */ - - /* - * Offset and size of a block of board memory where the buffers - * are to be allocated from (initialized by front-end). - */ - int buf_area; /* Start of descriptors and buffers */ - int buf_area_sz; /* Size of above */ - - /* - * The buffers & descriptors (recv and xmit) - */ - int rframes; /* Offset to `nrxbuf' frame descriptors */ - int rbds; /* Offset to `nrxbuf' buffer descriptors */ - int rbufs; /* Offset to `nrxbuf' receive buffers */ -#define IE_RBUF_ADDR(sc, i) (sc->rbufs + ((i) * IE_RBUF_SIZE)) - int rfhead, rftail; - int rbhead, rbtail; - int nframes; /* number of frames in use */ - int nrxbuf; /* number of recv buffs in use */ - int rnr_expect; /* XXX - expect a RCVR not ready interrupt */ - - int nop_cmds; /* Offset to NTXBUF no-op commands */ - int xmit_cmds; /* Offset to NTXBUF transmit commands */ - int xbds; /* Offset to NTXBUF buffer descriptors */ - int xbufs; /* Offset to NTXBUF transmit buffers */ -#define IE_XBUF_ADDR(sc, i) (sc->xbufs + ((i) * IE_TBUF_SIZE)) - - int xchead, xctail; - int xmit_busy; - int do_xmitnopchain; /* Controls use of xmit NOP chains */ - int xmit_req; - - /* Multicast addresses */ - char *mcast_addrs; /* Current MC filter addresses */ - int mcast_addrs_size; /* Current size of MC buffer */ - int mcast_count; /* Current # of addrs in buffer */ - int want_mcsetup; /* run mcsetup at next opportunity */ - - int promisc; /* are we in promisc mode? */ - int async_cmd_inprogress; /* we didn't wait for 586 to accept - a command */ - -#if I82586_DEBUG -#define I82586_TRACE(s, e, d) \ -do { rtems_interrupt_level level; rtems_interrupt_disable (level); \ - (s)->trace_flow[(s)->trace_flow_in++] = (e); \ - (s)->trace_flow[(s)->trace_flow_in++] = (unsigned int)(d); \ - if ((s)->trace_flow_in >= I82586_TRACE_FLOW) { \ - (s)->trace_flow_in = 0; \ - (s)->trace_flow_wrap = 1; \ - } \ - rtems_interrupt_enable (level); \ - } while (0) - - int sc_debug; - unsigned int trace_flow[I82586_TRACE_FLOW * 2]; - unsigned int trace_flow_wrap; -#endif - unsigned int trace_flow_in; -}; - -/* Exported functions */ -rtems_isr i82586_intr (rtems_vector_number , void *); -int i82586_proberam (struct ie_softc *); -int i82586_attach (struct rtems_bsdnet_ifconfig *config, int attaching); - -/* Shortcut macros to optional (driver uses default if unspecified) callbacks */ -#define xIE_BUS_BARRIER(sc, offset, length, flags) \ -do { \ - if ((sc)->ie_bus_barrier) \ - ((sc)->ie_bus_barrier)((sc), (offset), (length), (flags));\ - else \ - bus_space_barrier((sc)->bt, (sc)->bh, (offset), (length), \ - (flags)); \ -} while (0) - -#define IE_BUS_BARRIER(sc, offset, length, flags) diff --git a/c/src/libchip/network/if_dcreg.h b/c/src/libchip/network/if_dcreg.h deleted file mode 100644 index 07395c1884..0000000000 --- a/c/src/libchip/network/if_dcreg.h +++ /dev/null @@ -1,1120 +0,0 @@ -/* - * Copyright (c) 1997, 1998, 1999 - * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Bill Paul. - * 4. Neither the name of the author nor the names of any co-contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: src/sys/pci/if_dcreg.h,v 1.4.2.21 2003/02/12 22:19:34 mbr Exp $ - */ - -/* - * 21143 and clone common register definitions. - */ - -#define DC_BUSCTL 0x00 /* bus control */ -#define DC_TXSTART 0x08 /* tx start demand */ -#define DC_RXSTART 0x10 /* rx start demand */ -#define DC_RXADDR 0x18 /* rx descriptor list start addr */ -#define DC_TXADDR 0x20 /* tx descriptor list start addr */ -#define DC_ISR 0x28 /* interrupt status register */ -#define DC_NETCFG 0x30 /* network config register */ -#define DC_IMR 0x38 /* interrupt mask */ -#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ -#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ -#define DC_ROM 0x50 /* ROM programming address */ -#define DC_TIMER 0x58 /* general timer */ -#define DC_10BTSTAT 0x60 /* SIA status */ -#define DC_SIARESET 0x68 /* SIA connectivity */ -#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ -#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ - -/* - * There are two general 'types' of MX chips that we need to be - * concerned with. One is the original 98713, which has its internal - * NWAY support controlled via the MDIO bits in the serial I/O - * register. The other is everything else (from the 98713A on up), - * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, - * just like the 21143. This type setting also governs which of the - * 'magic' numbers we write to CSR16. The PNIC II falls into the - * 98713A/98715/98715A/98725 category. - */ -#define DC_TYPE_98713 0x1 -#define DC_TYPE_98713A 0x2 -#define DC_TYPE_987x5 0x3 - -/* Other type of supported chips. */ -#define DC_TYPE_21143 0x4 /* Intel 21143 */ -#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ -#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ -#define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */ -#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ -#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ -#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ -#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ - -#define DC_IS_MACRONIX(x) \ - (x->dc_type == DC_TYPE_98713 || \ - x->dc_type == DC_TYPE_98713A || \ - x->dc_type == DC_TYPE_987x5) - -#define DC_IS_ADMTEK(x) \ - (x->dc_type == DC_TYPE_AL981 || \ - x->dc_type == DC_TYPE_AN985) - -#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) -#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) -#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) -#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985) -#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) -#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) -#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) -#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) - -/* MII/symbol mode port types */ -#define DC_PMODE_MII 0x1 -#define DC_PMODE_SYM 0x2 -#define DC_PMODE_SIA 0x3 - -/* - * Bus control bits. - */ -#define DC_BUSCTL_RESET 0x00000001 -#define DC_BUSCTL_ARBITRATION 0x00000002 -#define DC_BUSCTL_SKIPLEN 0x0000007C -#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 -#define DC_BUSCTL_BURSTLEN 0x00003F00 -#define DC_BUSCTL_CACHEALIGN 0x0000C000 -#define DC_BUSCTL_TXPOLL 0x000E0000 -#define DC_BUSCTL_DBO 0x00100000 -#define DC_BUSCTL_MRME 0x00200000 -#define DC_BUSCTL_MRLE 0x00800000 -#define DC_BUSCTL_MWIE 0x01000000 -#define DC_BUSCTL_ONNOW_ENB 0x04000000 - -#define DC_SKIPLEN_1LONG 0x00000004 -#define DC_SKIPLEN_2LONG 0x00000008 -#define DC_SKIPLEN_3LONG 0x00000010 -#define DC_SKIPLEN_4LONG 0x00000020 -#define DC_SKIPLEN_5LONG 0x00000040 - -#define DC_CACHEALIGN_NONE 0x00000000 -#define DC_CACHEALIGN_8LONG 0x00004000 -#define DC_CACHEALIGN_16LONG 0x00008000 -#define DC_CACHEALIGN_32LONG 0x0000C000 - -#define DC_BURSTLEN_USECA 0x00000000 -#define DC_BURSTLEN_1LONG 0x00000100 -#define DC_BURSTLEN_2LONG 0x00000200 -#define DC_BURSTLEN_4LONG 0x00000400 -#define DC_BURSTLEN_8LONG 0x00000800 -#define DC_BURSTLEN_16LONG 0x00001000 -#define DC_BURSTLEN_32LONG 0x00002000 - -#define DC_TXPOLL_OFF 0x00000000 -#define DC_TXPOLL_1 0x00020000 -#define DC_TXPOLL_2 0x00040000 -#define DC_TXPOLL_3 0x00060000 -#define DC_TXPOLL_4 0x00080000 -#define DC_TXPOLL_5 0x000A0000 -#define DC_TXPOLL_6 0x000C0000 -#define DC_TXPOLL_7 0x000E0000 - -/* - * Interrupt status bits. - */ -#define DC_ISR_TX_OK 0x00000001 -#define DC_ISR_TX_IDLE 0x00000002 -#define DC_ISR_TX_NOBUF 0x00000004 -#define DC_ISR_TX_JABBERTIMEO 0x00000008 -#define DC_ISR_LINKGOOD 0x00000010 -#define DC_ISR_TX_UNDERRUN 0x00000020 -#define DC_ISR_RX_OK 0x00000040 -#define DC_ISR_RX_NOBUF 0x00000080 -#define DC_ISR_RX_READ 0x00000100 -#define DC_ISR_RX_WATDOGTIMEO 0x00000200 -#define DC_ISR_TX_EARLY 0x00000400 -#define DC_ISR_TIMER_EXPIRED 0x00000800 -#define DC_ISR_LINKFAIL 0x00001000 -#define DC_ISR_BUS_ERR 0x00002000 -#define DC_ISR_RX_EARLY 0x00004000 -#define DC_ISR_ABNORMAL 0x00008000 -#define DC_ISR_NORMAL 0x00010000 -#define DC_ISR_RX_STATE 0x000E0000 -#define DC_ISR_TX_STATE 0x00700000 -#define DC_ISR_BUSERRTYPE 0x03800000 -#define DC_ISR_100MBPSLINK 0x08000000 -#define DC_ISR_MAGICKPACK 0x10000000 - -#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ -#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ -#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ -#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ -#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ -#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ -#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ -#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ - -#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ -#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ -#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ -#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ -#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ -#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ -#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ -#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ - -/* - * Network config bits. - */ -#define DC_NETCFG_RX_HASHPERF 0x00000001 -#define DC_NETCFG_RX_ON 0x00000002 -#define DC_NETCFG_RX_HASHONLY 0x00000004 -#define DC_NETCFG_RX_BADFRAMES 0x00000008 -#define DC_NETCFG_RX_INVFILT 0x00000010 -#define DC_NETCFG_BACKOFFCNT 0x00000020 -#define DC_NETCFG_RX_PROMISC 0x00000040 -#define DC_NETCFG_RX_ALLMULTI 0x00000080 -#define DC_NETCFG_FULLDUPLEX 0x00000200 -#define DC_NETCFG_LOOPBACK 0x00000C00 -#define DC_NETCFG_FORCECOLL 0x00001000 -#define DC_NETCFG_TX_ON 0x00002000 -#define DC_NETCFG_TX_THRESH 0x0000C000 -#define DC_NETCFG_TX_BACKOFF 0x00020000 -#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ -#define DC_NETCFG_HEARTBEAT 0x00080000 -#define DC_NETCFG_STORENFWD 0x00200000 -#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ -#define DC_NETCFG_PCS 0x00800000 -#define DC_NETCFG_SCRAMBLER 0x01000000 -#define DC_NETCFG_NO_RXCRC 0x02000000 -#define DC_NETCFG_RX_ALL 0x40000000 -#define DC_NETCFG_CAPEFFECT 0x80000000 - -#define DC_OPMODE_NORM 0x00000000 -#define DC_OPMODE_INTLOOP 0x00000400 -#define DC_OPMODE_EXTLOOP 0x00000800 - -#if 0 -#define DC_TXTHRESH_72BYTES 0x00000000 -#define DC_TXTHRESH_96BYTES 0x00004000 -#define DC_TXTHRESH_128BYTES 0x00008000 -#define DC_TXTHRESH_160BYTES 0x0000C000 -#endif - -#define DC_TXTHRESH_MIN 0x00000000 -#define DC_TXTHRESH_INC 0x00004000 -#define DC_TXTHRESH_MAX 0x0000C000 - - -/* - * Interrupt mask bits. - */ -#define DC_IMR_TX_OK 0x00000001 -#define DC_IMR_TX_IDLE 0x00000002 -#define DC_IMR_TX_NOBUF 0x00000004 -#define DC_IMR_TX_JABBERTIMEO 0x00000008 -#define DC_IMR_LINKGOOD 0x00000010 -#define DC_IMR_TX_UNDERRUN 0x00000020 -#define DC_IMR_RX_OK 0x00000040 -#define DC_IMR_RX_NOBUF 0x00000080 -#define DC_IMR_RX_READ 0x00000100 -#define DC_IMR_RX_WATDOGTIMEO 0x00000200 -#define DC_IMR_TX_EARLY 0x00000400 -#define DC_IMR_TIMER_EXPIRED 0x00000800 -#define DC_IMR_LINKFAIL 0x00001000 -#define DC_IMR_BUS_ERR 0x00002000 -#define DC_IMR_RX_EARLY 0x00004000 -#define DC_IMR_ABNORMAL 0x00008000 -#define DC_IMR_NORMAL 0x00010000 -#define DC_IMR_100MBPSLINK 0x08000000 -#define DC_IMR_MAGICKPACK 0x10000000 - -#define DC_INTRS \ - (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ - DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ - DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) -/* - * Serial I/O (EEPROM/ROM) bits. - */ -#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ -#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ -#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ -#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ -#define DC_SIO_ROMDATA4 0x00000010 -#define DC_SIO_ROMDATA5 0x00000020 -#define DC_SIO_ROMDATA6 0x00000040 -#define DC_SIO_ROMDATA7 0x00000080 -#define DC_SIO_EESEL 0x00000800 -#define DC_SIO_ROMSEL 0x00001000 -#define DC_SIO_ROMCTL_WRITE 0x00002000 -#define DC_SIO_ROMCTL_READ 0x00004000 -#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ -#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ -#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ -#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ - -#define DC_EECMD_WRITE 0x140 -#define DC_EECMD_READ 0x180 -#define DC_EECMD_ERASE 0x1c0 - -#define DC_EE_NODEADDR_OFFSET 0x70 -#define DC_EE_NODEADDR 10 - -/* - * General purpose timer register - */ -#define DC_TIMER_VALUE 0x0000FFFF -#define DC_TIMER_CONTINUOUS 0x00010000 - -/* - * 10baseT status register - */ -#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ -#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ -#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ -#define DC_TSTAT_AUTOPOLARITY 0x00000008 -#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ -#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ -#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ -#define DC_TSTAT_REMFAULT 0x00000800 -#define DC_TSTAT_ANEGSTAT 0x00007000 -#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ -#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ - -#define DC_ASTAT_DISABLE 0x00000000 -#define DC_ASTAT_TXDISABLE 0x00001000 -#define DC_ASTAT_ABDETECT 0x00002000 -#define DC_ASTAT_ACKDETECT 0x00003000 -#define DC_ASTAT_CMPACKDETECT 0x00004000 -#define DC_ASTAT_AUTONEGCMP 0x00005000 -#define DC_ASTAT_LINKCHECK 0x00006000 - -/* - * PHY reset register - */ -#define DC_SIA_RESET 0x00000001 -#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ - -/* - * 10baseT control register - */ -#define DC_TCTL_ENCODER_ENB 0x00000001 -#define DC_TCTL_LOOPBACK 0x00000002 -#define DC_TCTL_DRIVER_ENB 0x00000004 -#define DC_TCTL_LNKPULSE_ENB 0x00000008 -#define DC_TCTL_HALFDUPLEX 0x00000040 -#define DC_TCTL_AUTONEGENBL 0x00000080 -#define DC_TCTL_RX_SQUELCH 0x00000100 -#define DC_TCTL_COLL_SQUELCH 0x00000200 -#define DC_TCTL_COLL_DETECT 0x00000400 -#define DC_TCTL_SQE_ENB 0x00000800 -#define DC_TCTL_LINKTEST 0x00001000 -#define DC_TCTL_AUTOPOLARITY 0x00002000 -#define DC_TCTL_SET_POL_PLUS 0x00004000 -#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ -#define DC_TCTL_100BTXHALF 0x00010000 -#define DC_TCTL_100BTXFULL 0x00020000 -#define DC_TCTL_100BT4 0x00040000 - -/* - * Watchdog timer register - */ -#define DC_WDOG_JABBERDIS 0x00000001 -#define DC_WDOG_HOSTUNJAB 0x00000002 -#define DC_WDOG_JABBERCLK 0x00000004 -#define DC_WDOG_RXWDOGDIS 0x00000010 -#define DC_WDOG_RXWDOGCLK 0x00000020 -#define DC_WDOG_MUSTBEZERO 0x00000100 -#define DC_WDOG_AUIBNC 0x00100000 -#define DC_WDOG_ACTIVITY 0x00200000 -#define DC_WDOG_RX_MATCH 0x00400000 -#define DC_WDOG_LINK 0x00800000 -#define DC_WDOG_CTLWREN 0x08000000 - -/* - * Size of a setup frame. - */ -#define DC_SFRAME_LEN 192 - -/* - * 21x4x TX/RX list structure. - */ - -struct dc_desc { - u_int32_t dc_status; - u_int32_t dc_ctl; - u_int32_t dc_ptr1; - u_int32_t dc_ptr2; -}; - -#define dc_data dc_ptr1 -#define dc_next dc_ptr2 - -#define DC_RXSTAT_FIFOOFLOW 0x00000001 -#define DC_RXSTAT_CRCERR 0x00000002 -#define DC_RXSTAT_DRIBBLE 0x00000004 -#define DC_RXSTAT_MIIERE 0x00000008 -#define DC_RXSTAT_WATCHDOG 0x00000010 -#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ -#define DC_RXSTAT_COLLSEEN 0x00000040 -#define DC_RXSTAT_GIANT 0x00000080 -#define DC_RXSTAT_LASTFRAG 0x00000100 -#define DC_RXSTAT_FIRSTFRAG 0x00000200 -#define DC_RXSTAT_MULTICAST 0x00000400 -#define DC_RXSTAT_RUNT 0x00000800 -#define DC_RXSTAT_RXTYPE 0x00003000 -#define DC_RXSTAT_DE 0x00004000 -#define DC_RXSTAT_RXERR 0x00008000 -#define DC_RXSTAT_RXLEN 0x3FFF0000 -#define DC_RXSTAT_OWN 0x80000000 - -#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) -#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) - -#define DC_RXCTL_BUFLEN1 0x00000FFF -#define DC_RXCTL_BUFLEN2 0x00FFF000 -#define DC_RXCTL_RLINK 0x01000000 -#define DC_RXCTL_RLAST 0x02000000 - -#define DC_TXSTAT_DEFER 0x00000001 -#define DC_TXSTAT_UNDERRUN 0x00000002 -#define DC_TXSTAT_LINKFAIL 0x00000003 -#define DC_TXSTAT_COLLCNT 0x00000078 -#define DC_TXSTAT_SQE 0x00000080 -#define DC_TXSTAT_EXCESSCOLL 0x00000100 -#define DC_TXSTAT_LATECOLL 0x00000200 -#define DC_TXSTAT_NOCARRIER 0x00000400 -#define DC_TXSTAT_CARRLOST 0x00000800 -#define DC_TXSTAT_JABTIMEO 0x00004000 -#define DC_TXSTAT_ERRSUM 0x00008000 -#define DC_TXSTAT_OWN 0x80000000 - -#define DC_TXCTL_BUFLEN1 0x000007FF -#define DC_TXCTL_BUFLEN2 0x003FF800 -#define DC_TXCTL_FILTTYPE0 0x00400000 -#define DC_TXCTL_PAD 0x00800000 -#define DC_TXCTL_TLINK 0x01000000 -#define DC_TXCTL_TLAST 0x02000000 -#define DC_TXCTL_NOCRC 0x04000000 -#define DC_TXCTL_SETUP 0x08000000 -#define DC_TXCTL_FILTTYPE1 0x10000000 -#define DC_TXCTL_FIRSTFRAG 0x20000000 -#define DC_TXCTL_LASTFRAG 0x40000000 -#define DC_TXCTL_FINT 0x80000000 - -#define DC_FILTER_PERFECT 0x00000000 -#define DC_FILTER_HASHPERF 0x00400000 -#define DC_FILTER_INVERSE 0x10000000 -#define DC_FILTER_HASHONLY 0x10400000 - -#define DC_MAXFRAGS 16 -#ifdef DEVICE_POLLING -#define DC_RX_LIST_CNT 192 -#else -#define DC_RX_LIST_CNT 64 -#endif -#define DC_TX_LIST_CNT 256 -#define DC_MIN_FRAMELEN 60 -#define DC_RXLEN 1536 - -#define DC_INC(x, y) (x) = (x + 1) % y - -struct dc_list_data { - struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; - struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; -}; - -struct dc_chain_data { - struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; - struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; - u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; - u_int8_t dc_pad[DC_MIN_FRAMELEN]; - int dc_tx_prod; - int dc_tx_cons; - int dc_tx_cnt; - int dc_rx_prod; -}; - -struct dc_mediainfo { - int dc_media; - u_int8_t *dc_gp_ptr; - u_int8_t dc_gp_len; - u_int8_t *dc_reset_ptr; - u_int8_t dc_reset_len; - struct dc_mediainfo *dc_next; -}; - - -struct dc_type { - u_int16_t dc_vid; - u_int16_t dc_did; - char *dc_name; - int dc_devsig; - int dc_bus; - int dc_dev; - int dc_fun; -}; - -struct dc_mii_frame { - u_int8_t mii_stdelim; - u_int8_t mii_opcode; - u_int8_t mii_phyaddr; - u_int8_t mii_regaddr; - u_int8_t mii_turnaround; - u_int16_t mii_data; -}; - -/* - * MII constants - */ -#define DC_MII_STARTDELIM 0x01 -#define DC_MII_READOP 0x02 -#define DC_MII_WRITEOP 0x01 -#define DC_MII_TURNAROUND 0x02 - - -/* - * Registers specific to clone devices. - * This mainly relates to RX filter programming: not all 21x4x clones - * use the standard DEC filter programming mechanism. - */ - -/* - * ADMtek specific registers and constants for the AL981 and AN985. - * The AN985 doesn't use the magic PHY registers. - */ -#define DC_AL_CR 0x88 /* command register */ -#define DC_AL_PAR0 0xA4 /* station address */ -#define DC_AL_PAR1 0xA8 /* station address */ -#define DC_AL_MAR0 0xAC /* multicast hash filter */ -#define DC_AL_MAR1 0xB0 /* multicast hash filter */ -#define DC_AL_BMCR 0xB4 /* built in PHY control */ -#define DC_AL_BMSR 0xB8 /* built in PHY status */ -#define DC_AL_VENID 0xBC /* built in PHY ID0 */ -#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ -#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ -#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ -#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ - -#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */ -#define DC_ADMTEK_PHYADDR 0x1 -#define DC_AL_EE_NODEADDR 4 -/* End of ADMtek specific registers */ - -/* - * ASIX specific registers. - */ -#define DC_AX_FILTIDX 0x68 /* RX filter index */ -#define DC_AX_FILTDATA 0x70 /* RX filter data */ - -/* - * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). - */ -#define DC_AX_NETCFG_RX_BROAD 0x00000100 - -/* - * RX Filter Index Register values - */ -#define DC_AX_FILTIDX_PAR0 0x00000000 -#define DC_AX_FILTIDX_PAR1 0x00000001 -#define DC_AX_FILTIDX_MAR0 0x00000002 -#define DC_AX_FILTIDX_MAR1 0x00000003 -/* End of ASIX specific registers */ - -/* - * Macronix specific registers. The Macronix chips have a special - * register for reading the NWAY status, which we don't use, plus - * a magic packet register, which we need to tweak a bit per the - * Macronix application notes. - */ -#define DC_MX_MAGICPACKET 0x80 -#define DC_MX_NWAYSTAT 0xA0 - -/* - * Magic packet register - */ -#define DC_MX_MPACK_DISABLE 0x00400000 - -/* - * NWAY status register. - */ -#define DC_MX_NWAY_10BTHALF 0x08000000 -#define DC_MX_NWAY_10BTFULL 0x10000000 -#define DC_MX_NWAY_100BTHALF 0x20000000 -#define DC_MX_NWAY_100BTFULL 0x40000000 -#define DC_MX_NWAY_100BT4 0x80000000 - -/* - * These are magic values that must be written into CSR16 - * (DC_MX_MAGICPACKET) in order to put the chip into proper - * operating mode. The magic numbers are documented in the - * Macronix 98715 application notes. - */ -#define DC_MX_MAGIC_98713 0x0F370000 -#define DC_MX_MAGIC_98713A 0x0B3C0000 -#define DC_MX_MAGIC_98715 0x0B3C0000 -#define DC_MX_MAGIC_98725 0x0B3C0000 -/* End of Macronix specific registers */ - -/* - * PNIC 82c168/82c169 specific registers. - * The PNIC has its own special NWAY support, which doesn't work, - * and shortcut ways of reading the EEPROM and MII bus. - */ -#define DC_PN_GPIO 0x60 /* general purpose pins control */ -#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ -#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ -#define DC_PN_MII 0xA0 /* MII access register */ -#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ - -/* Serial I/O EEPROM register */ -#define DC_PN_SIOCTL_DATA 0x0000003F -#define DC_PN_SIOCTL_OPCODE 0x00000300 -#define DC_PN_SIOCTL_BUSY 0x80000000 - -#define DC_PN_EEOPCODE_ERASE 0x00000300 -#define DC_PN_EEOPCODE_READ 0x00000600 -#define DC_PN_EEOPCODE_WRITE 0x00000100 - -/* - * The first two general purpose pins control speed selection and - * 100Mbps loopback on the 82c168 chip. The control bits should always - * be set (to make the data pins outputs) and the speed selction and - * loopback bits set accordingly when changing media. Physically, this - * will set the state of a relay mounted on the card. - */ -#define DC_PN_GPIO_DATA0 0x000000001 -#define DC_PN_GPIO_DATA1 0x000000002 -#define DC_PN_GPIO_DATA2 0x000000004 -#define DC_PN_GPIO_DATA3 0x000000008 -#define DC_PN_GPIO_CTL0 0x000000010 -#define DC_PN_GPIO_CTL1 0x000000020 -#define DC_PN_GPIO_CTL2 0x000000040 -#define DC_PN_GPIO_CTL3 0x000000080 -#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ -#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ -#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 -#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 -#define DC_PN_GPIO_SETBIT(sc, r) \ - DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) -#define DC_PN_GPIO_CLRBIT(sc, r) \ - { \ - DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ - DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ - } - -/* shortcut MII access register */ -#define DC_PN_MII_DATA 0x0000FFFF -#define DC_PN_MII_RESERVER 0x00020000 -#define DC_PN_MII_REGADDR 0x007C0000 -#define DC_PN_MII_PHYADDR 0x0F800000 -#define DC_PN_MII_OPCODE 0x30000000 -#define DC_PN_MII_BUSY 0x80000000 - -#define DC_PN_MIIOPCODE_READ 0x60020000 -#define DC_PN_MIIOPCODE_WRITE 0x50020000 - -/* Internal NWAY bits */ -#define DC_PN_NWAY_RESET 0x00000001 /* reset */ -#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ -#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ -#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ -#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ -#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ -#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ -#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ -#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ -#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ -#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ -#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ -#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ -#define DC_PN_NWAY_CAP10HDX 0x00002000 -#define DC_PN_NWAY_CAP10FDX 0x00004000 -#define DC_PN_NWAY_CAP100FDX 0x00008000 -#define DC_PN_NWAY_CAP100HDX 0x00010000 -#define DC_PN_NWAY_CAP100T4 0x00020000 -#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ -#define DC_PN_NWAY_REMFAULT 0x04000000 -#define DC_PN_NWAY_LPAR10HDX 0x08000000 -#define DC_PN_NWAY_LPAR10FDX 0x10000000 -#define DC_PN_NWAY_LPAR100FDX 0x20000000 -#define DC_PN_NWAY_LPAR100HDX 0x40000000 -#define DC_PN_NWAY_LPAR100T4 0x80000000 - -/* End of PNIC specific registers */ - -/* - * CONEXANT specific registers. - */ - -#define DC_CONEXANT_PHYADDR 0x1 -#define DC_CONEXANT_EE_NODEADDR 0x19A - -/* End of CONEXANT specific registers */ - - -struct dc_softc { - struct arpcom arpcom; /* interface info */ - rtems_irq_connect_data irqInfo; - volatile u_int32_t membase; - rtems_id daemontid; -#if 0 - bus_space_handle_t dc_bhandle; /* bus space handle */ - bus_space_tag_t dc_btag; /* bus space tag */ - void *dc_intrhand; - struct resource *dc_irq; - struct resource *dc_res; -#endif - struct dc_type *dc_info; /* adapter info */ -/* device_t dc_miibus; */ - u_int8_t dc_unit; /* interface number */ - char *dc_name; - u_int8_t dc_type; - u_int8_t dc_pmode; - u_int8_t dc_link; - u_int8_t dc_cachesize; - int dc_romwidth; - int dc_pnic_rx_bug_save; - unsigned char *dc_pnic_rx_buf; - int dc_if_flags; - int dc_if_media; - u_int32_t dc_flags; - u_int32_t dc_txthresh; - u_int8_t *dc_srom; - struct dc_mediainfo *dc_mi; -/* - struct callout_handle dc_stat_ch; -*/ - struct dc_list_data *dc_ldata; - struct dc_chain_data dc_cdata; -#ifdef __alpha__ - int dc_srm_media; -#endif -#ifdef DEVICE_POLLING - int rxcycles; /* ... when polling */ -#endif - int suspended; /* 0 = normal 1 = suspended */ - - u_int32_t saved_maps[5]; /* pci data */ - u_int32_t saved_biosaddr; - u_int8_t saved_intline; - u_int8_t saved_cachelnsz; - u_int8_t saved_lattimer; -}; - -#define DC_TX_POLL 0x00000001 -#define DC_TX_COALESCE 0x00000002 -#define DC_TX_ADMTEK_WAR 0x00000004 -#define DC_TX_USE_TX_INTR 0x00000008 -#define DC_RX_FILTER_TULIP 0x00000010 -#define DC_TX_INTR_FIRSTFRAG 0x00000020 -#define DC_PNIC_RX_BUG_WAR 0x00000040 -#define DC_TX_FIXED_RING 0x00000080 -#define DC_TX_STORENFWD 0x00000100 -#define DC_REDUCED_MII_POLL 0x00000200 -#define DC_TX_INTR_ALWAYS 0x00000400 -#define DC_21143_NWAY 0x00000800 -#define DC_128BIT_HASH 0x00001000 -#define DC_64BIT_HASH 0x00002000 -#define DC_TULIP_LEDS 0x00004000 -#define DC_TX_ONE 0x00008000 - -/* - * register space access macros - */ -#define _readl_(addr) (*(volatile unsigned int *)((void *)(addr))) -#define _writel_(b, addr) (*(volatile unsigned int *)((void *)(addr)) = (b)) - -#define CSR_READ_4(sc, reg) _readl_(((sc->membase)+(reg))) -#define CSR_WRITE_4(sc, reg, val) _writel_(val, ((sc->membase)+(reg))) - - - - - - -#define DC_TIMEOUT 1000 -#define ETHER_ALIGN 2 - -/* - * General constants that are fun to know. - */ - -/* - * DEC PCI vendor ID - */ -#define DC_VENDORID_DEC 0x1011 - -/* - * DEC/Intel 21143 PCI device ID - */ -#define DC_DEVICEID_21143 0x0019 - -/* - * Macronix PCI vendor ID - */ -#define DC_VENDORID_MX 0x10D9 - -/* - * Macronix PMAC device IDs. - */ -#define DC_DEVICEID_98713 0x0512 -#define DC_DEVICEID_987x5 0x0531 -#define DC_DEVICEID_98727 0x0532 -#define DC_DEVICEID_98732 0x0532 - -/* Macronix PCI revision codes. */ -#define DC_REVISION_98713 0x00 -#define DC_REVISION_98713A 0x10 -#define DC_REVISION_98715 0x20 -#define DC_REVISION_98715AEC_C 0x25 -#define DC_REVISION_98725 0x30 - -/* - * Compex PCI vendor ID. - */ -#define DC_VENDORID_CP 0x11F6 - -/* - * Compex PMAC PCI device IDs. - */ -#define DC_DEVICEID_98713_CP 0x9881 - -/* - * Lite-On PNIC PCI vendor ID - */ -#define DC_VENDORID_LO 0x11AD - -/* - * 82c168/82c169 PNIC device IDs. Both chips have the same device - * ID but different revisions. Revision 0x10 is the 82c168, and - * 0x20 is the 82c169. - */ -#define DC_DEVICEID_82C168 0x0002 - -#define DC_REVISION_82C168 0x10 -#define DC_REVISION_82C169 0x20 - -/* - * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A - * with wake on lan/magic packet support. - */ -#define DC_DEVICEID_82C115 0xc115 - -/* - * Davicom vendor ID. - */ -#define DC_VENDORID_DAVICOM 0x1282 - -/* - * Davicom device IDs. - */ -#define DC_DEVICEID_DM9009 0x9009 -#define DC_DEVICEID_DM9100 0x9100 -#define DC_DEVICEID_DM9102 0x9102 - -/* - * The DM9102A has the same PCI device ID as the DM9102, - * but a higher revision code. - */ -#define DC_REVISION_DM9102 0x10 -#define DC_REVISION_DM9102A 0x30 - -/* - * ADMtek vendor ID. - */ -#define DC_VENDORID_ADMTEK 0x1317 - -/* - * ADMtek device IDs. - */ -#define DC_DEVICEID_AL981 0x0981 -#define DC_DEVICEID_AN985 0x0985 - -/* - * ASIX vendor ID. - */ -#define DC_VENDORID_ASIX 0x125B - -/* - * ASIX device IDs. - */ -#define DC_DEVICEID_AX88140A 0x1400 - -/* - * The ASIX AX88140 and ASIX AX88141 have the same vendor and - * device IDs but different revision values. - */ -#define DC_REVISION_88140 0x00 -#define DC_REVISION_88141 0x10 - -/* - * Accton vendor ID. - */ -#define DC_VENDORID_ACCTON 0x1113 - -/* - * Accton device IDs. - */ -#define DC_DEVICEID_EN1217 0x1217 -#define DC_DEVICEID_EN2242 0x1216 - -/* - * Conexant vendor ID. - */ -#define DC_VENDORID_CONEXANT 0x14f1 - -/* - * Conexant device IDs. - */ -#define DC_DEVICEID_RS7112 0x1803 - -/* - * PCI low memory base and low I/O base register, and - * other PCI registers. - */ - -#define DC_PCI_CFID 0x00 /* Id */ -#define DC_PCI_CFCS 0x04 /* Command and status */ -#define DC_PCI_CFRV 0x08 /* Revision */ -#define DC_PCI_CFLT 0x0C /* Latency timer */ -#define DC_PCI_CFBIO 0x10 /* Base I/O address */ -#define DC_PCI_CFBMA 0x14 /* Base memory address */ -#define DC_PCI_CCIS 0x28 /* Card info struct */ -#define DC_PCI_CSID 0x2C /* Subsystem ID */ -#define DC_PCI_CBER 0x30 /* Expansion ROM base address */ -#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ -#define DC_PCI_CFIT 0x3C /* Interrupt */ -#define DC_PCI_CFDD 0x40 /* Device and driver area */ -#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ -#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ -#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ -#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ -#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ -#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ -#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ - -/* PCI ID register */ -#define DC_CFID_VENDOR 0x0000FFFF -#define DC_CFID_DEVICE 0xFFFF0000 - -/* PCI command/status register */ -#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ -#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ -#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ -#define DC_CFCS_MWI_ENB 0x00000010 /* mem write and inval enable */ -#define DC_CFCS_PARITYERR_ENB 0x00000040 /* parity error enable */ -#define DC_CFCS_SYSERR_ENB 0x00000100 /* system error enable */ -#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ -#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ -#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ -#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ -#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ -#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ -#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ -#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ - -/* PCI revision register */ -#define DC_CFRV_STEPPING 0x0000000F -#define DC_CFRV_REVISION 0x000000F0 -#define DC_CFRV_SUBCLASS 0x00FF0000 -#define DC_CFRV_BASECLASS 0xFF000000 - -#define DC_21143_PB_REV 0x00000030 -#define DC_21143_TB_REV 0x00000030 -#define DC_21143_PC_REV 0x00000030 -#define DC_21143_TC_REV 0x00000030 -#define DC_21143_PD_REV 0x00000041 -#define DC_21143_TD_REV 0x00000041 - -/* PCI latency timer register */ -#define DC_CFLT_CACHELINESIZE 0x000000FF -#define DC_CFLT_LATENCYTIMER 0x0000FF00 - -/* PCI subsystem ID register */ -#define DC_CSID_VENDOR 0x0000FFFF -#define DC_CSID_DEVICE 0xFFFF0000 - -/* PCI cababilities pointer */ -#define DC_CCAP_OFFSET 0x000000FF - -/* PCI interrupt config register */ -#define DC_CFIT_INTLINE 0x000000FF -#define DC_CFIT_INTPIN 0x0000FF00 -#define DC_CFIT_MIN_GNT 0x00FF0000 -#define DC_CFIT_MAX_LAT 0xFF000000 - -/* PCI capability register */ -#define DC_CCID_CAPID 0x000000FF -#define DC_CCID_NEXTPTR 0x0000FF00 -#define DC_CCID_PM_VERS 0x00070000 -#define DC_CCID_PME_CLK 0x00080000 -#define DC_CCID_DVSPEC_INT 0x00200000 -#define DC_CCID_STATE_D1 0x02000000 -#define DC_CCID_STATE_D2 0x04000000 -#define DC_CCID_PME_D0 0x08000000 -#define DC_CCID_PME_D1 0x10000000 -#define DC_CCID_PME_D2 0x20000000 -#define DC_CCID_PME_D3HOT 0x40000000 -#define DC_CCID_PME_D3COLD 0x80000000 - -/* PCI power management control/status register */ -#define DC_CPMC_STATE 0x00000003 -#define DC_CPMC_PME_ENB 0x00000100 -#define DC_CPMC_PME_STS 0x00008000 - -#define DC_PSTATE_D0 0x0 -#define DC_PSTATE_D1 0x1 -#define DC_PSTATE_D2 0x2 -#define DC_PSTATE_D3 0x3 - -/* Device specific region */ -/* Configuration and driver area */ -#define DC_CFDD_DRVUSE 0x0000FFFF -#define DC_CFDD_SNOOZE_MODE 0x40000000 -#define DC_CFDD_SLEEP_MODE 0x80000000 - -/* Configuration wake-up command register */ -#define DC_CWUC_MUST_BE_ZERO 0x00000001 -#define DC_CWUC_SECUREON_ENB 0x00000002 -#define DC_CWUC_FORCE_WUL 0x00000004 -#define DC_CWUC_BNC_ABILITY 0x00000008 -#define DC_CWUC_AUI_ABILITY 0x00000010 -#define DC_CWUC_TP10_ABILITY 0x00000020 -#define DC_CWUC_MII_ABILITY 0x00000040 -#define DC_CWUC_SYM_ABILITY 0x00000080 -#define DC_CWUC_LOCK 0x00000100 - -/* - * SROM nonsense. - */ - -#define DC_IB_CTLRCNT 0x13 -#define DC_IB_LEAF0_CNUM 0x1A -#define DC_IB_LEAF0_OFFSET 0x1B - -struct dc_info_leaf { - u_int16_t dc_conntype; - u_int8_t dc_blkcnt; - u_int8_t dc_rsvd; - u_int16_t dc_infoblk; -}; - -#define DC_CTYPE_10BT 0x0000 -#define DC_CTYPE_10BT_NWAY 0x0100 -#define DC_CTYPE_10BT_FDX 0x0204 -#define DC_CTYPE_10B2 0x0001 -#define DC_CTYPE_10B5 0x0002 -#define DC_CTYPE_100BT 0x0003 -#define DC_CTYPE_100BT_FDX 0x0205 -#define DC_CTYPE_100T4 0x0006 -#define DC_CTYPE_100FX 0x0007 -#define DC_CTYPE_100FX_FDX 0x0208 -#define DC_CTYPE_MII_10BT 0x0009 -#define DC_CTYPE_MII_10BT_FDX 0x020A -#define DC_CTYPE_MII_100BT 0x000D -#define DC_CTYPE_MII_100BT_FDX 0x020E -#define DC_CTYPE_MII_100T4 0x000F -#define DC_CTYPE_MII_100FX 0x0010 -#define DC_CTYPE_MII_100FX_FDX 0x0211 -#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 -#define DC_CTYPE_PUP_AUTOSENSE 0x8800 -#define DC_CTYPE_NOMEDIA 0xFFFF - -#define DC_EBLOCK_SIA 0x0002 -#define DC_EBLOCK_MII 0x0003 -#define DC_EBLOCK_SYM 0x0004 -#define DC_EBLOCK_RESET 0x0005 -#define DC_EBLOCK_PHY_SHUTDOWN 0x0006 - -struct dc_leaf_hdr { - u_int16_t dc_mtype; - u_int8_t dc_mcnt; - u_int8_t dc_rsvd; -}; - -struct dc_eblock_hdr { - u_int8_t dc_len; - u_int8_t dc_type; -}; - -struct dc_eblock_sia { - struct dc_eblock_hdr dc_sia_hdr; - u_int8_t dc_sia_code; - u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ - u_int8_t dc_sia_gpio_ctl[2]; - u_int8_t dc_sia_gpio_dat[2]; -}; - -#define DC_SIA_CODE_10BT 0x00 -#define DC_SIA_CODE_10B2 0x01 -#define DC_SIA_CODE_10B5 0x02 -#define DC_SIA_CODE_10BT_FDX 0x04 -#define DC_SIA_CODE_EXT 0x40 - -/* - * Note that the first word in the gpr and reset - * sequences is always a control word. - */ -struct dc_eblock_mii { - struct dc_eblock_hdr dc_mii_hdr; - u_int8_t dc_mii_phynum; - u_int8_t dc_gpr_len; -/* u_int16_t dc_gpr_dat[n]; */ -/* u_int8_t dc_reset_len; */ -/* u_int16_t dc_reset_dat[n]; */ -/* There are other fields after these, but we don't - * care about them since they can be determined by looking - * at the PHY. - */ -}; - -struct dc_eblock_sym { - struct dc_eblock_hdr dc_sym_hdr; - u_int8_t dc_sym_code; - u_int8_t dc_sym_gpio_ctl[2]; - u_int8_t dc_sym_gpio_dat[2]; - u_int8_t dc_sym_cmd[2]; -}; - -#define DC_SYM_CODE_100BT 0x03 -#define DC_SYM_CODE_100BT_FDX 0x05 -#define DC_SYM_CODE_100T4 0x06 -#define DC_SYM_CODE_100FX 0x07 -#define DC_SYM_CODE_100FX_FDX 0x08 - -struct dc_eblock_reset { - struct dc_eblock_hdr dc_reset_hdr; - u_int8_t dc_reset_len; -/* u_int16_t dc_reset_dat[n]; */ -}; - -#ifdef __alpha__ -#undef vtophys -#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) -#endif diff --git a/c/src/libchip/network/if_fxpvar.h b/c/src/libchip/network/if_fxpvar.h deleted file mode 100644 index f29f52c080..0000000000 --- a/c/src/libchip/network/if_fxpvar.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) 1995, David Greenman - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice unmodified, this list of conditions, and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD: src/sys/dev/fxp/if_fxpvar.h,v 1.17.2.3 2001/06/08 20:36:58 jlemon Exp $ - */ - -/* - * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast - * Ethernet driver - */ - -/* - * Number of transmit control blocks. This determines the number - * of transmit buffers that can be chained in the CB list. - * This must be a power of two. - */ -#define FXP_NTXCB 128 - -/* - * Number of completed TX commands at which point an interrupt - * will be generated to garbage collect the attached buffers. - * Must be at least one less than FXP_NTXCB, and should be - * enough less so that the transmitter doesn't becomes idle - * during the buffer rundown (which would reduce performance). - */ -#define FXP_CXINT_THRESH 120 - -/* - * TxCB list index mask. This is used to do list wrap-around. - */ -#define FXP_TXCB_MASK (FXP_NTXCB - 1) - -/* - * Number of receive frame area buffers. These are large so chose - * wisely. - */ -#if 0 -#define FXP_NRFABUFS 64 -#else -#define FXP_NRFABUFS 16 -#endif -/* - * Maximum number of seconds that the receiver can be idle before we - * assume it's dead and attempt to reset it by reprogramming the - * multicast filter. This is part of a work-around for a bug in the - * NIC. See fxp_stats_update(). - */ -#define FXP_MAX_RX_IDLE 15 - -#if __FreeBSD_version < 500000 -#define FXP_LOCK(_sc) -#define FXP_UNLOCK(_sc) -#define mtx_init(a, b, c) -#define mtx_destroy(a) -struct mtx { int dummy; }; -#else -#define FXP_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) -#define FXP_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) -#endif - -#ifdef __alpha__ -#undef vtophys -#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va)) -#endif /* __alpha__ */ - -/* - * NOTE: Elements are ordered for optimal cacheline behavior, and NOT - * for functional grouping. - */ -struct fxp_softc { - struct arpcom arpcom; /* per-interface network data */ -#ifdef NOTUSED - struct resource *mem; /* resource descriptor for registers */ - int rtp; /* register resource type */ - int rgd; /* register descriptor in use */ - struct resource *irq; /* resource descriptor for interrupt */ -#endif - void *ih; /* interrupt handler cookie */ - struct mtx sc_mtx; -#ifdef NOTUSED /* change for RTEMS */ - bus_space_tag_t sc_st; /* bus space tag */ - bus_space_handle_t sc_sh; /* bus space handle */ -#else - unsigned char pci_bus; /* RTEMS PCI bus number */ - unsigned char pci_dev; /* RTEMS PCI slot/device number */ - unsigned char pci_fun; /* RTEMS PCI function number */ - bool pci_regs_are_io; /* RTEMS dev regs are I/O mapped */ - u_int32_t pci_regs_base; /* RTEMS i386 register base */ - rtems_id daemonTid; /* Task ID of deamon */ - rtems_vector_number irq_num; - -#endif - struct mbuf *rfa_headm; /* first mbuf in receive frame area */ - struct mbuf *rfa_tailm; /* last mbuf in receive frame area */ - struct fxp_cb_tx *cbl_first; /* first active TxCB in list */ - int tx_queued; /* # of active TxCB's */ - int need_mcsetup; /* multicast filter needs programming */ - struct fxp_cb_tx *cbl_last; /* last active TxCB in list */ - struct fxp_stats *fxp_stats; /* Pointer to interface stats */ - int rx_idle_secs; /* # of seconds RX has been idle */ - enum {fxp_timeout_stopped,fxp_timeout_running,fxp_timeout_stop_rq} - stat_ch; /* status of status updater */ - struct fxp_cb_tx *cbl_base; /* base of TxCB list */ - struct fxp_cb_mcs *mcsp; /* Pointer to mcast setup descriptor */ -#ifdef NOTUSED - struct ifmedia sc_media; /* media information */ - device_t miibus; - device_t dev; -#endif - int eeprom_size; /* size of serial EEPROM */ - int suspended; /* 0 = normal 1 = suspended (APM) */ - int cu_resume_bug; - int chip; - int flags; - u_int32_t saved_maps[5]; /* pci data */ - u_int32_t saved_biosaddr; - u_int8_t saved_intline; - u_int8_t saved_cachelnsz; - u_int8_t saved_lattimer; -}; - -#define FXP_CHIP_82557 1 /* 82557 chip type */ - -#define FXP_FLAG_MWI_ENABLE 0x0001 /* MWI enable */ -#define FXP_FLAG_READ_ALIGN 0x0002 /* align read access with cacheline */ -#define FXP_FLAG_WRITE_ALIGN 0x0004 /* end write on cacheline */ -#define FXP_FLAG_EXT_TXCB 0x0008 /* enable use of extended TXCB */ -#define FXP_FLAG_SERIAL_MEDIA 0x0010 /* 10Mbps serial interface */ -#define FXP_FLAG_LONG_PKT_EN 0x0020 /* enable long packet reception */ -#define FXP_FLAG_ALL_MCAST 0x0040 /* accept all multicast frames */ -#define FXP_FLAG_CU_RESUME_BUG 0x0080 /* requires workaround for CU_RESUME */ - -/* Macros to ease CSR access. */ -#if 0 -#define CSR_READ_1(sc, reg) \ - bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) -#define CSR_READ_2(sc, reg) \ - bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) -#define CSR_READ_4(sc, reg) \ - bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) -#define CSR_WRITE_1(sc, reg, val) \ - bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) -#define CSR_WRITE_2(sc, reg, val) \ - bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) -#define CSR_WRITE_4(sc, reg, val) \ - bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) -#else -#define CSR_READ_1(sc, reg) fxp_csr_read_1(sc,reg) -#define CSR_READ_2(sc, reg) fxp_csr_read_2(sc,reg) -#define CSR_READ_4(sc, reg) fxp_csr_read_4(sc,reg) - -#define CSR_WRITE_1(sc, reg, val) \ - do { \ - if ((sc)->pci_regs_are_io) \ - outport_byte((sc)->pci_regs_base+(reg),val); \ - else \ - *((volatile u_int8_t*)((sc)->pci_regs_base)+(reg)) = val; \ - }while (0) - -#define CSR_WRITE_2(sc, reg, val) \ - do { \ - if ((sc)->pci_regs_are_io) \ - outport_word((sc)->pci_regs_base+(reg),val); \ - else \ - *((volatile u_int16_t*)((u_int8_t*)((sc)->pci_regs_base)+(reg))) = val; \ - }while (0) - -#define CSR_WRITE_4(sc, reg, val) \ - do { \ - if ((sc)->pci_regs_are_io) \ - outport_long((sc)->pci_regs_base+(reg),val); \ - else \ - *((volatile u_int32_t*)((u_int8_t*)((sc)->pci_regs_base)+(reg))) = val; \ - }while (0) - -#endif - -#define sc_if arpcom.ac_if - -#define FXP_UNIT(_sc) (_sc)->arpcom.ac_if.if_unit diff --git a/c/src/libchip/network/open_eth.h b/c/src/libchip/network/open_eth.h deleted file mode 100644 index 66a5204230..0000000000 --- a/c/src/libchip/network/open_eth.h +++ /dev/null @@ -1,173 +0,0 @@ -/* Opencores ethernet MAC driver */ -/* adapted from linux driver by Jiri Gaisler */ - -#ifndef _OPEN_ETH_ -#define _OPEN_ETH_ - - -/* Configuration Information */ - -typedef struct { - void *base_address; - uint32_t vector; - uint32_t txd_count; - uint32_t rxd_count; - uint32_t en100MHz; -} open_eth_configuration_t; - - -/* Ethernet buffer descriptor */ - -typedef struct _oeth_rxtxdesc { - volatile uint32_t len_status; /* Length and status */ - volatile uint32_t *addr; /* Buffer pointer */ -} oeth_rxtxdesc; - -/* Ethernet configuration registers */ - -typedef struct _oeth_regs { - volatile uint32_t moder; /* Mode Register */ - volatile uint32_t int_src; /* Interrupt Source Register */ - volatile uint32_t int_mask; /* Interrupt Mask Register */ - volatile uint32_t ipgt; /* Back to Bak Inter Packet Gap Register */ - volatile uint32_t ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */ - volatile uint32_t ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */ - volatile uint32_t packet_len; /* Packet Length Register (min. and max.) */ - volatile uint32_t collconf; /* Collision and Retry Configuration Register */ - volatile uint32_t tx_bd_num; /* Transmit Buffer Descriptor Number Register */ - volatile uint32_t ctrlmoder; /* Control Module Mode Register */ - volatile uint32_t miimoder; /* MII Mode Register */ - volatile uint32_t miicommand; /* MII Command Register */ - volatile uint32_t miiaddress; /* MII Address Register */ - volatile uint32_t miitx_data; /* MII Transmit Data Register */ - volatile uint32_t miirx_data; /* MII Receive Data Register */ - volatile uint32_t miistatus; /* MII Status Register */ - volatile uint32_t mac_addr0; /* MAC Individual Address Register 0 */ - volatile uint32_t mac_addr1; /* MAC Individual Address Register 1 */ - volatile uint32_t hash_addr0; /* Hash Register 0 */ - volatile uint32_t hash_addr1; /* Hash Register 1 */ - volatile uint32_t txctrl; /* Transmitter control register */ - uint32_t empty[235]; /* Unused space */ - oeth_rxtxdesc xd[128]; /* TX & RX descriptors */ -} oeth_regs; - -#define OETH_TOTAL_BD 128 -#define OETH_MAXBUF_LEN 0x610 - -/* Tx BD */ -#define OETH_TX_BD_READY 0x8000 /* Tx BD Ready */ -#define OETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */ -#define OETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */ -#define OETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */ -#define OETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */ - -#define OETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */ -#define OETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */ -#define OETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */ -#define OETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */ -#define OETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */ -#define OETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */ -#define OETH_TX_BD_STATS (OETH_TX_BD_UNDERRUN | \ - OETH_TX_BD_RETRY | \ - OETH_TX_BD_RETLIM | \ - OETH_TX_BD_LATECOL | \ - OETH_TX_BD_DEFER | \ - OETH_TX_BD_CARRIER) - -/* Rx BD */ -#define OETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */ -#define OETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */ -#define OETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */ - -#define OETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */ -#define OETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */ -#define OETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */ -#define OETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */ -#define OETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */ -#define OETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */ -#define OETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */ -#define OETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */ -#define OETH_RX_BD_STATS (OETH_RX_BD_MISS | \ - OETH_RX_BD_OVERRUN | \ - OETH_RX_BD_INVSIMB | \ - OETH_RX_BD_DRIBBLE | \ - OETH_RX_BD_TOOLONG | \ - OETH_RX_BD_SHORT | \ - OETH_RX_BD_CRCERR | \ - OETH_RX_BD_LATECOL) - -/* MODER Register */ -#define OETH_MODER_RXEN 0x00000001 /* Receive Enable */ -#define OETH_MODER_TXEN 0x00000002 /* Transmit Enable */ -#define OETH_MODER_NOPRE 0x00000004 /* No Preamble */ -#define OETH_MODER_BRO 0x00000008 /* Reject Broadcast */ -#define OETH_MODER_IAM 0x00000010 /* Use Individual Hash */ -#define OETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */ -#define OETH_MODER_IFG 0x00000040 /* Min. IFG not required */ -#define OETH_MODER_LOOPBCK 0x00000080 /* Loop Back */ -#define OETH_MODER_NOBCKOF 0x00000100 /* No Backoff */ -#define OETH_MODER_EXDFREN 0x00000200 /* Excess Defer */ -#define OETH_MODER_FULLD 0x00000400 /* Full Duplex */ -#define OETH_MODER_RST 0x00000800 /* Reset MAC */ -#define OETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */ -#define OETH_MODER_CRCEN 0x00002000 /* CRC Enable */ -#define OETH_MODER_HUGEN 0x00004000 /* Huge Enable */ -#define OETH_MODER_PAD 0x00008000 /* Pad Enable */ -#define OETH_MODER_RECSMALL 0x00010000 /* Receive Small */ - -/* Interrupt Source Register */ -#define OETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */ -#define OETH_INT_TXE 0x00000002 /* Transmit Error IRQ */ -#define OETH_INT_RXF 0x00000004 /* Receive Frame IRQ */ -#define OETH_INT_RXE 0x00000008 /* Receive Error IRQ */ -#define OETH_INT_BUSY 0x00000010 /* Busy IRQ */ -#define OETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */ -#define OETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */ - -/* Interrupt Mask Register */ -#define OETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */ -#define OETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */ -#define OETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */ -#define OETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */ -#define OETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */ -#define OETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */ -#define OETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */ - -/* Control Module Mode Register */ -#define OETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */ -#define OETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */ -#define OETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */ - -/* MII Mode Register */ -#define OETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */ -#define OETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */ -#define OETH_MIIMODER_RST 0x00000200 /* MIIM Reset */ - -/* MII Command Register */ -#define OETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */ -#define OETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */ -#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */ - -/* MII Address Register */ -#define OETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */ -#define OETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */ - -/* MII Status Register */ -#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */ -#define OETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */ -#define OETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */ - -/* Attatch routine */ - -int rtems_open_eth_driver_attach ( - struct rtems_bsdnet_ifconfig *config, - open_eth_configuration_t *chip -); - -/* -#ifdef CPU_U32_FIX -void ipalign(struct mbuf *m); -#endif - -*/ -#endif /* _OPEN_ETH_ */ diff --git a/c/src/libchip/network/smc91111.h b/c/src/libchip/network/smc91111.h deleted file mode 100644 index 7ec83716d0..0000000000 --- a/c/src/libchip/network/smc91111.h +++ /dev/null @@ -1,558 +0,0 @@ -#ifndef _SMC91111_H_ -#define _SMC91111_H_ - -#include <libchip/smc91111exp.h> -#include <rtems/bspIo.h> - -#define LAN91CXX_TCR 0x00 -#define LAN91CXX_EPH_STATUS 0x01 -#define LAN91CXX_RCR 0x02 -#define LAN91CXX_COUNTER 0x03 -#define LAN91CXX_MIR 0x04 -#define LAN91CXX_MCR 0x05 /* Other than 91C111*/ -#define LAN91CXX_RPCR 0x05 /* 91C111 only*/ -#define LAN91CXX_RESERVED_0 0x06 -#define LAN91CXX_BS 0x07 -#define LAN91CXX_CONFIG 0x08 -#define LAN91CXX_BASE_REG 0x09 -#define LAN91CXX_IA01 0x0a -#define LAN91CXX_IA23 0x0b -#define LAN91CXX_IA45 0x0c -#define LAN91CXX_GENERAL 0x0d /* 91C96 - was "RESERVED_1" for others*/ -#define LAN91CXX_CONTROL 0x0e -#define LAN91CXX_BS2 0x0f -#define LAN91CXX_MMU_COMMAND 0x10 -#define LAN91CXX_PNR 0x11 -#define LAN91CXX_FIFO_PORTS 0x12 -#define LAN91CXX_POINTER 0x13 -#define LAN91CXX_DATA_HIGH 0x14 -#define LAN91CXX_DATA 0x15 -#define LAN91CXX_INTERRUPT 0x16 -#define LAN91CXX_BS3 0x17 -#define LAN91CXX_MT01 0x18 -#define LAN91CXX_MT23 0x19 -#define LAN91CXX_MT45 0x1a -#define LAN91CXX_MT67 0x1b -#define LAN91CXX_MGMT 0x1c -#define LAN91CXX_REVISION 0x1d -#define LAN91CXX_ERCV 0x1e -#define LAN91CXX_BS4 0x1f - -#define LAN91CXX_RCR_SOFT_RST 0x8000 /* soft reset*/ -#define LAN91CXX_RCR_FILT_CAR 0x4000 /* filter carrier*/ -#define LAN91CXX_RCR_ABORT_ENB 0x2000 /* abort on collision*/ -#define LAN91CXX_RCR_STRIP_CRC 0x0200 /* strip CRC*/ -#define LAN91CXX_RCR_RXEN 0x0100 /* enable RX*/ -#define LAN91CXX_RCR_ALMUL 0x0004 /* receive all muticasts*/ -#define LAN91CXX_RCR_PRMS 0x0002 /* promiscuous*/ -#define LAN91CXX_RCR_RX_ABORT 0x0001 /* set when abort due to long frame*/ - -#define LAN91CXX_TCR_SWFDUP 0x8000 /* Switched Full Duplex mode*/ -#define LAN91CXX_TCR_ETEN_TYPE 0x4000 /* ETEN type (91C96) 0 <=> like a 91C94*/ -#define LAN91CXX_TCR_EPH_LOOP 0x2000 /* loopback mode*/ -#define LAN91CXX_TCR_STP_SQET 0x1000 /* Stop transmission on SQET error*/ -#define LAN91CXX_TCR_FDUPLX 0x0800 /* full duplex*/ -#define LAN91CXX_TCR_MON_CSN 0x0400 /* monitor carrier during tx (91C96)*/ -#define LAN91CXX_TCR_NOCRC 0x0100 /* does not append CRC to frames*/ -#define LAN91CXX_TCR_PAD_EN 0x0080 /* pads frames with 00 to min length*/ -#define LAN91CXX_TCR_FORCOL 0x0004 /* force collision*/ -#define LAN91CXX_TCR_LLOOP 0x0002 /* local loopback (91C96)*/ -#define LAN91CXX_TCR_TXENA 0x0001 /* enable*/ - -#define LAN91CXX_POINTER_RCV 0x8000 -#define LAN91CXX_POINTER_AUTO_INCR 0x4000 -#define LAN91CXX_POINTER_READ 0x2000 -#define LAN91CXX_POINTER_ETEN 0x1000 -#define LAN91CXX_POINTER_NOT_EMPTY 0x0800 - - -#define LAN91CXX_INTERRUPT_TX_IDLE_M 0x8000 /* (91C96)*/ -#define LAN91CXX_INTERRUPT_ERCV_INT_M 0x4000 -#define LAN91CXX_INTERRUPT_EPH_INT_M 0x2000 -#define LAN91CXX_INTERRUPT_RX_OVRN_INT_M 0x1000 -#define LAN91CXX_INTERRUPT_ALLOC_INT_M 0x0800 -#define LAN91CXX_INTERRUPT_TX_EMPTY_INT_M 0x0400 -#define LAN91CXX_INTERRUPT_TX_INT_M 0x0200 -#define LAN91CXX_INTERRUPT_RCV_INT_M 0x0100 -#define LAN91CXX_INTERRUPT_TX_IDLE 0x0080 /* (91C96)*/ -#define LAN91CXX_INTERRUPT_ERCV_INT 0x0040 /* also ack*/ -#define LAN91CXX_INTERRUPT_EPH_INT 0x0020 -#define LAN91CXX_INTERRUPT_RX_OVRN_INT 0x0010 /* also ack*/ -#define LAN91CXX_INTERRUPT_ALLOC_INT 0x0008 -#define LAN91CXX_INTERRUPT_TX_EMPTY_INT 0x0004 /* also ack*/ -#define LAN91CXX_INTERRUPT_TX_INT 0x0002 /* also ack*/ -#define LAN91CXX_INTERRUPT_RCV_INT 0x0001 - -#define LAN91CXX_INTERRUPT_TX_SET 0x0006 /* TX_EMPTY + TX*/ -#define LAN91CXX_INTERRUPT_TX_SET_ACK 0x0004 /* TX_EMPTY and not plain TX*/ -#define LAN91CXX_INTERRUPT_TX_FIFO_ACK 0x0002 /* TX alone*/ -#define LAN91CXX_INTERRUPT_TX_SET_M 0x0600 /* TX_EMPTY + TX*/ - -#define LAN91CXX_CONTROL_RCV_BAD 0x4000 -#define LAN91CXX_CONTROL_AUTO_RELEASE 0x0800 -#define LAN91CXX_CONTROL_LE_ENABLE 0x0080 -#define LAN91CXX_CONTROL_CR_ENABLE 0x0040 -#define LAN91CXX_CONTROL_TE_ENABLE 0x0020 - -/* These are for setting the MAC address in the 91C96 serial EEPROM*/ -#define LAN91CXX_CONTROL_EEPROM_SELECT 0x0004 -#define LAN91CXX_CONTROL_RELOAD 0x0002 -#define LAN91CXX_CONTROL_STORE 0x0001 -#define LAN91CXX_CONTROL_EEPROM_BUSY 0x0003 -#define LAN91CXX_ESA_EEPROM_OFFSET 0x0020 - -#define LAN91CXX_STATUS_TX_UNRN 0x8000 -#define LAN91CXX_STATUS_LINK_OK 0x4000 -#define LAN91CXX_STATUS_CTR_ROL 0x1000 -#define LAN91CXX_STATUS_EXC_DEF 0x0800 -#define LAN91CXX_STATUS_LOST_CARR 0x0400 -#define LAN91CXX_STATUS_LATCOL 0x0200 -#define LAN91CXX_STATUS_WAKEUP 0x0100 -#define LAN91CXX_STATUS_TX_DEFR 0x0080 -#define LAN91CXX_STATUS_LTX_BRD 0x0040 -#define LAN91CXX_STATUS_SQET 0x0020 -#define LAN91CXX_STATUS_16COL 0x0010 -#define LAN91CXX_STATUS_LTX_MULT 0x0008 -#define LAN91CXX_STATUS_MUL_COL 0x0004 -#define LAN91CXX_STATUS_SNGL_COL 0x0002 -#define LAN91CXX_STATUS_TX_SUC 0x0001 - -#define LAN91CXX_MMU_COMMAND_BUSY 0x0001 - -#define LAN91CXX_MMU_noop 0x0000 -#define LAN91CXX_MMU_alloc_for_tx 0x0020 -#define LAN91CXX_MMU_reset_mmu 0x0040 -#define LAN91CXX_MMU_rem_rx_frame 0x0060 -#define LAN91CXX_MMU_rem_tx_frame 0x0070 /* (91C96) only when TX stopped*/ -#define LAN91CXX_MMU_remrel_rx_frame 0x0080 -#define LAN91CXX_MMU_rel_packet 0x00a0 -#define LAN91CXX_MMU_enq_packet 0x00c0 -#define LAN91CXX_MMU_reset_tx_fifo 0x00e0 - -#define LAN91CXX_CONTROLBYTE_CRC 0x1000 -#define LAN91CXX_CONTROLBYTE_ODD 0x2000 -#define LAN91CXX_CONTROLBYTE_RX 0x4000 - -#define LAN91CXX_RX_STATUS_ALIGNERR 0x8000 -#define LAN91CXX_RX_STATUS_BCAST 0x4000 -#define LAN91CXX_RX_STATUS_BADCRC 0x2000 -#define LAN91CXX_RX_STATUS_ODDFRM 0x1000 -#define LAN91CXX_RX_STATUS_TOOLONG 0x0800 -#define LAN91CXX_RX_STATUS_TOOSHORT 0x0400 -#define LAN91CXX_RX_STATUS_HASHVALMASK 0x007e /* MASK*/ -#define LAN91CXX_RX_STATUS_MCAST 0x0001 -#define LAN91CXX_RX_STATUS_BAD \ - (LAN91CXX_RX_STATUS_ALIGNERR | \ - LAN91CXX_RX_STATUS_BADCRC | \ - LAN91CXX_RX_STATUS_TOOLONG | \ - LAN91CXX_RX_STATUS_TOOSHORT) - -#define LAN91CXX_RX_STATUS_IS_ODD(__cpd,__stat) ((__stat) & LAN91CXX_RX_STATUS_ODDFRM) -#define LAN91CXX_CONTROLBYTE_IS_ODD(__cpd,__val) ((__val) & LAN91CXX_CONTROLBYTE_ODD) - -/* Attribute memory registers in PCMCIA mode*/ -#define LAN91CXX_ECOR 0x8000 -#define LAN91CXX_ECOR_RESET (1<<7) -#define LAN91CXX_ECOR_LEVIRQ (1<<6) -#define LAN91CXX_ECOR_ATTWR (1<<2) -#define LAN91CXX_ECOR_ENABLE (1<<0) - -#define LAN91CXX_ECSR 0x8002 -#define LAN91CXX_ECSR_IOIS8 (1<<5) -#define LAN91CXX_ECSR_PWRDWN (1<<2) -#define LAN91CXX_ECSR_INTR (1<<1) - -/* These are for manipulating the MII interface*/ -#define LAN91CXX_MGMT_MDO 0x0001 -#define LAN91CXX_MGMT_MDI 0x0002 -#define LAN91CXX_MGMT_MCLK 0x0004 -#define LAN91CXX_MGMT_MDOE 0x0008 - -/* Internal PHY registers (91c111)*/ -#define LAN91CXX_PHY_CTRL 0 -#define LAN91CXX_PHY_STAT 1 -#define LAN91CXX_PHY_ID1 2 -#define LAN91CXX_PHY_ID2 3 -#define LAN91CXX_PHY_AUTO_AD 4 -#define LAN91CXX_PHY_AUTO_CAP 5 -#define LAN91CXX_PHY_CONFIG1 16 -#define LAN91CXX_PHY_CONFIG2 17 -#define LAN91CXX_PHY_STATUS_OUT 18 -#define LAN91CXX_PHY_MASK 19 - -/* PHY control bits*/ -#define LAN91CXX_PHY_CTRL_COLTST (1 << 7) -#define LAN91CXX_PHY_CTRL_DPLX (1 << 8) -#define LAN91CXX_PHY_CTRL_ANEG_RST (1 << 9) -#define LAN91CXX_PHY_CTRL_MII_DIS (1 << 10) -#define LAN91CXX_PHY_CTRL_PDN (1 << 11) -#define LAN91CXX_PHY_CTRL_ANEG_EN (1 << 12) -#define LAN91CXX_PHY_CTRL_SPEED (1 << 13) -#define LAN91CXX_PHY_CTRL_LPBK (1 << 14) -#define LAN91CXX_PHY_CTRL_RST (1 << 15) - -/* PHY Configuration Register 1 */ -#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ -#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ -#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ -#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ -#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ -#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ -#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ -#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ -#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ -#define PHY_CFG1_TLVL_MASK 0x003C -#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ - -/* PHY Configuration Register 2 */ -#define PHY_CFG2_REG 0x11 -#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ -#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ -#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ -#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ - -/* PHY Status Output (and Interrupt status) Register */ -#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ -#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ -#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ -#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ -#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ -#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ -#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ -#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ -#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ -#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ -#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ - -/* PHY Interrupt/Status Mask Register */ -#define PHY_MASK_REG 0x13 /* Interrupt Mask */ - -#define LAN91CXX_RPCR_LEDA_LINK (0 << 2) -#define LAN91CXX_RPCR_LEDA_TXRX (4 << 2) -#define LAN91CXX_RPCR_LEDA_RX (6 << 2) -#define LAN91CXX_RPCR_LEDA_TX (7 << 2) -#define LAN91CXX_RPCR_LEDB_LINK (0 << 5) -#define LAN91CXX_RPCR_LEDB_TXRX (4 << 5) -#define LAN91CXX_RPCR_LEDB_RX (6 << 5) -#define LAN91CXX_RPCR_LEDB_TX (7 << 5) -#define LAN91CXX_RPCR_ANEG (1 << 11) -#define LAN91CXX_RPCR_DPLX (1 << 12) -#define LAN91CXX_RPCR_SPEED (1 << 13) - -/* PHY Control Register */ -#define PHY_CNTL_REG 0x00 -#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ -#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ -#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ -#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ -#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ -#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ -#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ -#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ -#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ - -/* PHY Status Register */ -#define PHY_STAT_REG 0x01 -#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ -#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ -#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ -#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ -#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ -#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ -#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ -#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ -#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ -#define PHY_STAT_LINK 0x0004 /* 1=valid link */ -#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ -#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ -#define PHY_STAT_RESERVED 0x0780 /* Reserved bits mask. */ - -/* PHY Identifier Registers */ -#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ -#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ - -/* PHY Auto-Negotiation Advertisement Register */ -#define PHY_AD_REG 0x04 -#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ -#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ -#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ -#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ -#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ -#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ -#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ -#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ -#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ - - -static int debugflag_out = 0; - -#define dbc_printf(lvl,format, args...) do { \ - if (!debugflag_out) { \ - if (lvl & DEBUG) { \ - printk(format,##args); \ - } \ - } \ -} while(0) - -#define db64_printf(format, args...) dbc_printf(64,format,##args); -#define db16_printf(format, args...) dbc_printf(16,format,##args); -#define db9_printf(format, args...) dbc_printf(9,format,##args); -#define db4_printf(format, args...) dbc_printf(4,format,##args); -#define db2_printf(format, args...) dbc_printf(2,format,##args); -#define db1_printf(format, args...) dbc_printf(1,format,##args); -#define db_printf(format, args...) dbc_printf(0xffff,format,##args); - -#if DEBUG & 1 -#define DEBUG_FUNCTION() do { db_printf("# %s\n", __FUNCTION__); } while (0) -#else -#define DEBUG_FUNCTION() do {} while(0) -#endif - - -/* ------------------------------------------------------------------------*/ - -struct smsc_lan91cxx_stats { - unsigned int tx_good ; - unsigned int tx_max_collisions ; - unsigned int tx_late_collisions ; - unsigned int tx_underrun ; - unsigned int tx_carrier_loss ; - unsigned int tx_deferred ; - unsigned int tx_sqetesterrors ; - unsigned int tx_single_collisions; - unsigned int tx_mult_collisions ; - unsigned int tx_total_collisions ; - unsigned int rx_good ; - unsigned int rx_crc_errors ; - unsigned int rx_align_errors ; - unsigned int rx_resource_errors ; - unsigned int rx_overrun_errors ; - unsigned int rx_collisions ; - unsigned int rx_short_frames ; - unsigned int rx_too_long_frames ; - unsigned int rx_symbol_errors ; - unsigned int interrupts ; - unsigned int rx_count ; - unsigned int rx_deliver ; - unsigned int rx_resource ; - unsigned int rx_restart ; - unsigned int tx_count ; - unsigned int tx_complete ; - unsigned int tx_dropped ; -}; -#define INCR_STAT(c,n) (((c)->stats.n)++) - -struct lan91cxx_priv_data; - -typedef struct lan91cxx_priv_data { - - /* frontend */ - struct arpcom arpcom; - rtems_id rxDaemonTid; - rtems_id txDaemonTid; - - scmv91111_configuration_t config; - - /* backend */ - int rpc_cur_mode; - int autoneg_active; - int phyaddr; - unsigned int lastPhy18; - - int txbusy; /* A packet has been sent*/ - unsigned long txkey; /* Used to ack when packet sent*/ - unsigned short* base; /* Base I/O address of controller*/ - /* (as it comes out of reset)*/ - int interrupt; /* Interrupt vector used by controller*/ - unsigned char enaddr[6]; /* Controller ESA*/ - /* Function to configure the ESA - may fetch ESA from EPROM or */ - /* RedBoot config option. Use of the 'config_enaddr()' function*/ - /* is depreciated in favor of the 'provide_esa()' function and*/ - /* 'hardwired_esa' boolean*/ - void (*config_enaddr)(struct lan91cxx_priv_data* cpd); - int hardwired_esa; - int txpacket; - int rxpacket; - int within_send; - int c111_reva; /* true if this is a revA LAN91C111*/ - struct smsc_lan91cxx_stats stats; -} lan91cxx_priv_data; - -/* ------------------------------------------------------------------------*/ - -#ifdef LAN91CXX_32BIT_RX -typedef unsigned int rxd_t; -#else -typedef unsigned short rxd_t; -#endif - -typedef struct _debug_regs_pair { - int reg; char *name; struct _debug_regs_pair *bits; -} debug_regs_pair; - -static debug_regs_pair debug_regs[] = { - {LAN91CXX_TCR , "LAN91CXX_TCR" ,0}, - {LAN91CXX_EPH_STATUS , "LAN91CXX_EPH_STATUS",0}, - {LAN91CXX_RCR , "LAN91CXX_RCR" ,0}, - {LAN91CXX_COUNTER , "LAN91CXX_COUNTER" ,0}, - {LAN91CXX_MIR , "LAN91CXX_MIR" ,0}, - {LAN91CXX_MCR , "LAN91CXX_MCR" ,0}, - {LAN91CXX_RPCR , "LAN91CXX_RPCR" ,0}, - {LAN91CXX_RESERVED_0 , "LAN91CXX_RESERVED_0",0}, - {LAN91CXX_BS , "LAN91CXX_BS" ,0}, - {LAN91CXX_CONFIG , "LAN91CXX_CONFIG" ,0}, - {LAN91CXX_BASE_REG , "LAN91CXX_BASE_REG" ,0}, - {LAN91CXX_IA01 , "LAN91CXX_IA01" ,0}, - {LAN91CXX_IA23 , "LAN91CXX_IA23" ,0}, - {LAN91CXX_IA45 , "LAN91CXX_IA45" ,0}, - {LAN91CXX_GENERAL , "LAN91CXX_GENERAL" ,0}, - {LAN91CXX_CONTROL , "LAN91CXX_CONTROL" ,0}, - {LAN91CXX_BS2 , "LAN91CXX_BS2" ,0}, - {LAN91CXX_MMU_COMMAND, "LAN91CXX_MMU_COMMAND",0}, - {LAN91CXX_PNR , "LAN91CXX_PNR" ,0}, - {LAN91CXX_FIFO_PORTS , "LAN91CXX_FIFO_PORTS" ,0}, - {LAN91CXX_POINTER , "LAN91CXX_POINTER" ,0}, - {LAN91CXX_DATA_HIGH , "LAN91CXX_DATA_HIGH" ,0}, - {LAN91CXX_DATA , "LAN91CXX_DATA" ,0}, - {LAN91CXX_INTERRUPT , "LAN91CXX_INTERRUPT" ,0}, - {LAN91CXX_BS3 , "LAN91CXX_BS3" ,0}, - {LAN91CXX_MT01 , "LAN91CXX_MT01" ,0}, - {LAN91CXX_MT23 , "LAN91CXX_MT23" ,0}, - {LAN91CXX_MT45 , "LAN91CXX_MT45" ,0}, - {LAN91CXX_MT67 , "LAN91CXX_MT67" ,0}, -/*{LAN91CXX_MGMT , "LAN91CXX_MGMT" ,0}, */ - {LAN91CXX_REVISION , "LAN91CXX_REVISION" ,0}, - {LAN91CXX_ERCV , "LAN91CXX_ERCV" ,0}, - {LAN91CXX_BS4 , "LAN91CXX_BS4" ,0}, - - - - {-1,0} -}; - -static char *dbg_prefix = ""; - -#ifndef SMSC_PLATFORM_DEFINED_GET_REG -static __inline__ unsigned short -get_reg(struct lan91cxx_priv_data *cpd, int regno) -{ - unsigned short val; debug_regs_pair *dbg = debug_regs; int c; - uint32_t Irql; - - /*rtems_interrupt_disable(Irql);*/ - - HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3)); - HAL_READ_UINT16(cpd->base+((regno&0x7)), val); - val = CYG_LE16_TO_CPU(val); - - /*rtems_interrupt_enable(Irql);*/ - -#if DEBUG & 32 - while ((c = dbg->reg) != -1) { - if (c == regno) { - db_printf("%sread reg [%d:%x] -> 0x%04x (%-20s)\n", dbg_prefix, regno>>3,(regno&0x7)*2, val, dbg->name); - break; - } - dbg++; - } -#else - db2_printf("%sread reg %d:%x -> 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val); -#endif - - return val; -} -#endif /* SMSC_PLATFORM_DEFINED_GET_REG*/ - -#ifndef SMSC_PLATFORM_DEFINED_PUT_REG -static __inline__ void -put_reg(struct lan91cxx_priv_data *cpd, int regno, unsigned short val) -{ - debug_regs_pair *dbg = debug_regs; int c; - uint32_t Irql; - -#if DEBUG & 32 - while ((c = dbg->reg) != -1) { - if (c == regno) { - db_printf("%swrite reg [%d:%x] <- 0x%04x (%-20s)\n", dbg_prefix, regno>>3, (regno&0x07)*2, val, dbg->name); - break; - } - dbg++; - } -#else - db2_printf("%swrite reg %d:%x <- 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val); -#endif - - /*rtems_interrupt_disable(Irql);*/ - - HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3)); - HAL_WRITE_UINT16(cpd->base+((regno&0x7)), CYG_CPU_TO_LE16(val)); - - /*rtems_interrupt_enable(Irql);*/ - -} -#endif /* SMSC_PLATFORM_DEFINED_PUT_REG*/ - -#ifndef SMSC_PLATFORM_DEFINED_PUT_DATA -/* ------------------------------------------------------------------------*/ -/* Assumes bank2 has been selected*/ -static __inline__ void -put_data(struct lan91cxx_priv_data *cpd, unsigned short val) -{ - db2_printf("%s[wdata] <- 0x%04x\n", dbg_prefix, val); - - HAL_WRITE_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val); - -} - -/* Assumes bank2 has been selected*/ -static __inline__ void -put_data8(struct lan91cxx_priv_data *cpd, unsigned char val) -{ - db2_printf("%s[bdata] <- 0x%02x\n", dbg_prefix, val); - - HAL_WRITE_UINT8(((unsigned char *)(cpd->base+((LAN91CXX_DATA & 0x7))))+1, val); - -} - -#endif /* SMSC_PLATFORM_DEFINED_PUT_DATA*/ - -#ifndef SMSC_PLATFORM_DEFINED_GET_DATA -/* Assumes bank2 has been selected*/ -static __inline__ rxd_t -get_data(struct lan91cxx_priv_data *cpd) -{ - rxd_t val; - -#ifdef LAN91CXX_32BIT_RX - HAL_READ_UINT32(cpd->base+((LAN91CXX_DATA_HIGH & 0x7)), val); -#else - HAL_READ_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val); -#endif - - db2_printf("%s[rdata] -> 0x%08x\n", dbg_prefix, val); - return val; -} -#endif /* SMSC_PLATFORM_DEFINED_GET_DATA*/ - -/* ------------------------------------------------------------------------*/ -/* Read the bank register (this one is bank-independent)*/ -#ifndef SMSC_PLATFORM_DEFINED_GET_BANKSEL -static __inline__ unsigned short -get_banksel(struct lan91cxx_priv_data *cpd) -{ - unsigned short val; - - HAL_READ_UINT16(cpd->base+(LAN91CXX_BS), val); - val = CYG_LE16_TO_CPU(val); - db2_printf("read bank sel val 0x%04x\n", val); - return val; -} -#endif - - - - - -#endif /* _SMC_91111_H_ */ - - diff --git a/c/src/libchip/network/smc91111exp.h b/c/src/libchip/network/smc91111exp.h deleted file mode 100644 index 08e086d9e7..0000000000 --- a/c/src/libchip/network/smc91111exp.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _SMC91111_EXP_H_ -#define _SMC91111_EXP_H_ - -#include <bsp.h> - -typedef struct scmv91111_configuration { - void *baseaddr; - rtems_vector_number vector; - unsigned int pio; - unsigned int ctl_rspeed; - unsigned int ctl_rfduplx; - unsigned int ctl_autoneg; -#ifdef BSP_FEATURE_IRQ_EXTENSION - const char * info; - rtems_option options; - rtems_interrupt_handler interrupt_wrapper; - void * arg; -#endif -} scmv91111_configuration_t; - -int _rtems_smc91111_driver_attach (struct rtems_bsdnet_ifconfig *config, - scmv91111_configuration_t * scm_config); - -#endif /* _SMC_91111_EXP_H_ */ - - diff --git a/c/src/libchip/network/sonic.h b/c/src/libchip/network/sonic.h deleted file mode 100644 index fe119ff20a..0000000000 --- a/c/src/libchip/network/sonic.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * RTEMS NETWORK DRIVER FOR NATIONAL DP83932 `SONIC' - * SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER - * - * REUSABLE CHIP DRIVER CONFIGURATION - * - * References: - * - * 1) DP83932C-20/25/33 MHz SONIC(TM) Systems-Oriented Network Interface - * Controller data sheet. TL/F/10492, RRD-B30M105, National Semiconductor, - * 1995. - * - * 2) Software Driver Programmer's Guide for the DP83932 SONIC(TM), - * Application Note 746, Wesley Lee and Mike Lui, TL/F/11140, - * RRD-B30M75, National Semiconductor, March, 1991. - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _SONIC_DP83932_ -#define _SONIC_DP83932_ - - - /* - * Debug levels - * - */ - -#define SONIC_DEBUG_NONE 0x0000 -#define SONIC_DEBUG_ALL 0xFFFF -#define SONIC_DEBUG_PRINT_REGISTERS 0x0001 -#define SONIC_DEBUG_MEMORY 0x0002 -#define SONIC_DEBUG_MEMORY_ALLOCATE 0x0004 -#define SONIC_DEBUG_MEMORY_DESCRIPTORS 0x0008 -#define SONIC_DEBUG_FRAGMENTS 0x0008 -#define SONIC_DEBUG_CAM 0x0010 -#define SONIC_DEBUG_DESCRIPTORS 0x0020 -#define SONIC_DEBUG_ERRORS 0x0040 -#define SONIC_DEBUG_DUMP_TX_MBUFS 0x0080 -#define SONIC_DEBUG_DUMP_RX_MBUFS 0x0100 - -#define SONIC_DEBUG_DUMP_MBUFS \ - (SONIC_DEBUG_DUMP_TX_MBUFS|SONIC_DEBUG_DUMP_RX_MBUFS) - -#define SONIC_DEBUG (SONIC_DEBUG_NONE) -/* -#define SONIC_DEBUG (SONIC_DEBUG_ERRORS | SONIC_DEBUG_PRINT_REGISTERS |\ - SONIC_DEBUG_DESCRIPTORS) -*/ - -/* - ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_PRINT_REGISTERS|SONIC_DEBUG_DUMP_MBUFS)) - ((SONIC_DEBUG_ALL) & ~(SONIC_DEBUG_DUMP_MBUFS)) -*/ - -#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS) -extern char SONIC_Reg_name[64][6]; -#endif - - -/* - * Configuration Information - */ - -typedef void (*sonic_write_register_t)( - void *base, - uint32_t regno, - uint32_t value -); - -typedef uint32_t (*sonic_read_register_t)( - void *base, - uint32_t regno -); - -typedef struct { - void *base_address; - uint32_t vector; - uint32_t dcr_value; - uint32_t dc2_value; - uint32_t tda_count; - uint32_t rda_count; - sonic_write_register_t write_register; - sonic_read_register_t read_register; -} sonic_configuration_t; - -/* - ****************************************************************** - * * - * Device Registers * - * * - ****************************************************************** - */ -#define SONIC_REG_CR 0x00 /* Command */ -#define SONIC_REG_DCR 0x01 /* Data configuration */ -#define SONIC_REG_RCR 0x02 /* Receive control */ -#define SONIC_REG_TCR 0x03 /* Transmit control */ -#define SONIC_REG_IMR 0x04 /* Interrupt mask */ -#define SONIC_REG_ISR 0x05 /* Interrupt status */ -#define SONIC_REG_UTDA 0x06 /* Upper transmit descriptor address */ -#define SONIC_REG_CTDA 0x07 /* Current transmit descriptor address */ -#define SONIC_REG_URDA 0x0D /* Upper receive descriptor address */ -#define SONIC_REG_CRDA 0x0E /* Current receive descriptor address */ -#define SONIC_REG_EOBC 0x13 /* End of buffer word count */ -#define SONIC_REG_URRA 0x14 /* Upper receive resource */ -#define SONIC_REG_RSA 0x15 /* Resource start address */ -#define SONIC_REG_REA 0x16 /* Resource end address */ -#define SONIC_REG_RRP 0x17 /* Resouce read pointer */ -#define SONIC_REG_RWP 0x18 /* Resouce write pointer */ -#define SONIC_REG_CEP 0x21 /* CAM entry pointer */ -#define SONIC_REG_CAP2 0x22 /* CAM address port 2 */ -#define SONIC_REG_CAP1 0x23 /* CAM address port 1 */ -#define SONIC_REG_CAP0 0x24 /* CAM address port 0 */ -#define SONIC_REG_CE 0x25 /* CAM enable */ -#define SONIC_REG_CDP 0x26 /* CAM descriptor pointer */ -#define SONIC_REG_CDC 0x27 /* CAM descriptor count */ -#define SONIC_REG_SR 0x28 /* Silicon revision */ -#define SONIC_REG_WT0 0x29 /* Watchdog timer 0 */ -#define SONIC_REG_WT1 0x2A /* Watchdog timer 1 */ -#define SONIC_REG_RSC 0x2B /* Receive sequence counter */ -#define SONIC_REG_CRCT 0x2C /* CRC error tally */ -#define SONIC_REG_FAET 0x2D /* FAE tally */ -#define SONIC_REG_MPT 0x2E /* Missed packet tally */ -#define SONIC_REG_MDT 0x2F /* TX Maximum Deferral */ -#define SONIC_REG_DCR2 0x3F /* Data configuration 2 */ - -/* - * Command register - */ -#define CR_LCAM 0x0200 -#define CR_RRRA 0x0100 -#define CR_RST 0x0080 -#define CR_ST 0x0020 -#define CR_STP 0x0010 -#define CR_RXEN 0x0008 -#define CR_RXDIS 0x0004 -#define CR_TXP 0x0002 -#define CR_HTX 0x0001 - -/* - * Data configuration register - */ -#define DCR_EXBUS 0x8000 -#define DCR_LBR 0x2000 -#define DCR_PO1 0x1000 -#define DCR_PO0 0x0800 -#define DCR_SBUS 0x0400 -#define DCR_USR1 0x0200 -#define DCR_USR0 0x0100 -#define DCR_WC1 0x0080 -#define DCR_WC0 0x0040 -#define DCR_DW 0x0020 -#define DCR_BMS 0x0010 -#define DCR_RFT1 0x0008 -#define DCR_RFT0 0x0004 -#define DCR_TFT1 0x0002 -#define DCR_TFT0 0x0001 - -/* data configuration register aliases */ -#define DCR_SYNC DCR_SBUS /* synchronous (memory cycle 2 clocks) */ -#define DCR_ASYNC 0 /* asynchronous (memory cycle 3 clocks) */ - -#define DCR_WAIT0 0 /* 0 wait states added */ -#define DCR_WAIT1 DCR_WC0 /* 1 wait state added */ -#define DCR_WAIT2 DCR_WC1 /* 2 wait states added */ -#define DCR_WAIT3 (DCR_WC1|DCR_WC0) /* 3 wait states added */ - -#define DCR_DW16 0 /* use 16-bit DMA accesses */ -#define DCR_DW32 DCR_DW /* use 32-bit DMA accesses */ - -#define DCR_DMAEF 0 /* DMA until TX/RX FIFO has emptied/filled */ -#define DCR_DMABLOCK DCR_BMS /* DMA until RX/TX threshold crossed */ - -#define DCR_RFT4 0 /* receive threshold 4 bytes */ -#define DCR_RFT8 DCR_RFT0 /* receive threshold 8 bytes */ -#define DCR_RFT16 DCR_RFT1 /* receive threshold 16 bytes */ -#define DCR_RFT24 (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */ - -#define DCR_TFT8 0 /* transmit threshold 8 bytes */ -#define DCR_TFT16 DCR_TFT0 /* transmit threshold 16 bytes */ -#define DCR_TFT24 DCR_TFT1 /* transmit threshold 24 bytes */ -#define DCR_TFT28 (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */ - -/* - * Receive control register - */ -#define RCR_ERR 0x8000 -#define RCR_RNT 0x4000 -#define RCR_BRD 0x2000 -#define RCR_PRO 0x1000 -#define RCR_AMC 0x0800 -#define RCR_LB1 0x0400 -#define RCR_LB0 0x0200 -#define RCR_MC 0x0100 -#define RCR_BC 0x0080 -#define RCR_LPKT 0x0040 -#define RCR_CRS 0x0020 -#define RCR_COL 0x0010 -#define RCR_CRCR 0x0008 -#define RCR_FAER 0x0004 -#define RCR_LBK 0x0002 -#define RCR_PRX 0x0001 - -/* - * Transmit control register - */ -#define TCR_PINT 0x8000 -#define TCR_POWC 0x4000 -#define TCR_CRCI 0x2000 -#define TCR_EXDIS 0x1000 -#define TCR_EXD 0x0400 -#define TCR_DEF 0x0200 -#define TCR_NCRS 0x0100 -#define TCR_CRSL 0x0080 -#define TCR_EXC 0x0040 -#define TCR_OWC 0x0020 -#define TCR_PMB 0x0008 -#define TCR_FU 0x0004 -#define TCR_BCM 0x0002 -#define TCR_PTX 0x0001 - -/* - * Interrupt mask register - */ -#define IMR_BREN 0x4000 -#define IMR_HBLEN 0x2000 -#define IMR_LCDEN 0x1000 -#define IMR_PINTEN 0x0800 -#define IMR_PRXEN 0x0400 -#define IMR_PTXEN 0x0200 -#define IMR_TXEREN 0x0100 -#define IMR_TCEN 0x0080 -#define IMR_RDEEN 0x0040 -#define IMR_RBEEN 0x0020 -#define IMR_RBAEEN 0x0010 -#define IMR_CRCEN 0x0008 -#define IMR_FAEEN 0x0004 -#define IMR_MPEN 0x0002 -#define IMR_RFOEN 0x0001 - -/* - * Interrupt status register - */ -#define ISR_BR 0x4000 -#define ISR_HBL 0x2000 -#define ISR_LCD 0x1000 -#define ISR_PINT 0x0800 -#define ISR_PKTRX 0x0400 -#define ISR_TXDN 0x0200 -#define ISR_TXER 0x0100 -#define ISR_TC 0x0080 -#define ISR_RDE 0x0040 -#define ISR_RBE 0x0020 -#define ISR_RBAE 0x0010 -#define ISR_CRC 0x0008 -#define ISR_FAE 0x0004 -#define ISR_MP 0x0002 -#define ISR_RFO 0x0001 - -/* - * Data configuration register 2 - */ -#define DCR2_EXPO3 0x8000 -#define DCR2_EXPO2 0x4000 -#define DCR2_EXPO1 0x2000 -#define DCR2_EXPO0 0x1000 -#define DCR2_HBDIS 0x0800 -#define DCR2_PH 0x0010 -#define DCR2_PCM 0x0004 -#define DCR2_PCNM 0x0002 -#define DCR2_RJCM 0x0001 - -/* - * Known values for the Silicon Revision Register. - * Note that DP83934 has revision 5 and seems to work. - */ - -#define SONIC_REVISION_B 4 -#define SONIC_REVISION_DP83934 5 -#define SONIC_REVISION_C 6 - -/* - ****************************************************************** - * * - * Transmit Buffer Management * - * * - ****************************************************************** - */ - -/* - * Transmit descriptor area entry. - * There is one transmit descriptor for each packet to be transmitted. - * Statically reserve space for up to MAXIMUM_FRAGS_PER_PACKET fragments - * per descriptor. - */ -#define MAXIMUM_FRAGS_PER_DESCRIPTOR 6 -struct TransmitDescriptor { - uint32_t status; - uint32_t pkt_config; - uint32_t pkt_size; - uint32_t frag_count; - - /* - * Packet fragment pointers - */ - struct TransmitDescriptorFragLink { - uint32_t frag_lsw; /* LSW of fragment address */ -#define frag_link frag_lsw - uint32_t frag_msw; /* MSW of fragment address */ - uint32_t frag_size; - } frag[MAXIMUM_FRAGS_PER_DESCRIPTOR]; - - /* - * Space for link if all fragment pointers are used. - */ - uint32_t link_pad; - - /* - * Extra RTEMS stuff - */ - struct TransmitDescriptor *next; /* Circularly-linked list */ - struct mbuf *mbufp; /* First mbuf in packet */ - volatile uint32_t *linkp; /* Pointer to un[xxx].link */ -}; -typedef struct TransmitDescriptor TransmitDescriptor_t; -typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t; - -/* - * Transmit Configuration. - * For standard Ethernet transmission, all bits in the transmit - * configuration field are set to 0. - */ -#define TDA_CONFIG_PINT 0x8000 -#define TDA_CONFIG_POWC 0x4000 -#define TDA_CONFIG_CRCI 0x2000 -#define TDA_CONFIG_EXDIS 0x1000 - -/* - * Transmit status - */ -#define TDA_STATUS_COLLISION_MASK 0xF800 -#define TDA_STATUS_COLLISION_SHIFT 11 -#define TDA_STATUS_EXD 0x0400 -#define TDA_STATUS_DEF 0x0200 -#define TDA_STATUS_NCRS 0x0100 -#define TDA_STATUS_CRSL 0x0080 -#define TDA_STATUS_EXC 0x0040 -#define TDA_STATUS_OWC 0x0020 -#define TDA_STATUS_PMB 0x0008 -#define TDA_STATUS_FU 0x0004 -#define TDA_STATUS_BCM 0x0002 -#define TDA_STATUS_PTX 0x0001 - -#define TDA_LINK_EOL 0x0001 -#define TDA_LINK_EOL_MASK 0xFFFE - - - -/* - ****************************************************************** - * * - * Receive Buffer Management * - * * - ****************************************************************** - */ - -/* - * Receive resource area entry. - * There is one receive resource entry for each receive buffer area (RBA). - * This driver allows only one packet per receive buffer area, so one - * receive resource entry corresponds to one correctly-received packet. - */ -struct ReceiveResource { - uint32_t buff_ptr_lsw; /* LSW of RBA address */ - uint32_t buff_ptr_msw; /* MSW of RBA address */ - uint32_t buff_wc_lsw; /* LSW of RBA size (16-bit words) */ - uint32_t buff_wc_msw; /* MSW of RBA size (16-bit words) */ -}; -typedef struct ReceiveResource ReceiveResource_t; -typedef volatile ReceiveResource_t *ReceiveResourcePointer_t; - -/* - * Receive descriptor area entry. - * There is one receive descriptor for each packet received. - */ -struct ReceiveDescriptor { - uint32_t status; - uint32_t byte_count; - uint32_t pkt_lsw; /* LSW of packet address */ - uint32_t pkt_msw; /* MSW of packet address */ - uint32_t seq_no; - uint32_t link; - uint32_t in_use; - - /* - * Extra RTEMS stuff - */ - volatile struct ReceiveDescriptor *next; /* Circularly-linked list */ - struct mbuf *mbufp; /* First mbuf in packet */ -}; -typedef struct ReceiveDescriptor ReceiveDescriptor_t; -typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t; - -typedef struct { - uint32_t cep; /* CAM Entry Pointer */ - uint32_t cap0; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */ - uint32_t cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */ - uint32_t cap2; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */ - uint32_t ce; -} CamDescriptor_t; - -typedef volatile CamDescriptor_t *CamDescriptorPointer_t; - -/* - * Receive status - */ -#define RDA_STATUS_ERR 0x8800 -#define RDA_STATUS_RNT 0x4000 -#define RDA_STATUS_BRD 0x2000 -#define RDA_STATUS_PRO 0x1000 -#define RDA_STATUS_AMC 0x0800 -#define RDA_STATUS_LB1 0x0400 -#define RDA_STATUS_LB0 0x0200 -#define RDA_STATUS_MC 0x0100 -#define RDA_STATUS_BC 0x0080 -#define RDA_STATUS_LPKT 0x0040 -#define RDA_STATUS_CRS 0x0020 -#define RDA_STATUS_COL 0x0010 -#define RDA_STATUS_CRCR 0x0008 -#define RDA_STATUS_FAER 0x0004 -#define RDA_STATUS_LBK 0x0002 -#define RDA_STATUS_PRX 0x0001 - -#define RDA_LINK_EOL 0x0001 -#define RDA_LINK_EOL_MASK 0xFFFE -#define RDA_IN_USE 0x0000 /* SONIC has finished with the packet */ - /* and the driver can process it */ -#define RDA_FREE 0xFFFF /* SONIC can use it */ - -/* - * Attach routine - */ - -int rtems_sonic_driver_attach ( - struct rtems_bsdnet_ifconfig *config, - sonic_configuration_t *chip -); - -#ifdef CPU_U32_FIX -void ipalign(struct mbuf *m); -#endif - -#endif /* _SONIC_DP83932_ */ diff --git a/c/src/libchip/network/wd80x3.h b/c/src/libchip/network/wd80x3.h deleted file mode 100644 index b4aa12e735..0000000000 --- a/c/src/libchip/network/wd80x3.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - * @file - * - * @ingroup i386_pc386 - * - * @brief DP8390 Ethernet controller definitions. - */ - -/* - * Information about the DP8390 Ethernet controller. - */ - -#ifndef __BSP_WD80x3_h -#define __BSP_WD80x3_h - -/* Register descriptions */ -/* Controller DP8390. */ - -#define DATAPORT 0x10 /* Port Window. */ -#define RESET 0x1f /* Issue a read for reset */ -#define W83CREG 0x00 /* I/O port definition */ -#define ADDROM 0x08 - -/* page 0 read or read/write registers */ - -#define CMDR 0x00+RO -#define CLDA0 0x01+RO /* current local dma addr 0 for read */ -#define CLDA1 0x02+RO /* current local dma addr 1 for read */ -#define BNRY 0x03+RO /* boundary reg for rd and wr */ -#define TSR 0x04+RO /* tx status reg for rd */ -#define NCR 0x05+RO /* number of collision reg for rd */ -#define FIFO 0x06+RO /* FIFO for rd */ -#define ISR 0x07+RO /* interrupt status reg for rd and wr */ -#define CRDA0 0x08+RO /* current remote dma address 0 for rd */ -#define CRDA1 0x09+RO /* current remote dma address 1 for rd */ -#define RSR 0x0C+RO /* rx status reg for rd */ -#define CNTR0 0x0D+RO /* tally cnt 0 for frm alg err for rd */ -#define CNTR1 RO+0x0E /* tally cnt 1 for crc err for rd */ -#define CNTR2 0x0F+RO /* tally cnt 2 for missed pkt for rd */ - -/* page 0 write registers */ - -#define PSTART 0x01+RO /* page start register */ -#define PSTOP 0x02+RO /* page stop register */ -#define TPSR 0x04+RO /* tx start page start reg */ -#define TBCR0 0x05+RO /* tx byte count 0 reg */ -#define TBCR1 0x06+RO /* tx byte count 1 reg */ -#define RSAR0 0x08+RO /* remote start address reg 0 */ -#define RSAR1 0x09+RO /* remote start address reg 1 */ -#define RBCR0 0x0A+RO /* remote byte count reg 0 */ -#define RBCR1 0x0B+RO /* remote byte count reg 1 */ -#define RCR 0x0C+RO /* rx configuration reg */ -#define TCR 0x0D+RO /* tx configuration reg */ -#define DCR RO+0x0E /* data configuration reg */ -#define IMR 0x0F+RO /* interrupt mask reg */ - -/* page 1 registers */ - -#define PAR 0x01+RO /* physical addr reg base for rd and wr */ -#define CURR 0x07+RO /* current page reg for rd and wr */ -#define MAR 0x08+RO /* multicast addr reg base fro rd and WR */ -#define MARsize 8 /* size of multicast addr space */ - -/*-----W83CREG command bits-----*/ -#define MSK_RESET 0x80 /* W83CREG masks */ -#define MSK_ENASH 0x40 -#define MSK_DECOD 0x3F /* memory decode bits, corresponding */ - /* to SA 18-13. SA 19 assumed to be 1 */ - -/*-----CMDR command bits-----*/ -#define MSK_STP 0x01 /* stop the chip */ -#define MSK_STA 0x02 /* start the chip */ -#define MSK_TXP 0x04 /* initial txing of a frm */ -#define MSK_RRE 0x08 /* remote read */ -#define MSK_RWR 0x10 /* remote write */ -#define MSK_RD2 0x20 /* no DMA used */ -#define MSK_PG0 0x00 /* select register page 0 */ -#define MSK_PG1 0x40 /* select register page 1 */ -#define MSK_PG2 0x80 /* select register page 2 */ - -/*-----ISR and TSR status bits-----*/ -#define MSK_PRX 0x01 /* rx with no error */ -#define MSK_PTX 0x02 /* tx with no error */ -#define MSK_RXE 0x04 /* rx with error */ -#define MSK_TXE 0x08 /* tx with error */ -#define MSK_OVW 0x10 /* overwrite warning */ -#define MSK_CNT 0x20 /* MSB of one of the tally counters is set */ -#define MSK_RDC 0x40 /* remote dma completed */ -#define MSK_RST 0x80 /* reset state indicator */ - -/*-----DCR command bits-----*/ -#define MSK_WTS 0x01 /* word transfer mode selection */ -#define MSK_BOS 0x02 /* byte order selection */ -#define MSK_LAS 0x04 /* long addr selection */ -#define MSK_BMS 0x08 /* burst mode selection */ -#define MSK_ARM 0x10 /* autoinitialize remote */ -#define MSK_FT00 0x00 /* burst lrngth selection */ -#define MSK_FT01 0x20 /* burst lrngth selection */ -#define MSK_FT10 0x40 /* burst lrngth selection */ -#define MSK_FT11 0x60 /* burst lrngth selection */ - -/*-----RCR command bits-----*/ -#define MSK_SEP 0x01 /* save error pkts */ -#define MSK_AR 0x02 /* accept runt pkt */ -#define MSK_AB 0x04 /* 8390 RCR */ -#define MSK_AM 0x08 /* accept multicast */ -#define MSK_PRO 0x10 /* accept all pkt with physical adr */ -#define MSK_MON 0x20 /* monitor mode */ - -/*-----TCR command bits-----*/ -#define MSK_CRC 0x01 /* inhibit CRC, do not append crc */ -#define MSK_LOOP 0x02 /* set loopback mode */ -#define MSK_BCST 0x04 /* Accept broadcasts */ -#define MSK_LB01 0x06 /* encoded loopback control */ -#define MSK_ATD 0x08 /* auto tx disable */ -#define MSK_OFST 0x10 /* collision offset enable */ - -/*-----receive status bits-----*/ -#define SMK_PRX 0x01 /* rx without error */ -#define SMK_CRC 0x02 /* CRC error */ -#define SMK_FAE 0x04 /* frame alignment error */ -#define SMK_FO 0x08 /* FIFO overrun */ -#define SMK_MPA 0x10 /* missed pkt */ -#define SMK_PHY 0x20 /* physical/multicase address */ -#define SMK_DIS 0x40 /* receiver disable. set in monitor mode */ -#define SMK_DEF 0x80 /* deferring */ - -/*-----transmit status bits-----*/ -#define SMK_PTX 0x01 /* tx without error */ -#define SMK_DFR 0x02 /* non deferred tx */ -#define SMK_COL 0x04 /* tx collided */ -#define SMK_ABT 0x08 /* tx abort because of excessive collisions */ -#define SMK_CRS 0x10 /* carrier sense lost */ -#define SMK_FU 0x20 /* FIFO underrun */ -#define SMK_CDH 0x40 /* collision detect heartbeat */ -#define SMK_OWC 0x80 /* out of window collision */ - -#endif -/* end of include */ |