diff options
Diffstat (limited to 'c/src/libchip/network/smc91111.h')
| -rw-r--r-- | c/src/libchip/network/smc91111.h | 144 |
1 files changed, 72 insertions, 72 deletions
diff --git a/c/src/libchip/network/smc91111.h b/c/src/libchip/network/smc91111.h index 0201acd3d6..7cf047e42c 100644 --- a/c/src/libchip/network/smc91111.h +++ b/c/src/libchip/network/smc91111.h @@ -195,41 +195,41 @@ #define LAN91CXX_PHY_CTRL_LPBK (1 << 14) #define LAN91CXX_PHY_CTRL_RST (1 << 15) -// PHY Configuration Register 1 -#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled -#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled -#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down -#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler -#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable -#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled -#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) -#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db -#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust +/* PHY Configuration Register 1 */ +#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ +#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ +#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ +#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ +#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ +#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ +#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ +#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ +#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ #define PHY_CFG1_TLVL_MASK 0x003C -#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time +#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ -// PHY Configuration Register 2 +/* PHY Configuration Register 2 */ #define PHY_CFG2_REG 0x11 -#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled -#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled -#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) -#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo - -// PHY Status Output (and Interrupt status) Register -#define PHY_INT_REG 0x12 // Status Output (Interrupt Status) -#define PHY_INT_INT 0x8000 // 1=bits have changed since last read -#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected -#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync -#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx -#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx -#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx -#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected -#define PHY_INT_JAB 0x0100 // 1=Jabber detected -#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode -#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex - -// PHY Interrupt/Status Mask Register -#define PHY_MASK_REG 0x13 // Interrupt Mask +#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ +#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ +#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ +#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ + +/* PHY Status Output (and Interrupt status) Register */ +#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ +#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ +#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ +#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ +#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ +#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ +#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ +#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ +#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ +#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ +#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ + +/* PHY Interrupt/Status Mask Register */ +#define PHY_MASK_REG 0x13 /* Interrupt Mask */ #define LAN91CXX_RPCR_LEDA_LINK (0 << 2) #define LAN91CXX_RPCR_LEDA_TXRX (4 << 2) @@ -243,49 +243,49 @@ #define LAN91CXX_RPCR_DPLX (1 << 12) #define LAN91CXX_RPCR_SPEED (1 << 13) -// PHY Control Register +/* PHY Control Register */ #define PHY_CNTL_REG 0x00 -#define PHY_CNTL_RST 0x8000 // 1=PHY Reset -#define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback -#define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs -#define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation -#define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode -#define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled -#define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate -#define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex -#define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test - -// PHY Status Register +#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ +#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ +#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ +#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ +#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ +#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ +#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ +#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ +#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ + +/* PHY Status Register */ #define PHY_STAT_REG 0x01 -#define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable -#define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable -#define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable -#define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable -#define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable -#define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble -#define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed -#define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected -#define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable -#define PHY_STAT_LINK 0x0004 // 1=valid link -#define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition -#define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented -#define PHY_STAT_RESERVED 0x0780 // Reserved bits mask. - -// PHY Identifier Registers -#define PHY_ID1_REG 0x02 // PHY Identifier 1 -#define PHY_ID2_REG 0x03 // PHY Identifier 2 - -// PHY Auto-Negotiation Advertisement Register +#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ +#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ +#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ +#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ +#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ +#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ +#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ +#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ +#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ +#define PHY_STAT_LINK 0x0004 /* 1=valid link */ +#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ +#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ +#define PHY_STAT_RESERVED 0x0780 /* Reserved bits mask. */ + +/* PHY Identifier Registers */ +#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ +#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ + +/* PHY Auto-Negotiation Advertisement Register */ #define PHY_AD_REG 0x04 -#define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page -#define PHY_AD_ACK 0x4000 // 1=got link code word from remote -#define PHY_AD_RF 0x2000 // 1=advertise remote fault -#define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4 -#define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX -#define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX -#define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX -#define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX -#define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA +#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ +#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ +#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ +#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ +#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ +#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ +#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ +#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ +#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ static int debugflag_out = 0; |