diff options
Diffstat (limited to 'c/src/libchip/network/dwmac-regs.h')
| -rw-r--r-- | c/src/libchip/network/dwmac-regs.h | 515 |
1 files changed, 515 insertions, 0 deletions
diff --git a/c/src/libchip/network/dwmac-regs.h b/c/src/libchip/network/dwmac-regs.h new file mode 100644 index 0000000000..53d7486750 --- /dev/null +++ b/c/src/libchip/network/dwmac-regs.h @@ -0,0 +1,515 @@ +#ifndef MAC_REGS_H +#define MAC_REGS_H + +#include <bsp/utility.h> + +typedef struct { + uint32_t high; +#define MAC_HIGH_ADDRHI(val) BSP_FLD32(val, 0, 15) +#define MAC_HIGH_ADDRHI_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define MAC_HIGH_ADDRHI_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) +#define MAC_HIGH_MBC0 BSP_BIT32(24) +#define MAC_HIGH_MBC1 BSP_BIT32(25) +#define MAC_HIGH_MBC2 BSP_BIT32(26) +#define MAC_HIGH_MBC3 BSP_BIT32(27) +#define MAC_HIGH_MBC4 BSP_BIT32(28) +#define MAC_HIGH_MBC5 BSP_BIT32(29) +#define MAC_HIGH_SA BSP_BIT32(30) +#define MAC_HIGH_AE BSP_BIT32(31) + uint32_t low; +#define MAC_LOW_ADDRLO(val) BSP_FLD32(val, 0, 32) +#define MAC_LOW_ADDRLO_GET(reg) BSP_FLD32GET(reg, 0, 32) +#define MAC_LOW_ADDRLO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 32) +} mac; + +typedef struct { + uint32_t mac_configuration; +#define MACGRP_MAC_CONFIGURATION_PRELEN(val) BSP_FLD32(val, 0, 1) +#define MACGRP_MAC_CONFIGURATION_PRELEN_GET(reg) BSP_FLD32GET(reg, 0, 1) +#define MACGRP_MAC_CONFIGURATION_PRELEN_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) +#define MACGRP_MAC_CONFIGURATION_RE BSP_BIT32(2) +#define MACGRP_MAC_CONFIGURATION_TE BSP_BIT32(3) +#define MACGRP_MAC_CONFIGURATION_DC BSP_BIT32(4) +#define MACGRP_MAC_CONFIGURATION_BL(val) BSP_FLD32(val, 5, 6) +#define MACGRP_MAC_CONFIGURATION_BL_GET(reg) BSP_FLD32GET(reg, 5, 6) +#define MACGRP_MAC_CONFIGURATION_BL_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6) +#define MACGRP_MAC_CONFIGURATION_ACS BSP_BIT32(7) +#define MACGRP_MAC_CONFIGURATION_LUD BSP_BIT32(8) +#define MACGRP_MAC_CONFIGURATION_DR BSP_BIT32(9) +#define MACGRP_MAC_CONFIGURATION_IPC BSP_BIT32(10) +#define MACGRP_MAC_CONFIGURATION_DM BSP_BIT32(11) +#define MACGRP_MAC_CONFIGURATION_LM BSP_BIT32(12) +#define MACGRP_MAC_CONFIGURATION_DO BSP_BIT32(13) +#define MACGRP_MAC_CONFIGURATION_FES BSP_BIT32(14) +#define MACGRP_MAC_CONFIGURATION_PS BSP_BIT32(15) +#define MACGRP_MAC_CONFIGURATION_DCRS BSP_BIT32(16) +#define MACGRP_MAC_CONFIGURATION_IFG(val) BSP_FLD32(val, 17, 19) +#define MACGRP_MAC_CONFIGURATION_IFG_GET(reg) BSP_FLD32GET(reg, 17, 19) +#define MACGRP_MAC_CONFIGURATION_IFG_SET(reg, val) BSP_FLD32SET(reg, val, 17, 19) +#define MACGRP_MAC_CONFIGURATION_JE BSP_BIT32(20) +#define MACGRP_MAC_CONFIGURATION_BE BSP_BIT32(21) +#define MACGRP_MAC_CONFIGURATION_JD BSP_BIT32(22) +#define MACGRP_MAC_CONFIGURATION_WD BSP_BIT32(23) +#define MACGRP_MAC_CONFIGURATION_TC BSP_BIT32(24) +#define MACGRP_MAC_CONFIGURATION_CST BSP_BIT32(25) +#define MACGRP_MAC_CONFIGURATION_TWOKPE BSP_BIT32(27) + uint32_t mac_frame_filter; +#define MACGRP_MAC_FRAME_FILTER_PR BSP_BIT32(0) +#define MACGRP_MAC_FRAME_FILTER_HUC BSP_BIT32(1) +#define MACGRP_MAC_FRAME_FILTER_HMC BSP_BIT32(2) +#define MACGRP_MAC_FRAME_FILTER_DAIF BSP_BIT32(3) +#define MACGRP_MAC_FRAME_FILTER_PM BSP_BIT32(4) +#define MACGRP_MAC_FRAME_FILTER_DBF BSP_BIT32(5) +#define MACGRP_MAC_FRAME_FILTER_PCF(val) BSP_FLD32(val, 6, 7) +#define MACGRP_MAC_FRAME_FILTER_PCF_GET(reg) BSP_FLD32GET(reg, 6, 7) +#define MACGRP_MAC_FRAME_FILTER_PCF_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7) +#define MACGRP_MAC_FRAME_FILTER_SAIF BSP_BIT32(8) +#define MACGRP_MAC_FRAME_FILTER_SAF BSP_BIT32(9) +#define MACGRP_MAC_FRAME_FILTER_HPF BSP_BIT32(10) +#define MACGRP_MAC_FRAME_FILTER_VTFE BSP_BIT32(16) +#define MACGRP_MAC_FRAME_FILTER_IPFE BSP_BIT32(20) +#define MACGRP_MAC_FRAME_FILTER_DNTU BSP_BIT32(21) +#define MACGRP_MAC_FRAME_FILTER_RA BSP_BIT32(31) + uint32_t reserved_08[2]; + uint32_t gmii_address; +#define MACGRP_GMII_ADDRESS_GMII_BUSY BSP_BIT32(0) +#define MACGRP_GMII_ADDRESS_GMII_WRITE BSP_BIT32(1) +#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE(val) BSP_FLD32(val, 2, 5) +#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_GET(reg) BSP_FLD32GET(reg, 2, 5) +#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_SET(reg, val) BSP_FLD32SET(reg, val, 2, 5) +#define MACGRP_GMII_ADDRESS_GMII_REGISTER(val) BSP_FLD32(val, 6, 10) +#define MACGRP_GMII_ADDRESS_GMII_REGISTER_GET(reg) BSP_FLD32GET(reg, 6, 10) +#define MACGRP_GMII_ADDRESS_GMII_REGISTER_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10) +#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS(val) BSP_FLD32(val, 11, 15) +#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_GET(reg) BSP_FLD32GET(reg, 11, 15) +#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15) + uint32_t gmii_data; +#define MACGRP_GMII_DATA_GMII_DATA(val) BSP_FLD32(val, 0, 15) +#define MACGRP_GMII_DATA_GMII_DATA_GET(reg) BSP_FLD32GET(reg, 0, 15) +#define MACGRP_GMII_DATA_GMII_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) + uint32_t reserved_18[9]; + uint32_t interrupt_mask; +#define MACGRP_INTERRUPT_MASK_RGSMIIIM BSP_BIT32(0) +#define MACGRP_INTERRUPT_MASK_PCSLCHGIM BSP_BIT32(1) +#define MACGRP_INTERRUPT_MASK_PCSANCIM BSP_BIT32(2) +#define MACGRP_INTERRUPT_MASK_TSIM BSP_BIT32(9) +#define MACGRP_INTERRUPT_MASK_LPIIM BSP_BIT32(10) + mac mac_addr0_15[16]; + uint32_t reserved_c0[16]; + uint32_t mmc_control; +#define MACGRP_MMC_CONTROL_CNTRST BSP_BIT32(0) +#define MACGRP_MMC_CONTROL_CNTSTOPRO BSP_BIT32(1) +#define MACGRP_MMC_CONTROL_RSTONRD BSP_BIT32(2) +#define MACGRP_MMC_CONTROL_CNTFREEZ BSP_BIT32(3) +#define MACGRP_MMC_CONTROL_CNTPRST BSP_BIT32(4) +#define MACGRP_MMC_CONTROL_CNTPRSTLVL BSP_BIT32(5) +#define MACGRP_MMC_CONTROL_UCDBC BSP_BIT32(8) + uint32_t mmc_receive_interrupt; +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBFRMIS BSP_BIT32(0) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBOCTIS BSP_BIT32(1) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGOCTIS BSP_BIT32(2) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXBCGFIS BSP_BIT32(3) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXMCGFIS BSP_BIT32(4) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXCRCERFIS BSP_BIT32(5) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXALGNERFIS BSP_BIT32(6) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXRUNTFIS BSP_BIT32(7) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXJABERFIS BSP_BIT32(8) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS BSP_BIT32(9) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS BSP_BIT32(10) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS BSP_BIT32(11) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS BSP_BIT32(12) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS BSP_BIT32(13) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS BSP_BIT32(14) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS BSP_BIT32(15) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS BSP_BIT32(16) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXUCGFIS BSP_BIT32(17) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXLENERFIS BSP_BIT32(18) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXORANGEFIS BSP_BIT32(19) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXPAUSFIS BSP_BIT32(20) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXFOVFIS BSP_BIT32(21) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS BSP_BIT32(22) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXWDOGFIS BSP_BIT32(23) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS BSP_BIT32(24) +#define MACGRP_MMC_RECEIVE_INTERRUPT_RXCTRLFIS BSP_BIT32(25) + uint32_t mmc_transmit_interrupt; +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS BSP_BIT32(0) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS BSP_BIT32(1) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGFIS BSP_BIT32(2) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGFIS BSP_BIT32(3) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS BSP_BIT32(4) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS BSP_BIT32(5) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS BSP_BIT32(6) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS BSP_BIT32(7) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS BSP_BIT32(8) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS BSP_BIT32(9) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS BSP_BIT32(10) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS BSP_BIT32(11) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS BSP_BIT32(12) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS BSP_BIT32(13) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS BSP_BIT32(14) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS BSP_BIT32(15) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXDEFFIS BSP_BIT32(16) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS BSP_BIT32(17) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS BSP_BIT32(18) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXCARERFIS BSP_BIT32(19) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGOCTIS BSP_BIT32(20) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGFRMIS BSP_BIT32(21) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS BSP_BIT32(22) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS BSP_BIT32(23) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS BSP_BIT32(24) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS BSP_BIT32(25) + uint32_t mmc_receive_interrupt_mask; +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM BSP_BIT32(0) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM BSP_BIT32(1) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM BSP_BIT32(2) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM BSP_BIT32(3) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM BSP_BIT32(4) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM BSP_BIT32(5) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM BSP_BIT32(6) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM BSP_BIT32(7) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM BSP_BIT32(8) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM BSP_BIT32(9) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM BSP_BIT32(10) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM BSP_BIT32(11) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM BSP_BIT32(12) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM BSP_BIT32(13) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM BSP_BIT32(14) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM BSP_BIT32(15) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM BSP_BIT32(16) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM BSP_BIT32(17) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM BSP_BIT32(18) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM BSP_BIT32(19) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM BSP_BIT32(20) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM BSP_BIT32(21) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM BSP_BIT32(22) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM BSP_BIT32(23) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM BSP_BIT32(24) +#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM BSP_BIT32(25) + uint32_t mmc_transmit_interrupt_mask; +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM BSP_BIT32(0) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM BSP_BIT32(1) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM BSP_BIT32(2) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM BSP_BIT32(3) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM BSP_BIT32(4) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM BSP_BIT32(5) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM BSP_BIT32(6) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM BSP_BIT32(7) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM BSP_BIT32(8) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM BSP_BIT32(9) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM BSP_BIT32(10) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM BSP_BIT32(11) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM BSP_BIT32(12) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM BSP_BIT32(13) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM BSP_BIT32(14) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM BSP_BIT32(15) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM BSP_BIT32(16) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM BSP_BIT32(17) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM BSP_BIT32(18) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM BSP_BIT32(19) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM BSP_BIT32(20) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM BSP_BIT32(21) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM BSP_BIT32(22) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM BSP_BIT32(23) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM BSP_BIT32(24) +#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM BSP_BIT32(25) + uint32_t txoctetcount_gb; + uint32_t txframecount_gb; + uint32_t txbroadcastframes_g; + uint32_t txmulticastframes_g; + uint32_t tx64octets_gb; + uint32_t tx65to127octets_gb; + uint32_t tx128to255octets_gb; + uint32_t tx256to511octets_gb; + uint32_t tx512to1023octets_gb; + uint32_t tx1024tomaxoctets_gb; + uint32_t txunicastframes_gb; + uint32_t txmulticastframes_gb; + uint32_t txbroadcastframes_gb; + uint32_t txunderflowerror; + uint32_t txsinglecol_g; + uint32_t txmulticol_g; + uint32_t txdeferred; + uint32_t txlatecol; + uint32_t txexesscol; + uint32_t txcarriererr; + uint32_t txoctetcnt; + uint32_t txframecount_g; + uint32_t txexcessdef; + uint32_t txpauseframes; + uint32_t txvlanframes_g; + uint32_t txoversize_g; + uint32_t reserved_17c; + uint32_t rxframecount_gb; + uint32_t rxoctetcount_gb; + uint32_t rxoctetcount_g; + uint32_t rxbroadcastframes_g; + uint32_t rxmulticastframes_g; + uint32_t rxcrcerror; + uint32_t rxalignmenterror; + uint32_t rxrunterror; + uint32_t rxjabbererror; + uint32_t rxundersize_g; + uint32_t rxoversize_g; + uint32_t rx64octets_gb; + uint32_t rx65to127octets_gb; + uint32_t rx128to255octets_gb; + uint32_t rx256to511octets_gb; + uint32_t rx512to1023octets_gb; + uint32_t rx1024tomaxoctets_gb; + uint32_t rxunicastframes_g; + uint32_t rxlengtherror; + uint32_t rxoutofrangetype; + uint32_t rxpauseframes; + uint32_t rxfifooverflow; + uint32_t rxvlanframes_gb; + uint32_t rxwatchdogerror; + uint32_t rxrcverror; + uint32_t rxctrlframes_g; + uint32_t reserved_1e8[6]; + uint32_t mmc_ipc_receive_interrupt_mask; +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM BSP_BIT32(0) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM BSP_BIT32(1) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM BSP_BIT32(2) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM BSP_BIT32(3) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM BSP_BIT32(4) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM BSP_BIT32(5) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM BSP_BIT32(6) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM BSP_BIT32(7) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM BSP_BIT32(8) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM BSP_BIT32(9) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM BSP_BIT32(10) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM BSP_BIT32(11) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM BSP_BIT32(12) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM BSP_BIT32(13) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM BSP_BIT32(16) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM BSP_BIT32(17) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM BSP_BIT32(18) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM BSP_BIT32(19) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM BSP_BIT32(20) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM BSP_BIT32(21) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM BSP_BIT32(22) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM BSP_BIT32(23) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM BSP_BIT32(24) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM BSP_BIT32(25) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM BSP_BIT32(26) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM BSP_BIT32(27) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM BSP_BIT32(28) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM BSP_BIT32(29) + uint32_t reserved_204; + uint32_t mmc_ipc_receive_interrupt; +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS BSP_BIT32(0) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS BSP_BIT32(1) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS BSP_BIT32(2) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS BSP_BIT32(3) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS BSP_BIT32(4) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS BSP_BIT32(5) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS BSP_BIT32(6) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS BSP_BIT32(7) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS BSP_BIT32(8) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS BSP_BIT32(9) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS BSP_BIT32(10) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS BSP_BIT32(11) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS BSP_BIT32(12) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS BSP_BIT32(13) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS BSP_BIT32(16) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS BSP_BIT32(17) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS BSP_BIT32(18) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS BSP_BIT32(19) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS BSP_BIT32(20) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS BSP_BIT32(21) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS BSP_BIT32(22) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS BSP_BIT32(23) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS BSP_BIT32(24) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS BSP_BIT32(25) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS BSP_BIT32(26) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS BSP_BIT32(27) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS BSP_BIT32(28) +#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS BSP_BIT32(29) + uint32_t reserved_20c; + uint32_t rxipv4_gd_frms; + uint32_t rxipv4_hdrerr_frms; + uint32_t rxipv4_nopay_frms; + uint32_t rxipv4_frag_frms; + uint32_t rxipv4_udsbl_frms; + uint32_t rxipv6_gd_frms; + uint32_t rxipv6_hdrerr_frms; + uint32_t rxipv6_nopay_frms; + uint32_t rxudp_gd_frms; + uint32_t rxudp_err_frms; + uint32_t rxtcp_gd_frms; + uint32_t rxtcp_err_frms; + uint32_t rxicmp_gd_frms; + uint32_t rxicmp_err_frms; + uint32_t reserved_248[2]; + uint32_t rxipv4_gd_octets; + uint32_t rxipv4_hdrerr_octets; + uint32_t rxipv4_nopay_octets; + uint32_t rxipv4_frag_octets; + uint32_t rxipv4_udsbl_octets; + uint32_t rxipv6_gd_octets; + uint32_t rxipv6_hdrerr_octets; + uint32_t rxipv6_nopay_octets; + uint32_t rxudp_gd_octets; + uint32_t rxudp_err_octets; + uint32_t rxtcp_gd_octets; + uint32_t rxtcperroctets; + uint32_t rxicmp_gd_octets; + uint32_t rxicmp_err_octets; + uint32_t reserved_288[158]; + uint32_t hash_table_reg[8]; + uint32_t reserved_520[184]; + mac mac_addr16_127[112]; +} macgrp; + +typedef struct { + uint32_t bus_mode; +#define DMAGRP_BUS_MODE_SWR BSP_BIT32(0) +#define DMAGRP_BUS_MODE_DSL(val) BSP_FLD32(val, 2, 6) +#define DMAGRP_BUS_MODE_DSL_GET(reg) BSP_FLD32GET(reg, 2, 6) +#define DMAGRP_BUS_MODE_DSL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 6) +#define DMAGRP_BUS_MODE_ATDS BSP_BIT32(7) +#define DMAGRP_BUS_MODE_PBL(val) BSP_FLD32(val, 8, 13) +#define DMAGRP_BUS_MODE_PBL_GET(reg) BSP_FLD32GET(reg, 8, 13) +#define DMAGRP_BUS_MODE_PBL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) +#define DMAGRP_BUS_MODE_FB BSP_BIT32(16) +#define DMAGRP_BUS_MODE_RPBL(val) BSP_FLD32(val, 17, 22) +#define DMAGRP_BUS_MODE_RPBL_GET(reg) BSP_FLD32GET(reg, 17, 22) +#define DMAGRP_BUS_MODE_RPBL_SET(reg, val) BSP_FLD32SET(reg, val, 17, 22) +#define DMAGRP_BUS_MODE_USP BSP_BIT32(23) +#define DMAGRP_BUS_MODE_EIGHTXPBL BSP_BIT32(24) +#define DMAGRP_BUS_MODE_AAL BSP_BIT32(25) +#define DMAGRP_BUS_MODE_MB BSP_BIT32(26) + uint32_t transmit_poll_demand; +#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD(val) BSP_FLD32(val, 0, 31) +#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_GET(reg) BSP_FLD32GET(reg, 0, 31) +#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31) + uint32_t receive_poll_demand; +#define DMAGRP_RECEIVE_POLL_DEMAND_RPD(val) BSP_FLD32(val, 0, 31) +#define DMAGRP_RECEIVE_POLL_DEMAND_RPD_GET(reg) BSP_FLD32GET(reg, 0, 31) +#define DMAGRP_RECEIVE_POLL_DEMAND_RPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31) + uint32_t receive_descr_list_addr; +#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT(val) BSP_FLD32(val, 2, 31) +#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_GET(reg) BSP_FLD32GET(reg, 2, 31) +#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_SET(reg, val) BSP_FLD32SET(reg, val, 2, 31) + uint32_t transmit_descr_list_addr; +#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT(val) BSP_FLD32(val, 2, 31) +#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_GET(reg) BSP_FLD32GET(reg, 2, 31) +#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_SET(reg, val) BSP_FLD32SET(reg, val, 2, 31) + uint32_t status; +#define DMAGRP_STATUS_TI BSP_BIT32(0) +#define DMAGRP_STATUS_TPS BSP_BIT32(1) +#define DMAGRP_STATUS_TU BSP_BIT32(2) +#define DMAGRP_STATUS_TJT BSP_BIT32(3) +#define DMAGRP_STATUS_OVF BSP_BIT32(4) +#define DMAGRP_STATUS_UNF BSP_BIT32(5) +#define DMAGRP_STATUS_RI BSP_BIT32(6) +#define DMAGRP_STATUS_RU BSP_BIT32(7) +#define DMAGRP_STATUS_RPS BSP_BIT32(8) +#define DMAGRP_STATUS_RWT BSP_BIT32(9) +#define DMAGRP_STATUS_ETI BSP_BIT32(10) +#define DMAGRP_STATUS_FBI BSP_BIT32(13) +#define DMAGRP_STATUS_ERI BSP_BIT32(14) +#define DMAGRP_STATUS_AIS BSP_BIT32(15) +#define DMAGRP_STATUS_NIS BSP_BIT32(16) +#define DMAGRP_STATUS_RS(val) BSP_FLD32(val, 17, 19) +#define DMAGRP_STATUS_RS_GET(reg) BSP_FLD32GET(reg, 17, 19) +#define DMAGRP_STATUS_RS_SET(reg, val) BSP_FLD32SET(reg, val, 17, 19) +#define DMAGRP_STATUS_TS(val) BSP_FLD32(val, 20, 22) +#define DMAGRP_STATUS_TS_GET(reg) BSP_FLD32GET(reg, 20, 22) +#define DMAGRP_STATUS_TS_SET(reg, val) BSP_FLD32SET(reg, val, 20, 22) +#define DMAGRP_STATUS_EB(val) BSP_FLD32(val, 23, 25) +#define DMAGRP_STATUS_EB_GET(reg) BSP_FLD32GET(reg, 23, 25) +#define DMAGRP_STATUS_EB_SET(reg, val) BSP_FLD32SET(reg, val, 23, 25) +#define DMAGRP_STATUS_GLI BSP_BIT32(26) +#define DMAGRP_STATUS_GMI BSP_BIT32(27) +#define DMAGRP_STATUS_TTI BSP_BIT32(29) +#define DMAGRP_STATUS_GLPII BSP_BIT32(30) + uint32_t operation_mode; +#define DMAGRP_OPERATION_MODE_SR BSP_BIT32(1) +#define DMAGRP_OPERATION_MODE_OSF BSP_BIT32(2) +#define DMAGRP_OPERATION_MODE_RTC(val) BSP_FLD32(val, 3, 4) +#define DMAGRP_OPERATION_MODE_RTC_GET(reg) BSP_FLD32GET(reg, 3, 4) +#define DMAGRP_OPERATION_MODE_RTC_SET(reg, val) BSP_FLD32SET(reg, val, 3, 4) +#define DMAGRP_OPERATION_MODE_FUF BSP_BIT32(6) +#define DMAGRP_OPERATION_MODE_FEF BSP_BIT32(7) +#define DMAGRP_OPERATION_MODE_EFC BSP_BIT32(8) +#define DMAGRP_OPERATION_MODE_RFA(val) BSP_FLD32(val, 9, 10) +#define DMAGRP_OPERATION_MODE_RFA_GET(reg) BSP_FLD32GET(reg, 9, 10) +#define DMAGRP_OPERATION_MODE_RFA_SET(reg, val) BSP_FLD32SET(reg, val, 9, 10) +#define DMAGRP_OPERATION_MODE_RFD(val) BSP_FLD32(val, 11, 12) +#define DMAGRP_OPERATION_MODE_RFD_GET(reg) BSP_FLD32GET(reg, 11, 12) +#define DMAGRP_OPERATION_MODE_RFD_SET(reg, val) BSP_FLD32SET(reg, val, 11, 12) +#define DMAGRP_OPERATION_MODE_ST BSP_BIT32(13) +#define DMAGRP_OPERATION_MODE_TTC(val) BSP_FLD32(val, 14, 16) +#define DMAGRP_OPERATION_MODE_TTC_GET(reg) BSP_FLD32GET(reg, 14, 16) +#define DMAGRP_OPERATION_MODE_TTC_SET(reg, val) BSP_FLD32SET(reg, val, 14, 16) +#define DMAGRP_OPERATION_MODE_FTF BSP_BIT32(20) +#define DMAGRP_OPERATION_MODE_TSF BSP_BIT32(21) +#define DMAGRP_OPERATION_MODE_DFF BSP_BIT32(24) +#define DMAGRP_OPERATION_MODE_RSF BSP_BIT32(25) +#define DMAGRP_OPERATION_MODE_DT BSP_BIT32(26) + uint32_t interrupt_enable; +#define DMAGRP_INTERRUPT_ENABLE_TIE BSP_BIT32(0) +#define DMAGRP_INTERRUPT_ENABLE_TSE BSP_BIT32(1) +#define DMAGRP_INTERRUPT_ENABLE_TUE BSP_BIT32(2) +#define DMAGRP_INTERRUPT_ENABLE_TJE BSP_BIT32(3) +#define DMAGRP_INTERRUPT_ENABLE_OVE BSP_BIT32(4) +#define DMAGRP_INTERRUPT_ENABLE_UNE BSP_BIT32(5) +#define DMAGRP_INTERRUPT_ENABLE_RIE BSP_BIT32(6) +#define DMAGRP_INTERRUPT_ENABLE_RUE BSP_BIT32(7) +#define DMAGRP_INTERRUPT_ENABLE_RSE BSP_BIT32(8) +#define DMAGRP_INTERRUPT_ENABLE_RWE BSP_BIT32(9) +#define DMAGRP_INTERRUPT_ENABLE_ETE BSP_BIT32(10) +#define DMAGRP_INTERRUPT_ENABLE_FBE BSP_BIT32(13) +#define DMAGRP_INTERRUPT_ENABLE_ERE BSP_BIT32(14) +#define DMAGRP_INTERRUPT_ENABLE_AIE BSP_BIT32(15) +#define DMAGRP_INTERRUPT_ENABLE_NIE BSP_BIT32(16) + uint32_t reserved_20[2]; + uint32_t axi_bus_mode; +#define DMAGRP_AXI_BUS_MODE_UNDEFINED BSP_BIT32(0) +#define DMAGRP_AXI_BUS_MODE_BLEND4 BSP_BIT32(1) +#define DMAGRP_AXI_BUS_MODE_BLEND8 BSP_BIT32(2) +#define DMAGRP_AXI_BUS_MODE_BLEND16 BSP_BIT32(3) +#define DMAGRP_AXI_BUS_MODE_AXI_AAL BSP_BIT32(12) +#define DMAGRP_AXI_BUS_MODE_ONEKBBE BSP_BIT32(13) +#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT(val) BSP_FLD32(val, 16, 19) +#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_GET(reg) BSP_FLD32GET(reg, 16, 19) +#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) +#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT(val) BSP_FLD32(val, 20, 23) +#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_GET(reg) BSP_FLD32GET(reg, 20, 23) +#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23) +#define DMAGRP_AXI_BUS_MODE_LPI_XIT_FRM BSP_BIT32(30) +#define DMAGRP_AXI_BUS_MODE_EN_LPI BSP_BIT32(31) + uint32_t reserved_2c[11]; + uint32_t hw_feature; +#define DMAGRP_HW_FEATURE_MIISEL BSP_BIT32(0) +#define DMAGRP_HW_FEATURE_GMIISEL BSP_BIT32(1) +#define DMAGRP_HW_FEATURE_HDSEL BSP_BIT32(2) +#define DMAGRP_HW_FEATURE_HASHSEL BSP_BIT32(4) +#define DMAGRP_HW_FEATURE_ADDMACADRSEL BSP_BIT32(5) +#define DMAGRP_HW_FEATURE_PCSSEL BSP_BIT32(6) +#define DMAGRP_HW_FEATURE_SMASEL BSP_BIT32(8) +#define DMAGRP_HW_FEATURE_RWKSEL BSP_BIT32(9) +#define DMAGRP_HW_FEATURE_MGKSEL BSP_BIT32(10) +#define DMAGRP_HW_FEATURE_MMCSEL BSP_BIT32(11) +#define DMAGRP_HW_FEATURE_TSVER1SEL BSP_BIT32(12) +#define DMAGRP_HW_FEATURE_TSVER2SEL BSP_BIT32(13) +#define DMAGRP_HW_FEATURE_EEESEL BSP_BIT32(14) +#define DMAGRP_HW_FEATURE_AVSEL BSP_BIT32(15) +#define DMAGRP_HW_FEATURE_TXOESEL BSP_BIT32(16) +#define DMAGRP_HW_FEATURE_RXTYP1COE BSP_BIT32(17) +#define DMAGRP_HW_FEATURE_RXTYP2COE BSP_BIT32(18) +#define DMAGRP_HW_FEATURE_RXFIFOSIZE BSP_BIT32(19) +#define DMAGRP_HW_FEATURE_RXCHCNT(val) BSP_FLD32(val, 20, 21) +#define DMAGRP_HW_FEATURE_RXCHCNT_GET(reg) BSP_FLD32GET(reg, 20, 21) +#define DMAGRP_HW_FEATURE_RXCHCNT_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21) +#define DMAGRP_HW_FEATURE_TXCHCNT(val) BSP_FLD32(val, 22, 23) +#define DMAGRP_HW_FEATURE_TXCHCNT_GET(reg) BSP_FLD32GET(reg, 22, 23) +#define DMAGRP_HW_FEATURE_TXCHCNT_SET(reg, val) BSP_FLD32SET(reg, val, 22, 23) +#define DMAGRP_HW_FEATURE_ENHDESSEL BSP_BIT32(24) +#define DMAGRP_HW_FEATURE_ACTPHYIF(val) BSP_FLD32(val, 28, 30) +#define DMAGRP_HW_FEATURE_ACTPHYIF_GET(reg) BSP_FLD32GET(reg, 28, 30) +#define DMAGRP_HW_FEATURE_ACTPHYIF_SET(reg, val) BSP_FLD32SET(reg, val, 28, 30) +} dmagrp; + +#endif /* MAC_REGS_H */ |