diff options
Diffstat (limited to 'c/src/lib/libcpu/powerpc/shared')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h | 2 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/shared/include/io.h | 2 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/shared/include/mmu.h | 18 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h | 14 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/shared/include/spr.h | 4 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/shared/src/cache.c | 4 |
6 files changed, 22 insertions, 22 deletions
diff --git a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h index ba7000670c..95b8e05d2d 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h +++ b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h @@ -66,7 +66,7 @@ typedef enum * below. */ -typedef struct { +typedef struct { unsigned has_altivec : 1; unsigned has_fpu : 1; unsigned has_hw_ptbl_lkup : 1; diff --git a/c/src/lib/libcpu/powerpc/shared/include/io.h b/c/src/lib/libcpu/powerpc/shared/include/io.h index 1b68e069f6..3921e1855f 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/io.h +++ b/c/src/lib/libcpu/powerpc/shared/include/io.h @@ -57,7 +57,7 @@ static inline void eieio(void) } -/* Enforce in-order execution of data I/O. +/* Enforce in-order execution of data I/O. * No distinction between read/write on PPC; use eieio for all three. */ #define iobarrier_rw() eieio() diff --git a/c/src/lib/libcpu/powerpc/shared/include/mmu.h b/c/src/lib/libcpu/powerpc/shared/include/mmu.h index c230bf0fac..db3f66aca3 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/mmu.h +++ b/c/src/lib/libcpu/powerpc/shared/include/mmu.h @@ -35,7 +35,7 @@ typedef struct _PTE { unsigned long g:1; /* Guarded */ unsigned long :1; /* Unused */ unsigned long pp:2; /* Page protection */ -} PTE; +} PTE; /* Values for PP (assumes Ks=0, Kp=1) */ #define PP_RWXX 0 /* Supervisor read/write, User none */ @@ -71,7 +71,7 @@ typedef struct _BATU { /* Upper part of BAT (all except 601) */ unsigned long bl:11; /* Block size mask */ unsigned long vs:1; /* Supervisor valid */ unsigned long vp:1; /* User valid */ -} BATU; +} BATU; typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ unsigned long brpn:15; /* Real page index (physical address) */ @@ -139,7 +139,7 @@ typedef struct _pte { #define PT_SHIFT (12) /* Page Table */ #define PT_MASK 0x03FF #define PG_SHIFT (12) /* Page Entry */ - + /* MMU context */ @@ -156,13 +156,13 @@ typedef struct _MMU_context { #define HASH_TABLE_SIZE_1M 0x00100000 #define HASH_TABLE_SIZE_2M 0x00200000 #define HASH_TABLE_SIZE_4M 0x00400000 -#define HASH_TABLE_MASK_64K 0x000 -#define HASH_TABLE_MASK_128K 0x001 -#define HASH_TABLE_MASK_256K 0x003 +#define HASH_TABLE_MASK_64K 0x000 +#define HASH_TABLE_MASK_128K 0x001 +#define HASH_TABLE_MASK_256K 0x003 #define HASH_TABLE_MASK_512K 0x007 -#define HASH_TABLE_MASK_1M 0x00F -#define HASH_TABLE_MASK_2M 0x01F -#define HASH_TABLE_MASK_4M 0x03F +#define HASH_TABLE_MASK_1M 0x00F +#define HASH_TABLE_MASK_2M 0x01F +#define HASH_TABLE_MASK_4M 0x03F /* invalidate a TLB entry */ static inline void _tlbie(unsigned long va) diff --git a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h index b71db63fa6..68e16b1c52 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h +++ b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h @@ -14,7 +14,7 @@ * D-82178 Puchheim * Germany * rtems@embedded-brains.de - * + * * access function for Device Control Registers inspired by "ppc405common.h" * from Michael Hamel ADInstruments May 2008 * @@ -213,7 +213,7 @@ static inline void ppc_synchronize_instructions(void) /** * @brief Enables external exceptions. - * + * * You can use this function to enable the external exceptions and restore the * machine state with ppc_external_exceptions_disable() later. */ @@ -236,7 +236,7 @@ static inline uint32_t ppc_external_exceptions_enable(void) /** * @brief Restores machine state. - * + * * @see ppc_external_exceptions_enable() */ static inline void ppc_external_exceptions_disable(uint32_t msr) @@ -345,7 +345,7 @@ static inline void PPC_Set_timebase_register (uint64_t tbr) tbr_high = (uint32_t) (tbr >> 32); asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); - + } static inline uint32_t ppc_decrementer_register(void) @@ -606,11 +606,11 @@ void ppc_code_copy(void *dest, const void *src, size_t n); LWI \reg2, \mask and \reg1, \reg1, \reg2 cmplw \reg1, \reg2 -.endm - +.endm + .macro SETBITS reg1, reg2, mask LWI \reg2, \mask - or \reg1, \reg1, \reg2 + or \reg1, \reg1, \reg2 .endm .macro CLRBITS reg1, reg2, mask diff --git a/c/src/lib/libcpu/powerpc/shared/include/spr.h b/c/src/lib/libcpu/powerpc/shared/include/spr.h index 8a1a65c469..3501b52b74 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/spr.h +++ b/c/src/lib/libcpu/powerpc/shared/include/spr.h @@ -55,7 +55,7 @@ static inline unsigned long _read_MSR(void) unsigned long val; asm volatile("mfmsr %0" : "=r" (val)); return val; -} +} static inline void _write_MSR(unsigned long val) { @@ -68,7 +68,7 @@ static inline unsigned long _read_SR(void * va) unsigned long val; asm volatile("mfsrin %0,%1" : "=r" (val): "r" (va)); return val; -} +} static inline void _write_SR(unsigned long val, void * va) { diff --git a/c/src/lib/libcpu/powerpc/shared/src/cache.c b/c/src/lib/libcpu/powerpc/shared/src/cache.c index d998fb5016..d40e7d0f39 100644 --- a/c/src/lib/libcpu/powerpc/shared/src/cache.c +++ b/c/src/lib/libcpu/powerpc/shared/src/cache.c @@ -23,10 +23,10 @@ * They provide the basic implementation for the rtems_* cache * management routines. If a given function has no meaning for the CPU, * it does nothing by default. - * + * * FIXME: Some functions simply have not been implemented. */ - + #if defined(ppc603) || defined(ppc603e) || defined(mpc8260) /* And possibly others */ /* Helpful macros */ |