diff options
Diffstat (limited to 'c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h index 753fc14931..fc9a66647c 100644 --- a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h +++ b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h @@ -108,6 +108,7 @@ extern "C" { #define CPU_MODEL_NAME "PowerPC 405" #endif #define PPC_CACHE_ALIGNMENT 16 +#define PPC_HAS_RI 0 #define PPC_HAS_RFCI 1 #define PPC_USE_MULTIPLE 1 #define PPC_I_CACHE 2048 @@ -362,6 +363,14 @@ extern "C" { #ifndef PPC_HAS_EXCEPTION_PREFIX #define PPC_HAS_EXCEPTION_PREFIX 1 #endif +/* + * Unless otherwise specified, assume the model has an RI bit to + * identify non-recoverable interrupts + */ + +#ifndef PPC_HAS_RI +#define PPC_HAS_RI 1 +#endif /* * Unless otherwise specified, assume the model does NOT have @@ -657,15 +666,17 @@ extern "C" { * Machine Status Register (MSR) Constants Used by RTEMS */ -/* - * Some PPC model manuals refer to the Exception Prefix (EP) bit as - * IP for no apparent reason. - */ - +#if PPC_HAS_RI #define PPC_MSR_RI 0x000000002 /* bit 30 - recoverable exception */ +#endif + #define PPC_MSR_DR 0x000000010 /* bit 27 - data address translation */ #define PPC_MSR_IR 0x000000020 /* bit 26 - instruction addr translation*/ +/* + * Some PPC model manuals refer to the Exception Prefix (EP) bit as + * IP for no apparent reason. + */ #if (PPC_HAS_EXCEPTION_PREFIX) #define PPC_MSR_EP 0x000000040 /* bit 25 - exception prefix */ #else @@ -708,4 +719,4 @@ extern "C" { } #endif -#endif /* _RTEMS_SCORE_POWERPC_H */ +#endif /* _RTEMS_POWERPC_POWERPC_H */ |