diff options
Diffstat (limited to 'c/src/lib/libcpu/powerpc/mpc8xx')
-rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c | 16 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c | 88 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c | 4 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c | 12 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h | 6 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h | 8 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h | 58 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c | 44 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c | 2 |
9 files changed, 119 insertions, 119 deletions
diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c b/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c index 346e188a76..78cc703010 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c @@ -56,10 +56,10 @@ void Clock_exit( void ); /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; - + /* * ISR Handler */ @@ -104,7 +104,7 @@ void clockOn(void* unused) s_value = (plprcr_val & (0x00300000)) >> (31-11); mfi_value = (plprcr_val & (0x000f0000)) >> (31-15); pdf_value = (plprcr_val & (0x00000006)) >> (31-30); - extclk = (((uint64_t)bsp_clock_speed) + extclk = (((uint64_t)bsp_clock_speed) * ((pdf_value + 1) * (mfd_value + 1)) / (mfi_value * (mfd_value + 1) + mfn_value) * (1 << s_value)); @@ -128,7 +128,7 @@ void clockOn(void* unused) else { pit_value = (rtems_configuration_get_microseconds_per_tick() * bsp_clicks_per_usec); - + m8xx.sccr &= ~(1<<23); } if ((pit_value > 0xffff) || force_prescaler){ @@ -162,7 +162,7 @@ void clockOff(void* unused) { /* disable PIT and PIT interrupts */ - m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); + m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); } int clockIsOn(void* unused) @@ -203,13 +203,13 @@ rtems_device_driver Clock_initialize( ) { Install_clock( Clock_isr ); - + /* * make major/minor avail to others such as shared memory driver */ - + rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c index 574120bd4f..b8dff4683b 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c @@ -122,7 +122,7 @@ m8xx_get_brg_cd (int baud) } -/* +/* * This function will fail if more that 4 baud rates have been selected * at any time since the OS started. It needs to be fixed. FIXME */ @@ -181,7 +181,7 @@ static int m8xx_smc_set_attributes (int minor, const struct termios *t) { int baud, brg=0, csize=0, ssize, psize; - uint16_t clen=0, cstopb, parenb, parodd, cread; + uint16_t clen=0, cstopb, parenb, parodd, cread; /* Baud rate */ switch (t->c_cflag & CBAUD) { @@ -209,7 +209,7 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) if (baud > 0) brg = m8xx_get_brg_clk(baud); /* 4 BRGs, 6 serial ports - hopefully */ /* at least 2 ports will be the same */ - + /* Number of data bits */ switch ( t->c_cflag & CSIZE ) { case CS5: csize = 5; break; @@ -235,15 +235,15 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) parenb = 0x0000; /* No parity on Tx and Rx */ psize = 0; } - + if ( t->c_cflag & PARODD ) parodd = 0x0000; /* Odd parity */ else parodd = 0x0100; - /* + /* * Character Length = start + data + parity + stop - 1 - */ + */ switch ( 1 + csize + psize + ssize - 1 ) { case 6: clen = 0x3000; break; case 7: clen = 0x3800; break; @@ -257,7 +257,7 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) cread = 0x0023; /* UART normal operation, enable Rx and Tx */ else cread = 0x0021; /* UART normal operation, enable Tx */ - + /* Write the SIMODE/SMCMR registers */ switch (minor) { case SMC1_MINOR: @@ -306,7 +306,7 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) brg = m8xx_get_brg_clk(baud); /* 4 BRGs, 5 serial ports - hopefully */ /* at least 2 ports will be the same */ /* Write the SICR register below */ - + /* Number of data bits */ switch ( t->c_cflag & CSIZE ) { case CS5: csize = 0x0000; break; @@ -320,13 +320,13 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) cstopb = 0x4000; /* Two stop bits */ else cstopb = 0x0000; /* One stop bit */ - + /* Parity */ if ( t->c_cflag & PARENB ) parenb = 0x0010; /* Parity enabled on Tx and Rx */ else parenb = 0x0000; /* No parity on Tx and Rx */ - + if ( t->c_cflag & PARODD ) parodd = 0x0000; /* Odd parity */ else @@ -349,12 +349,12 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) break; #endif } - + return 0; } -int +int m8xx_uart_setAttributes( int minor, const struct termios *t @@ -363,7 +363,7 @@ m8xx_uart_setAttributes( /* * Check that port number is valid */ - if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) + if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) return 0; switch (minor) { @@ -396,8 +396,8 @@ static void m8xx_scc2_interrupt_handler (void *unused) /* Check that the buffer is ours */ if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC2_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC2_MINOR]->buffer, RxBd[SCC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC2_MINOR], @@ -438,8 +438,8 @@ m8xx_scc3_interrupt_handler (void *unused) /* Check that the buffer is ours */ if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC3_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC3_MINOR]->buffer, RxBd[SCC3_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC3_MINOR], @@ -479,8 +479,8 @@ m8xx_scc4_interrupt_handler (void *unused) /* Check that the buffer is ours */ if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC4_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC4_MINOR]->buffer, RxBd[SCC4_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC4_MINOR], @@ -520,8 +520,8 @@ m8xx_smc1_interrupt_handler (void *unused) /* Check that the buffer is ours */ if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SMC1_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SMC1_MINOR]->buffer, RxBd[SMC1_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SMC1_MINOR], @@ -561,8 +561,8 @@ m8xx_smc2_interrupt_handler (void *unused) /* Check that the buffer is ours */ if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SMC2_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SMC2_MINOR]->buffer, RxBd[SMC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SMC2_MINOR], @@ -641,7 +641,7 @@ int m8xx_scc_isOn(const rtems_irq_connect_data* ptr) } static rtems_irq_connect_data consoleIrqData; - + void m8xx_uart_scc_initialize (int minor) { @@ -652,7 +652,7 @@ m8xx_uart_scc_initialize (int minor) /* * Check that minor number is valid */ - if ( (minor < SCC2_MINOR) || (minor > NUM_PORTS-1) ) + if ( (minor < SCC2_MINOR) || (minor > NUM_PORTS-1) ) return; /* Get the sicr clock source bit values for 9600 bps */ @@ -694,7 +694,7 @@ m8xx_uart_scc_initialize (int minor) case SCC2_MINOR: sccparms = &m8xx.scc2p; sccregs = &m8xx.scc2; - + m8xx.papar |= 0x000C; /* PA12 & PA13 are dedicated peripheral pins */ m8xx.padir &= ~0x000C; /* PA13 & PA12 must not drive the UART lines */ m8xx.paodr &= ~0x000C; /* PA12 & PA13 are not open drain */ @@ -702,7 +702,7 @@ m8xx_uart_scc_initialize (int minor) m8xx.pcpar &= ~0x00C0; /* PC8 & PC9 are SCC2 DCD and CTS */ m8xx.pcdir &= ~0x00C2; /* PC8, PC9 & PC14 must not drive the UART lines */ m8xx.pcso |= 0x00C0; /* Enable DCD and CTS inputs */ - + m8xx.sicr &= 0xFFFF00FF; /* Clear TCS2 & RCS2, GR2=no grant, SC2=NMSI mode */ m8xx.sicr |= (brg<<11) | (brg<<8); /* TCS2 = RCS2 = brg */ break; @@ -711,12 +711,12 @@ m8xx_uart_scc_initialize (int minor) case SCC3_MINOR: sccparms = &m8xx.scc3p; sccregs = &m8xx.scc3; - + m8xx.pcpar &= ~0x0300; /* PC6 & PC7 are SCC3 DCD and CTS */ m8xx.pcdir &= ~0x0300; /* PC6 & PC7 must not drive the UART lines */ m8xx.pcso |= 0x0300; /* Enable DCD and CTS inputs */ m8xx.pdpar |= 0x0130; /* PD7, PD10 & PD11 are dedicated peripheral pins */ - + m8xx.sicr &= 0xFF00FFFF; /* Clear TCS3 & RCS3, GR3=no grant, SC3=NMSI mode */ m8xx.sicr |= (brg<<19) | (brg<<16); /* TCS3 = RCS3 = brg */ break; @@ -724,12 +724,12 @@ m8xx_uart_scc_initialize (int minor) case SCC4_MINOR: sccparms = &m8xx.scc4p; sccregs = &m8xx.scc4; - + m8xx.pcpar &= ~0x0C00; /* PC4 & PC5 are SCC4 DCD and CTS */ m8xx.pcdir &= ~0x0C00; /* PC4 & PC5 must not drive the UART lines */ m8xx.pcso |= 0x0C00; /* Enable DCD and CTS inputs */ m8xx.pdpar |= 0x02C0; /* PD6, PD8 & PD9 are dedicated peripheral pins */ - + m8xx.sicr &= 0x00FFFFFF; /* Clear TCS4 & RCS4, GR4=no grant, SC4=NMSI mode */ m8xx.sicr |= (brg<<27) | (brg<<24); /* TCS4 = RCS4 = brg */ break; @@ -822,7 +822,7 @@ m8xx_uart_scc_initialize (int minor) consoleIrqData.on = m8xx_scc_enable; consoleIrqData.off = m8xx_scc_disable; consoleIrqData.isOn = m8xx_scc_isOn; - + switch (minor) { case SCC2_MINOR: consoleIrqData.name = BSP_CPM_IRQ_SCC2; @@ -834,7 +834,7 @@ m8xx_uart_scc_initialize (int minor) consoleIrqData.name = BSP_CPM_IRQ_SCC3; consoleIrqData.hdl = m8xx_scc3_interrupt_handler; break; - + case SCC4_MINOR: consoleIrqData.name = BSP_CPM_IRQ_SCC4; consoleIrqData.hdl = m8xx_scc4_interrupt_handler; @@ -895,7 +895,7 @@ m8xx_uart_smc_initialize (int minor) /* * Check that minor number is valid */ - if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) + if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) return; m8xx.sdcr = 0x01; /* as per section 16.10.2.1 MPC821UM/AD */ @@ -922,7 +922,7 @@ m8xx_uart_smc_initialize (int minor) case SMC1_MINOR: smcparms = &m8xx.smc1p; smcregs = &m8xx.smc1; - + m8xx.pbpar |= 0x000000C0; /* PB24 & PB25 are dedicated peripheral pins */ m8xx.pbdir &= ~0x000000C0; /* PB24 & PB25 must not drive UART lines */ m8xx.pbodr &= ~0x000000C0; /* PB24 & PB25 are not open drain */ @@ -934,16 +934,16 @@ m8xx_uart_smc_initialize (int minor) case SMC2_MINOR: smcparms = &m8xx.smc2p; smcregs = &m8xx.smc2; - + m8xx.pbpar |= 0x00000C00; /* PB20 & PB21 are dedicated peripheral pins */ m8xx.pbdir &= ~0x00000C00; /* PB20 & PB21 must not drive the UART lines */ m8xx.pbodr &= ~0x00000C00; /* PB20 & PB21 are not open drain */ - + m8xx.simode &= 0x0FFFFFFF; /* Clear SMC2CS & SMC2 for NMSI mode */ m8xx.simode |= brg << 28; /* SMC2CS = brg */ break; } - + /* * Set up SMC1 parameter RAM common to all protocols */ @@ -994,7 +994,7 @@ m8xx_uart_smc_initialize (int minor) m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC2); break; } - + /* * Enable receiver and transmitter */ @@ -1008,7 +1008,7 @@ m8xx_uart_smc_initialize (int minor) consoleIrqData.name = BSP_CPM_IRQ_SMC1; consoleIrqData.hdl = m8xx_smc1_interrupt_handler; break; - + case SMC2_MINOR: consoleIrqData.name = BSP_CPM_IRQ_SMC2_OR_PIP; consoleIrqData.hdl = m8xx_smc2_interrupt_handler; @@ -1025,7 +1025,7 @@ void m8xx_uart_initialize(void) { int i; - + for (i=0; i < 4; i++) { brg_spd[i] = 0; brg_used[i] = 0; @@ -1044,7 +1044,7 @@ m8xx_uart_pollRead( if (RxBd[minor]->status & M8xx_BD_EMPTY) { return -1; } - rtems_cache_invalidate_multiple_data_lines( + rtems_cache_invalidate_multiple_data_lines( (const void *) RxBd[minor]->buffer, RxBd[minor]->length ); @@ -1057,7 +1057,7 @@ m8xx_uart_pollRead( /* * TODO: Get a free buffer and set it up. */ -int +int m8xx_uart_write( int minor, const char *buf, @@ -1070,7 +1070,7 @@ m8xx_uart_write( TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT; return 0; } - + int m8xx_uart_pollWrite( diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c index 560299f69d..de38f0a5df 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c @@ -2,7 +2,7 @@ * cp.c * * MPC8xx CPM RISC Communication Processor routines. - * + * * Based on code (alloc860.c in eth_comm port) by * Jay Monkman (jmonkman@frasca.com), * which, in turn, is based on code by @@ -23,7 +23,7 @@ void m8xx_cp_execute_cmd( uint16_t command ) { rtems_interrupt_level lvl; - + rtems_interrupt_disable(lvl); while (m8xx.cpcr & M8xx_CR_FLG) { continue; diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c index 22319c3c1b..94fcaa61c8 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c @@ -2,7 +2,7 @@ * dpram.c * * MPC8xx dual-port RAM allocation routines - * + * * Based on code (alloc860.c in eth_comm port) by * Jay Monkman (jmonkman@frasca.com), * which, in turn, is based on code by @@ -47,16 +47,16 @@ m8xx_dpram_allocate( unsigned int byte_count ) unsigned int i; ISR_Level level; void *blockp = NULL; - + byte_count = (byte_count + 3) & ~0x3; - + /* * Running with interrupts disabled is usually considered bad * form, but this routine is probably being run as part of an * initialization sequence so the effect shouldn't be too severe. */ _ISR_Disable (level); - + for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) { /* * Verify that the region is available for use. @@ -82,9 +82,9 @@ m8xx_dpram_allocate( unsigned int byte_count ) break; } } - + _ISR_Enable(level); - + if (blockp == NULL) rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count); return blockp; diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h index ddc6d19f23..f3341ed915 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h +++ b/c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h @@ -1,7 +1,7 @@ -/* +/* * cpm.h - * - * This include file contains definitions pertaining + * + * This include file contains definitions pertaining * to the Communications Processor Module (CPM) on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h index 5e4cd2536b..73e75a8904 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h +++ b/c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h @@ -1,7 +1,7 @@ -/* +/* * mmu.h - * - * This include file contains definitions pertaining + * + * This include file contains definitions pertaining * to the MMU on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada @@ -29,7 +29,7 @@ typedef struct { } MMU_TLB_table_t; /* - * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be + * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be * supplied by the BSP. */ extern MMU_TLB_table_t MMU_TLB_table[]; /* MMU TLB table supplied by BSP */ diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h b/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h index 6aa75d1269..3222e7fd03 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h +++ b/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h @@ -722,8 +722,8 @@ typedef struct m8xxBufferDescriptor_ { */ typedef struct m8xxIDMABufferDescriptor_ { uint16_t status; - uint8_t dfcr; - uint8_t sfcr; + uint8_t dfcr; + uint8_t sfcr; uint32_t length; void *source; void *destination; @@ -1116,14 +1116,14 @@ typedef struct m8xxIDMABufferDescriptor_ { * Value to write to a key register to unlock the corresponding SIU register */ #define M8xx_UNLOCK_KEY 0x55CCAA33 - + /* ************************************************************************* * MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address) * ************************************************************************* */ typedef struct m8xx_ { - + /* * SIU Block */ @@ -1144,7 +1144,7 @@ typedef struct m8xx_ { uint32_t _pad1[3]; uint32_t sdcr; uint8_t _pad2[0x80-0x34]; - + /* * PCMCIA Block */ @@ -1173,7 +1173,7 @@ typedef struct m8xx_ { uint32_t _pad5; uint32_t per; uint32_t _pad6; - + /* * MEMC Block */ @@ -1188,7 +1188,7 @@ typedef struct m8xx_ { uint16_t mptpr; uint32_t mdr; uint8_t _pad9[0x200-0x180]; - + /* * System integration timers */ @@ -1210,8 +1210,8 @@ typedef struct m8xx_ { uint16_t pitr; uint16_t _pad_14_2; uint8_t _pad15[0x280-0x24c]; - - + + /* * Clocks and Reset */ @@ -1219,8 +1219,8 @@ typedef struct m8xx_ { uint32_t plprcr; uint32_t rsr; uint8_t _pad16[0x300-0x28c]; - - + + /* * System integration timers keys */ @@ -1237,7 +1237,7 @@ typedef struct m8xx_ { uint32_t piscrk; uint32_t pitck; uint8_t _pad19[0x380-0x348]; - + /* * Clocks and Reset Keys */ @@ -1247,8 +1247,8 @@ typedef struct m8xx_ { uint8_t _pad20[0x400-0x38c]; uint8_t _pad21[0x800-0x400]; uint8_t _pad22[0x860-0x800]; - - + + /* * I2C */ @@ -1264,7 +1264,7 @@ typedef struct m8xx_ { uint8_t _pad27[3]; uint8_t i2cmr; uint8_t _pad28[0x900-0x875]; - + /* * DMA Block */ @@ -1282,7 +1282,7 @@ typedef struct m8xx_ { uint8_t _pad34[3]; uint8_t idmr2; uint8_t _pad35[0x930-0x91d]; - + /* * CPM Interrupt Control Block */ @@ -1292,7 +1292,7 @@ typedef struct m8xx_ { uint32_t cipr; uint32_t cimr; uint32_t cisr; - + /* * I/O Port Block */ @@ -1312,7 +1312,7 @@ typedef struct m8xx_ { uint16_t _pad40; uint16_t pddat; uint8_t _pad41[8]; - + /* * CPM Timers Block */ @@ -1358,7 +1358,7 @@ typedef struct m8xx_ { uint16_t _pad47; uint16_t rtmr; uint8_t _pad48[0x9f0-0x9dc]; - + /* * BRG Block */ @@ -1366,7 +1366,7 @@ typedef struct m8xx_ { uint32_t brgc2; uint32_t brgc3; uint32_t brgc4; - + /* * SCC Block */ @@ -1384,7 +1384,7 @@ typedef struct m8xx_ { */ m8xxSMCRegisters_t smc1; m8xxSMCRegisters_t smc2; - + /* * SPI Block */ @@ -1397,7 +1397,7 @@ typedef struct m8xx_ { uint8_t _pad52[2]; uint8_t spcom; uint16_t _pad53[2]; - + /* * PIP Block */ @@ -1410,7 +1410,7 @@ typedef struct m8xx_ { uint16_t pbodr; uint32_t pbdat; uint32_t _pad56[6]; - + /* * SI Block */ @@ -1434,7 +1434,7 @@ typedef struct m8xx_ { uint8_t lcdram[512]; #endif uint8_t _pad62[0x2000-0x1000]; - + /* * Dual-port RAM */ @@ -1444,11 +1444,11 @@ typedef struct m8xx_ { uint8_t dpram3[0x600]; /* BD/DATA*/ uint8_t dpram4[0x200]; /* BD/DATA/UCODE */ uint8_t _pad63[0x3c00-0x3000]; - + /* When using SCC1 for ethernet, we lose the use of I2C since * their parameters would overlap. Motorola has a microcode * patch to move parameters around so that both can be used - * together. It is available on their web site somewhere + * together. It is available on their web site somewhere * under http://www.mot.com/mpc8xx. If ethernet is used on * one (or more) of the other SCCs, then other CPM features * will be unavailable: @@ -1463,7 +1463,7 @@ typedef struct m8xx_ { uint8_t _rsv2[0xcc0-0xCB0-sizeof(m8xxMiscParms_t)]; m8xxIDMAparms_t idma1p; uint8_t _rsv3[0xd00-0xcc0-sizeof(m8xxIDMAparms_t)]; - + m8xxSCCparms_t scc2p; uint8_t _rsv4[0xD80-0xD00-sizeof(m8xxSCCparms_t)]; m8xxSPIparms_t spip; @@ -1472,14 +1472,14 @@ typedef struct m8xx_ { uint8_t _rsv6[0xDC0-0xDB0-sizeof(m8xxTimerParms_t)]; m8xxIDMAparms_t idma2p; uint8_t _rsv7[0xE00-0xDC0-sizeof(m8xxIDMAparms_t)]; - + m8xxSCCparms_t scc3p; /* Not available on MPC821 */ uint8_t _rsv8[0xE80-0xE00-sizeof(m8xxSCCparms_t)]; m8xxSMCparms_t smc1p; uint8_t _rsv9[0xEC0-0xE80-sizeof(m8xxSMCparms_t)]; m8xxDSPparms_t dsp1p; uint8_t _rsv10[0xF00-0xEC0-sizeof(m8xxDSPparms_t)]; - + m8xxSCCparms_t scc4p; /* Not available on MPC821 */ uint8_t _rsv11[0xF80-0xF00-sizeof(m8xxSCCparms_t)]; m8xxSMCparms_t smc2p; diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c b/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c index 4fa55701cd..fbf2d2eeb0 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c @@ -1,7 +1,7 @@ -/* +/* * mmu.c - * - * This file contains routines for initializing + * + * This file contains routines for initializing * and manipulating the MMU on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada @@ -20,18 +20,18 @@ /* * mmu_init * - * This routine sets up the virtual memory maps on an MPC8xx. - * The MPC8xx does not support block address translation (BATs) - * and does not have segment registers. Thus, we must set up page + * This routine sets up the virtual memory maps on an MPC8xx. + * The MPC8xx does not support block address translation (BATs) + * and does not have segment registers. Thus, we must set up page * translation. However, its MMU supports variable size pages * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task. * - * The MPC8xx has separate data and instruction 32-entry translation - * lookaside buffers (TLB). By mapping all of DRAM as one huge page, - * we can preload the TLBs and not have to be concerned with taking + * The MPC8xx has separate data and instruction 32-entry translation + * lookaside buffers (TLB). By mapping all of DRAM as one huge page, + * we can preload the TLBs and not have to be concerned with taking * TLB miss exceptions. * - * We set up the virtual memory map so that virtual address of a + * We set up the virtual memory map so that virtual address of a * location is equal to its real address. */ void mmu_init( void ) @@ -46,14 +46,14 @@ void mmu_init( void ) * We can assume the MSR has already been set this way. */ - /* + /* * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR) * GPM [0] 0b0 = PowerPC mode * PPM [1] 0b0 = Page resolution of protection - * CIDEF [2] 0b0/0b0 = Default cache-inhibit attribute = + * CIDEF [2] 0b0/0b0 = Default cache-inhibit attribute = * NO for IMMU, NO for DMMU * NOTE: it is vital that data caching is ON, when - * DMMU is off, otherwise valid/dirty values in + * DMMU is off, otherwise valid/dirty values in * cache would be ignored during exception entry * reserved/WTDEF [3] 0b0 = Default write-through attribute = not * RSV4x [4] 0b0 = 4 entries not reserved @@ -62,7 +62,7 @@ void mmu_init( void ) * reserved [7-18] 0x00 * xTLB_INDX [19-23] 31 = 0x1F * reserved [24-31] 0x00 - * + * * Note: It is important that cache-inhibit be set as the default for the * data cache when the DMMU is disabled in order to prevent internal memory * mapped registers from being cached accidentally when address translation @@ -73,15 +73,15 @@ void mmu_init( void ) reg1 = M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31); _mtspr( M8xx_MD_CTR, reg1 ); _isync; - - /* + + /* * Invalidate all TLB entries in both TLBs. * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so * all 32 entries are invalidated. */ __asm__ volatile ("tlbia\n"::); _isync; - + /* * Set Current Address Space ID Register (M_CASID). * Supervisor: CASID = 0 @@ -89,7 +89,7 @@ void mmu_init( void ) reg1 = 0; _mtspr( M8xx_M_CASID, reg1 ); - /* + /* * Initialize the MMU Access Protection Registers (MI_AP, MD_AP) * We ignore the Access Protection Group (APG) mechanism globally * by setting all of the Mx_AP fields to 0b01 : client access @@ -99,10 +99,10 @@ void mmu_init( void ) _mtspr( M8xx_MI_AP, reg1 ); _mtspr( M8xx_MD_AP, reg1 ); - /* + /* * Load both 32-entry TLBs with values from the MMU_TLB_table * which is defined in the BSP. - * Note the _TLB_Table must have at most 32 entries. This code + * Note the _TLB_Table must have at most 32 entries. This code * makes no effort to enforce this restriction. */ for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) { @@ -117,9 +117,9 @@ void mmu_init( void ) _mtspr( M8xx_MD_RPN, reg1 ); } - /* + /* * Turn on address translation by setting MSR[IR] and MSR[DR]. - */ + */ _CPU_MSR_GET( reg1 ); reg1 |= PPC_MSR_IR | PPC_MSR_DR; _CPU_MSR_SET( reg1 ); diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c index 517b2a90d8..3258d46b49 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c @@ -67,7 +67,7 @@ void benchmark_timer_initialize(void) /* set interrupt level and enable timebase. This should never */ /* generate an interrupt however. */ m8xx.tbscr |= M8xx_TBSCR_TBIRQ(4) | M8xx_TBSCR_TBE; - + Timer_starting = get_itimer(); } |