diff options
Diffstat (limited to 'c/src/lib/libcpu/powerpc/mpc8260')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c | 72 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c | 4 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c | 10 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h | 10 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h | 8 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h | 28 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c | 42 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c | 2 |
8 files changed, 88 insertions, 88 deletions
diff --git a/c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c index 167d860dcd..68d857dd2e 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c +++ b/c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c @@ -12,7 +12,7 @@ * resource minor note * SMC1 0 * SMC2 1 - * SCC1 2 + * SCC1 2 * SCC2 3 * SCC3 4 * SCC4 5 @@ -117,7 +117,7 @@ static int m8xx_smc_set_attributes (int minor, const struct termios *t) { int baud, brg=0, csize=0, ssize, psize; - uint16_t clen=0, cstopb, parenb, parodd, cread; + uint16_t clen=0, cstopb, parenb, parodd, cread; /* Baud rate */ switch (t->c_cflag & CBAUD) { @@ -152,13 +152,13 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) break; case SMC2_MINOR: /* SMC2 can only choose between BRG2 and 8 */ - brg = m8xx_get_brg( M8260_SMC2_BRGS, baud*16 ) + 1; + brg = m8xx_get_brg( M8260_SMC2_BRGS, baud*16 ) + 1; m8260.cmxsmr &= ~0x30; m8260.cmxsmr |= (brg==2? 0x00: 0x01 ); break; } } - + /* Number of data bits */ switch ( t->c_cflag & CSIZE ) { case CS5: csize = 5; break; @@ -184,15 +184,15 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) parenb = 0x0000; /* No parity on Tx and Rx */ psize = 0; } - + if ( t->c_cflag & PARODD ) parodd = 0x0000; /* Odd parity */ else parodd = 0x0100; - /* + /* * Character Length = start + data + parity + stop - 1 - */ + */ switch ( 1 + csize + psize + ssize - 1 ) { case 6: clen = 0x3000; break; case 7: clen = 0x3800; break; @@ -206,7 +206,7 @@ m8xx_smc_set_attributes (int minor, const struct termios *t) cread = 0x0023; /* UART normal operation, enable Rx and Tx */ else cread = 0x0021; /* UART normal operation, enable Tx */ - + /* Write the SIMODE/SMCMR registers */ switch (minor) { case SMC1_MINOR: @@ -257,7 +257,7 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) case B460800: baud = 460800; break; } if (baud > 0) { - brg = m8xx_get_brg( M8260_SCC_BRGS, baud*16 ); + brg = m8xx_get_brg( M8260_SCC_BRGS, baud*16 ); m8260.cmxscr &= ~(0xFF000000 >> (8*(minor-SCC1_MINOR)) ); m8260.cmxscr |= ((brg<<(3+8*(3-(minor-SCC1_MINOR)))) & (brg<<(8*(3-(minor-SCC1_MINOR))))); @@ -275,13 +275,13 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) cstopb = 0x4000; /* Two stop bits */ else cstopb = 0x0000; /* One stop bit */ - + /* Parity */ if ( t->c_cflag & PARENB ) parenb = 0x0010; /* Parity enabled on Tx and Rx */ else parenb = 0x0000; /* No parity on Tx and Rx */ - + if ( t->c_cflag & PARODD ) parodd = 0x0000; /* Odd parity */ else @@ -319,7 +319,7 @@ m8xx_scc_set_attributes (int minor, const struct termios *t) } -int +int m8xx_uart_setAttributes( int minor, const struct termios *t @@ -328,7 +328,7 @@ m8xx_uart_setAttributes( /* * Check that port number is valid */ - if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) + if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) return 0; switch (minor) { @@ -408,8 +408,8 @@ m8xx_scc2_interrupt_handler (rtems_irq_hdl_param unused) /* Check that the buffer is ours */ if ((RxBd[SCC2_MINOR]->status & M8260_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC2_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC2_MINOR]->buffer, RxBd[SCC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC2_MINOR], @@ -453,8 +453,8 @@ m8xx_scc3_interrupt_handler (rtems_irq_hdl_param unused) /* Check that the buffer is ours */ if ((RxBd[SCC3_MINOR]->status & M8260_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC3_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC3_MINOR]->buffer, RxBd[SCC3_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC3_MINOR], @@ -499,8 +499,8 @@ m8xx_scc4_interrupt_handler (rtems_irq_hdl_param unused) /* Check that the buffer is ours */ if ((RxBd[SCC4_MINOR]->status & M8260_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SCC4_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC4_MINOR]->buffer, RxBd[SCC4_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SCC4_MINOR], @@ -543,8 +543,8 @@ m8xx_smc1_interrupt_handler (rtems_irq_hdl_param unused) /* Check that the buffer is ours */ if ((RxBd[SMC1_MINOR]->status & M8260_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SMC1_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SMC1_MINOR]->buffer, RxBd[SMC1_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SMC1_MINOR], @@ -588,8 +588,8 @@ m8xx_smc2_interrupt_handler (rtems_irq_hdl_param unused) /* Check that the buffer is ours */ if ((RxBd[SMC2_MINOR]->status & M8260_BD_EMPTY) == 0) { - rtems_cache_invalidate_multiple_data_lines( - (const void *) RxBd[SMC2_MINOR]->buffer, + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SMC2_MINOR]->buffer, RxBd[SMC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( (void *)ttyp[SMC2_MINOR], @@ -693,7 +693,7 @@ m8xx_uart_scc_initialize (int minor) /* * Check that minor number is valid */ - if ( (minor < SCC1_MINOR) || (minor > NUM_PORTS-1) ) + if ( (minor < SCC1_MINOR) || (minor > NUM_PORTS-1) ) return; /* Get the sicr clock source bit values for 9600 bps */ @@ -740,7 +740,7 @@ m8xx_uart_scc_initialize (int minor) sccparms = (m8260SCCparms_t*)&m8260.scc4p; sccregs = (m8260SCCRegisters_t*)&m8260.scc4; } - + sccparms->rbase = (char *)RxBd[minor] - (char *)&m8260; sccparms->tbase = (char *)TxBd[minor] - (char *)&m8260; @@ -823,7 +823,7 @@ m8xx_uart_scc_initialize (int minor) switch (minor) { case SCC1_MINOR: consoleIrqData.name = BSP_CPM_IRQ_SCC1; - consoleIrqData.hdl = m8xx_scc1_interrupt_handler; + consoleIrqData.hdl = m8xx_scc1_interrupt_handler; break; case SCC2_MINOR: consoleIrqData.name = BSP_CPM_IRQ_SCC2; @@ -837,7 +837,7 @@ m8xx_uart_scc_initialize (int minor) consoleIrqData.name = BSP_CPM_IRQ_SCC4; consoleIrqData.hdl = m8xx_scc4_interrupt_handler; break; - + } if (!BSP_install_rtems_irq_handler (&consoleIrqData)) { printk("Unable to connect SCC Irq handler\n"); @@ -896,7 +896,7 @@ m8xx_uart_smc_initialize (int minor) /* * Check that minor number is valid */ - if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) + if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) return; /* Get the simode clock source bit values for 9600 bps */ @@ -943,13 +943,13 @@ m8xx_uart_smc_initialize (int minor) m8260.pbpar |= 0x00000C00; /* PB20 & PB21 are dedicated peripheral pins */ m8260.pbdir &= ~0x00000C00; /* PB20 & PB21 must not drive the UART lines */ m8260.pbodr &= ~0x00000C00; /* PB20 & PB21 are not open drain */ - + m8260.simode &= 0x0FFFFFFF; /* Clear SMC2CS & SMC2 for NMSI mode */ m8260.simode |= brg << 28; /* SMC2CS = brg */ #endif break; } - + /* * Set up SMC parameter RAM common to all protocols */ @@ -1000,7 +1000,7 @@ m8xx_uart_smc_initialize (int minor) m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SMC2); break; } - + /* * Enable receiver and transmitter */ @@ -1029,7 +1029,7 @@ m8xx_uart_smc_initialize (int minor) m8260.sipnr_l |= M8260_SIMASK_SMC1; /* Clear pending register */ m8260.simr_l |= M8260_SIMASK_SMC1; /* Enable SMC1 interrupts */ break; - + case SMC2_MINOR: rtems_interrupt_catch (m8xx_smc2_interrupt_handler, PPC_IRQ_CPM_SMC2, @@ -1055,7 +1055,7 @@ m8xx_uart_initialize(void) } -void +void m8xx_uart_interrupts_initialize(void) { #ifdef mpc8260 @@ -1085,7 +1085,7 @@ m8xx_uart_pollRead( if (RxBd[minor]->status & M8260_BD_EMPTY) { return -1; } - rtems_cache_invalidate_multiple_data_lines( + rtems_cache_invalidate_multiple_data_lines( (const void *) RxBd[minor]->buffer, RxBd[minor]->length ); @@ -1098,7 +1098,7 @@ m8xx_uart_pollRead( /* * TODO: Get a free buffer and set it up. */ -int +int m8xx_uart_write( int minor, const char *buf, @@ -1113,7 +1113,7 @@ m8xx_uart_write( TxBd[minor]->status = M8260_BD_READY | M8260_BD_WRAP | M8260_BD_INTERRUPT; return 0; } - + int m8xx_uart_pollWrite( diff --git a/c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c b/c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c index 7f56abff7e..b8adf9feaf 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c +++ b/c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c @@ -2,7 +2,7 @@ * cp.c * * MPC8xx CPM RISC Communication Processor routines. - * + * * Based on code (alloc860.c in eth_comm port) by * Jay Monkman (jmonkman@frasca.com), * which, in turn, is based on code by @@ -23,7 +23,7 @@ void m8xx_cp_execute_cmd( uint32_t command ) { uint16_t lvl; - + rtems_interrupt_disable(lvl); while (m8260.cpcr & M8260_CR_FLG) { continue; diff --git a/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c b/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c index b38a63ee16..4e6202ed79 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c +++ b/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c @@ -49,16 +49,16 @@ m8xx_dpram_allocate( unsigned int byte_count ) unsigned int i; ISR_Level level; void *blockp = NULL; - + byte_count = (byte_count + 3) & ~0x3; - + /* * Running with interrupts disabled is usually considered bad * form, but this routine is probably being run as part of an * initialization sequence so the effect shouldn't be too severe. */ _ISR_Disable (level); - + for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) { /* * Verify that the region is available for use. @@ -84,9 +84,9 @@ m8xx_dpram_allocate( unsigned int byte_count ) break; } } - + _ISR_Enable(level); - + if (blockp == NULL) rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count); return blockp; diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h b/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h index c73afa138a..34800a6ba5 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h +++ b/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h @@ -1,7 +1,7 @@ -/* +/* * cpm.h - * - * This include file contains definitions pertaining + * + * This include file contains definitions pertaining * to the Communications Processor Module (CPM) on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada @@ -104,7 +104,7 @@ void *m8xx_dpram_allocate( unsigned int byte_count ); #define m8xx_RISC_timer_table_allocate(count) \ m8xx_dpram_allocate( (count) * 4 ) - + int m8xx_get_brg_cd (int baud); int m8xx_get_brg(unsigned brgmask, int baud); @@ -114,7 +114,7 @@ void m8xx_free_brg(int brg_num); int m8xx_get_clk( unsigned clkmask ); void m8xx_free_clk( int clk_num ); - + #ifdef __cplusplus } #endif diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h b/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h index 352c7e25ca..66bd426c79 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h +++ b/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h @@ -1,7 +1,7 @@ -/* +/* * mmu.h - * - * This include file contains definitions pertaining + * + * This include file contains definitions pertaining * to the MMU on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada @@ -29,7 +29,7 @@ typedef struct { } MMU_TLB_table_t; /* - * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be + * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be * supplied by the BSP. */ extern MMU_TLB_table_t MMU_TLB_table[]; /* MMU TLB table supplied by BSP */ diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h b/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h index a710765650..ea088ebae8 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h +++ b/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h @@ -738,8 +738,8 @@ typedef struct m8260BufferDescriptor_ { */ typedef struct m8260IDMABufferDescriptor_ { uint16_t status; - uint8_t dfcr; - uint8_t sfcr; + uint8_t dfcr; + uint8_t sfcr; uint32_t length; void *source; void *destination; @@ -1178,7 +1178,7 @@ typedef struct m8260_ { uint8_t cpm_pad2[16384]; /* 0xC000 - 0xFFFF Reserved */ - + /* * General SIU Block */ @@ -1237,7 +1237,7 @@ typedef struct m8260_ { uint32_t immr; uint8_t mem_pad4[84]; - + /* * System integration timers */ @@ -1255,7 +1255,7 @@ typedef struct m8260_ { uint8_t sit_pad3[94]; uint8_t sit_pad4[2390]; - + /* * Interrupt Controller */ @@ -1283,7 +1283,7 @@ typedef struct m8260_ { uint32_t rsr; uint32_t rmr; uint8_t clr_pad0[104]; - + /* * Input/ Output Port @@ -1369,7 +1369,7 @@ typedef struct m8260_ { uint8_t idmr4; uint8_t dma_pad9[707]; - + /* * FCC Block */ @@ -1404,8 +1404,8 @@ typedef struct m8260_ { uint8_t i2m_pad4[3]; uint8_t i2cmr; uint8_t i2m_pad5[331]; - - + + /* * CPM Block */ @@ -1419,7 +1419,7 @@ typedef struct m8260_ { uint8_t cpm_pad4[2]; uint32_t rtsr; uint8_t cpm_pad5[12]; - + /* * BRG 1-4 Block @@ -1428,7 +1428,7 @@ typedef struct m8260_ { uint32_t brgc2; uint32_t brgc3; uint32_t brgc4; - + /* * SCC Block @@ -1438,14 +1438,14 @@ typedef struct m8260_ { m8260SCCRegisters_t scc3; m8260SCCRegisters_t scc4; - + /* * SMC Block */ m8260SMCRegisters_t smc1; m8260SMCRegisters_t smc2; - + /* * SPI Block */ @@ -1458,7 +1458,7 @@ typedef struct m8260_ { uint8_t spcom; uint8_t spi_pad3[82]; - + /* * CPM Mux Block */ diff --git a/c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c b/c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c index 5c1fac655f..278f5165ad 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c +++ b/c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c @@ -1,7 +1,7 @@ -/* +/* * mmu.c - * - * This file contains routines for initializing + * + * This file contains routines for initializing * and manipulating the MMU on the MPC8xx. * * Copyright (c) 1999, National Research Council of Canada @@ -21,18 +21,18 @@ /* * mmu_init * - * This routine sets up the virtual memory maps on an MPC8xx. - * The MPC8xx does not support block address translation (BATs) - * and does not have segment registers. Thus, we must set up page + * This routine sets up the virtual memory maps on an MPC8xx. + * The MPC8xx does not support block address translation (BATs) + * and does not have segment registers. Thus, we must set up page * translation. However, its MMU supports variable size pages * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task. * - * The MPC8xx has separate data and instruction 32-entry translation - * lookaside buffers (TLB). By mapping all of DRAM as one huge page, - * we can preload the TLBs and not have to be concerned with taking + * The MPC8xx has separate data and instruction 32-entry translation + * lookaside buffers (TLB). By mapping all of DRAM as one huge page, + * we can preload the TLBs and not have to be concerned with taking * TLB miss exceptions. * - * We set up the virtual memory map so that virtual address of a + * We set up the virtual memory map so that virtual address of a * location is equal to its real address. */ void mmu_init( void ) @@ -50,11 +50,11 @@ void mmu_init( void ) * We can assume the MSR has already been set this way. */ - /* + /* * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR) * GPM [0] 0b0 = PowerPC mode * PPM [1] 0b0 = Page resolution of protection - * CIDEF [2] 0b0/0b1 = Default cache-inhibit attribute = + * CIDEF [2] 0b0/0b1 = Default cache-inhibit attribute = * NO for IMMU, YES for DMMU! * reserved/WTDEF [3] 0b0 = Default write-through attribute = not * RSV4x [4] 0b0 = 4 entries not reserved @@ -63,7 +63,7 @@ void mmu_init( void ) * reserved [7-18] 0x00 * xTLB_INDX [19-23] 31 = 0x1F * reserved [24-31] 0x00 - * + * * Note: It is important that cache-inhibit be set as the default for the * data cache when the DMMU is disabled in order to prevent internal memory * mapped registers from being cached accidentally when address translation @@ -74,15 +74,15 @@ void mmu_init( void ) reg1 = M8xx_MD_CTR_CIDEF | M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31); _mtspr( M8xx_MD_CTR, reg1 ); _isync; - - /* + + /* * Invalidate all TLB entries in both TLBs. * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so * all 32 entries are invalidated. */ __asm__ volatile ("tlbia\n"::); _isync; - + /* * Set Current Address Space ID Register (M_CASID). * Supervisor: CASID = 0 @@ -90,7 +90,7 @@ void mmu_init( void ) reg1 = 0; _mtspr( M8xx_M_CASID, reg1 ); - /* + /* * Initialize the MMU Access Protection Registers (MI_AP, MD_AP) * We ignore the Access Protection Group (APG) mechanism globally * by setting all of the Mx_AP fields to 0b01 : client access @@ -100,10 +100,10 @@ void mmu_init( void ) _mtspr( M8xx_MI_AP, reg1 ); _mtspr( M8xx_MD_AP, reg1 ); - /* + /* * Load both 32-entry TLBs with values from the MMU_TLB_table * which is defined in the BSP. - * Note the _TLB_Table must have at most 32 entries. This code + * Note the _TLB_Table must have at most 32 entries. This code * makes no effort to enforce this restriction. */ for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) { @@ -118,9 +118,9 @@ void mmu_init( void ) _mtspr( M8xx_MD_RPN, reg1 ); } - /* + /* * Turn on address translation by setting MSR[IR] and MSR[DR]. - */ + */ _CPU_MSR_GET( reg1 ); reg1 |= PPC_MSR_IR | PPC_MSR_DR; _CPU_MSR_SET( reg1 ); diff --git a/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c index 2b8d0b812d..be77f4fd14 100644 --- a/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c +++ b/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c @@ -73,7 +73,7 @@ void benchmark_timer_initialize(void) /* m860.tbscr |= M860_TBSCR_TBIRQ(4) | M860_TBSCR_TBE; */ - + Timer_starting = get_itimer(); } |