diff options
Diffstat (limited to 'c/src/lib/libcpu/powerpc/mpc5xx/irq')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c | 44 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h | 20 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S | 54 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c | 8 |
4 files changed, 63 insertions, 63 deletions
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c index c109bc35b2..443340a914 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c @@ -16,7 +16,7 @@ * * $Id$ */ - + #include <rtems.h> #include <rtems/score/apiext.h> #include <mpc5xx.h> @@ -28,12 +28,12 @@ * Convert an rtems_irq_number constant to an interrupt level * suitable for programming into an I/O device's interrupt level field. */ - + int CPU_irq_level_from_symbolic_name(const rtems_irq_number name) { if (CPU_USIU_EXT_IRQ_0 <= name && name <= CPU_USIU_INT_IRQ_7) return (name - CPU_USIU_EXT_IRQ_0) / 2; - + if (CPU_UIMB_IRQ_8 <= name && name <= CPU_UIMB_IRQ_31) return 8 + (name - CPU_UIMB_IRQ_8); @@ -84,9 +84,9 @@ static inline int is_proc_irq(const rtems_irq_number irqLine) /* - * Masks used to mask off the interrupts. For exmaple, for ILVL2, the - * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 - * and ILVL7. + * Masks used to mask off the interrupts. For exmaple, for ILVL2, the + * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 + * and ILVL7. * */ const static unsigned int USIU_IvectMask[CPU_USIU_IRQ_COUNT] = @@ -134,7 +134,7 @@ static void compute_USIU_IvectMask_from_prio () */ static int isValidInterrupt(int irq) { - if ( (irq < CPU_MIN_OFFSET) || (irq > CPU_MAX_OFFSET) + if ( (irq < CPU_MIN_OFFSET) || (irq > CPU_MAX_OFFSET) || (irq == CPU_UIMB_INTERRUPT) ) return 0; return 1; @@ -164,7 +164,7 @@ int CPU_irq_enabled_at_uimb(const rtems_irq_number irqLine) int CPU_irq_enable_at_usiu(const rtems_irq_number irqLine) { int usiu_irq_index; - + if (!is_usiu_irq(irqLine)) return 1; @@ -181,7 +181,7 @@ int CPU_irq_disable_at_usiu(const rtems_irq_number irqLine) if (!is_usiu_irq(irqLine)) return 1; - + usiu_irq_index = ((int) (irqLine) - CPU_USIU_IRQ_MIN_OFFSET); ppc_cached_irq_mask &= ~(1 << (31-usiu_irq_index)); usiu.simask = ppc_cached_irq_mask; @@ -207,7 +207,7 @@ int CPU_irq_enabled_at_usiu(const rtems_irq_number irqLine) int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -228,14 +228,14 @@ int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * store the data provided by user */ rtems_hdl_tbl[irq->name] = *irq; - + if (is_uimb_irq(irq->name)) { /* * Enable interrupt at UIMB level */ CPU_irq_enable_at_uimb (irq->name); } - + if (is_usiu_irq(irq->name)) { /* * Enable interrupt at USIU level @@ -254,7 +254,7 @@ int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq) */ if (irq->on) irq->on(irq); - + rtems_interrupt_enable(level); return 1; @@ -273,7 +273,7 @@ int CPU_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) int CPU_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -311,7 +311,7 @@ int CPU_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) /* * disable exception at processor level */ - } + } /* * restore the default irq value @@ -424,7 +424,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[CPU_DECREMENTER].hdl(rtems_hdl_tbl[CPU_DECREMENTER].handle); _CPU_MSR_SET(msr); @@ -448,20 +448,20 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) * interrupts. */ usiu.sipend = (1 << (31 - irq)); - + if (uimbIntr) { /* * Look at the bits set in the UIMB interrupt-pending register. The - * highest-order set bit indicates the handler we will run. + * highest-order set bit indicates the handler we will run. * * Unfortunately, we can't easily mask individual UIMB interrupts * unless they use USIU levels 0 to 6, so we must mask all low-level * (level > 7) UIMB interrupts while we service any interrupt. */ int uipend = imb.uimb.uipend << 8; - + if (uipend == 0) { /* spurious interrupt? use last vector */ - irq = CPU_UIMB_IRQ_MAX_OFFSET; + irq = CPU_UIMB_IRQ_MAX_OFFSET; } else { irq = CPU_UIMB_IRQ_MIN_OFFSET; @@ -473,7 +473,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); _CPU_MSR_SET(msr); @@ -482,7 +482,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) usiu.simask = ppc_cached_irq_mask; } } - + void _ThreadProcessSignalsFromIrq (CPU_Exception_frame* ctx) { /* diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h index 6086db8e65..87c6593e10 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h @@ -1,4 +1,4 @@ -/* +/* * irq.h * * This include file describe the data structure and the functions implemented @@ -40,8 +40,8 @@ extern volatile unsigned int ppc_cached_irq_mask; * Symblolic IRQ names and related definitions. */ - /* - * Base vector for our USIU IRQ handlers. + /* + * Base vector for our USIU IRQ handlers. */ #define CPU_USIU_VECTOR_BASE (CPU_ASM_IRQ_VECTOR_BASE) /* @@ -71,7 +71,7 @@ extern volatile unsigned int ppc_cached_irq_mask; #define CPU_MAX_OFFSET (CPU_PROC_IRQ_MAX_OFFSET) /* * USIU IRQ symbolic name definitions. - */ + */ #define CPU_USIU_EXT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 0) #define CPU_USIU_INT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 1) @@ -80,19 +80,19 @@ extern volatile unsigned int ppc_cached_irq_mask; #define CPU_USIU_EXT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 4) #define CPU_USIU_INT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 5) - + #define CPU_USIU_EXT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 6) #define CPU_USIU_INT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 7) - + #define CPU_USIU_EXT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 8) #define CPU_USIU_INT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 9) #define CPU_USIU_EXT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 10) #define CPU_USIU_INT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 11) - + #define CPU_USIU_EXT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 12) #define CPU_USIU_INT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 13) - + #define CPU_USIU_EXT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 14) #define CPU_USIU_INT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 15) @@ -101,7 +101,7 @@ extern volatile unsigned int ppc_cached_irq_mask; */ #define CPU_PERIODIC_TIMER (CPU_USIU_INT_IRQ_6) #define CPU_UIMB_INTERRUPT (CPU_USIU_INT_IRQ_7) - + /* * UIMB IRQ symbolic name definitions. The first 8 sources are aliases to * the USIU interrupts of the same number, because they are detected in @@ -140,7 +140,7 @@ extern volatile unsigned int ppc_cached_irq_mask; #define CPU_UIMB_IRQ_29 (CPU_UIMB_IRQ_MIN_OFFSET+21) #define CPU_UIMB_IRQ_30 (CPU_UIMB_IRQ_MIN_OFFSET+22) #define CPU_UIMB_IRQ_31 (CPU_UIMB_IRQ_MIN_OFFSET+23) - + /* * Symbolic names for UIMB interrupt sources. */ diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S index 9271a83f1d..cf79c13ed9 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S @@ -1,7 +1,7 @@ /* * irq_asm.S * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * IRQ veneers for RTEMS. * * The license and distribution terms for this file may be @@ -23,7 +23,7 @@ * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <libcpu/vectors.h> @@ -33,7 +33,7 @@ #define SYNC \ sync; \ isync - + /* * Common handler for interrupt exceptions. * @@ -46,22 +46,22 @@ * LR have been saved. R4 holds the exception number. */ PUBLIC_VAR(C_dispatch_irq_handler) - + PUBLIC_VAR(dispatch_irq_handler) SYM (dispatch_irq_handler): /* - * Save SRR0/SRR1 As soon As possible as it is the minimal needed + * Save SRR0/SRR1 As soon As possible as it is the minimal needed * to re-enable exception processing. - * + * * Note that R2 should never change (it's the EABI pointer to - * .sdata2), but we save it just in case. + * .sdata2), but we save it just in case. */ stw r0, GPR0_OFFSET(r1) stw r2, GPR2_OFFSET(r1) - + mfsrr0 r0 mfsrr1 r3 - + stw r0, SRR0_FRAME_OFFSET(r1) stw r3, SRR1_FRAME_OFFSET(r1) @@ -93,11 +93,11 @@ SYM (dispatch_irq_handler): mfcr r5 mfctr r6 mfxer r7 - + stw r5, EXC_CR_OFFSET(r1) stw r6, EXC_CTR_OFFSET(r1) stw r7, EXC_XER_OFFSET(r1) - + /* * Add some non volatile registers to store information that will be * used when returning from C handler. @@ -128,9 +128,9 @@ SYM (dispatch_irq_handler): bne nested mfspr r1, SPRG1 /* switch to interrupt stack */ -nested: +nested: - /* + /* * Start Incrementing nesting level in R3 */ addi r3, r3, 1 @@ -153,11 +153,11 @@ nested: /* * We are now running on the interrupt stack. External and decrementer * exceptions are still disabled. I see no purpose trying to optimize - * further assembler code. + * further assembler code. */ /* - * Call C exception handler for decrementer or external interrupt. + * Call C exception handler for decrementer or external interrupt. * Pass frame along just in case.. * * C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) @@ -166,7 +166,7 @@ nested: bl C_dispatch_irq_handler /* - * start decrementing nesting level. Note : do not test result against 0 + * start decrementing nesting level. Note : do not test result against 0 * value as an easy exit condition because if interrupt nesting level > 1 * then _Thread_Dispatch_disable_level > 1 */ @@ -187,7 +187,7 @@ nested: cmpwi r3, 0 /* - * switch back to original stack (done here just optimize registers + * switch back to original stack (done here just optimize registers * contention. Could have been done before...) */ addi r1, r14, 0 @@ -196,14 +196,14 @@ nested: /* * Here we are running again on the thread system stack. * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0. - * Interrupt are still disabled. Time to check if scheduler request to + * Interrupt are still disabled. Time to check if scheduler request to * do something with the current thread... */ addis r4, 0, _Context_Switch_necessary@ha lbz r5, _Context_Switch_necessary@l(r4) cmpwi r5, 0 bne switch - + addis r6, 0, _ISR_Signals_to_thread_executing@ha lbz r7, _ISR_Signals_to_thread_executing@l(r6) cmpwi r7, 0 @@ -241,12 +241,12 @@ nested: lwz r30, EXC_XER_OFFSET(r1) lwz r29, EXC_CR_OFFSET(r1) lwz r28, EXC_LR_OFFSET(r1) - + mtctr r31 mtxer r30 mtcr r29 mtlr r28 - + lmw r4, GPR4_OFFSET(r1) lwz r2, GPR2_OFFSET(r1) lwz r0, GPR0_OFFSET(r1) @@ -260,22 +260,22 @@ nested: /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC rfi - + switch: bl SYM (_Thread_Dispatch) - -easy_exit: + +easy_exit: /* * start restoring interrupt frame */ @@ -283,7 +283,7 @@ easy_exit: lwz r4, EXC_XER_OFFSET(r1) lwz r5, EXC_CR_OFFSET(r1) lwz r6, EXC_LR_OFFSET(r1) - + mtctr r3 mtxer r4 mtcr r5 diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c index 9f2488a012..009443cca2 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c @@ -1,4 +1,4 @@ -/* +/* * irq_init.c * * This file contains the implementation of rtems initialization @@ -90,7 +90,7 @@ void CPU_USIU_irq_init() usiu.siel = usiu.siel; } -/* +/* * Initialize UIMB interrupt management */ void @@ -102,7 +102,7 @@ void CPU_rtems_irq_mng_init(unsigned cpuId) { rtems_raw_except_connect_data vectorDesc; int i; - + CPU_USIU_irq_init(); CPU_UIMB_irq_init(); /* @@ -130,7 +130,7 @@ void CPU_rtems_irq_mng_init(unsigned cpuId) */ BSP_panic("Unable to initialize RTEMS interrupt Management\n"); } - + /* * We must connect the raw irq handler for the two * expected interrupt sources : decrementer and external interrupts. |