3 files changed, 56 insertions, 19 deletions
diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/Makefile.am b/c/src/lib/libcpu/mips/tx39/vectorisrs/Makefile.am
index 16c4dbef0b..761fa2914c 100644
--- a/c/src/lib/libcpu/mips/tx39/vectorisrs/Makefile.am
+++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/Makefile.am
@@ -6,7 +6,7 @@ AUTOMAKE_OPTIONS = foreign 1.4
 
 PGM = $(ARCH)/vectorisrs.rel
 
-C_FILES = vectorisrs.c
+C_FILES = maxvectors.c vectorisrs.c
 
 vectorisrs_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
 
diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c
new file mode 100644
index 0000000000..0f1b649e33
--- /dev/null
+++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c
@@ -0,0 +1,30 @@
+/* 
+ *  This file contains the maximum number of vectors.  This can not
+ *  be determined without knowing the RTEMS CPU model. 
+ *
+ *  COPYRIGHT (c) 1989-2000.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+/*
+ *  Reserve first 32 for exceptions.
+ */
+
+/*
+ *  The Toshiba TX3904 attaches 4 of the eight interrupt bits to an
+ *  on-CPU interrupt controller so that these four bits map to 16
+ *  unique interrupts.  So you have: 2 software interrupts, an NMI,
+ *  and 16 others.
+ */
+
+#include <rtems.h>
+#include <libcpu/tx3904.h>
+
+unsigned int mips_interrupt_number_of_vectors = TX3904_MAXIMUM_VECTORS;
+
diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
index 71b4bb9804..997e7736b6 100644
--- a/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
+++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c
@@ -1,4 +1,6 @@
 /*
+ *  TX3904 Interrupt Vectoring 
+ *
  *  $Id$
  */
 
@@ -6,28 +8,19 @@
 #include <stdlib.h>
 #include <libcpu/tx3904.h>
 
-#define mips_get_cause( _cause ) \
-  do { \
-    asm volatile( "mfc0 %0, $13; nop" : "=r" (_cause) :  ); \
-  } while (0)
+void mips_default_isr( int vector );
 
-#define CALL_ISR(_vector) \
+#define CALL_ISR(_vector,_frame) \
   do { \
     if ( _ISR_Vector_table[_vector] ) \
-      (_ISR_Vector_table[_vector])(_vector); \
+      (_ISR_Vector_table[_vector])(_vector,_frame); \
     else \
-      mips_default_exception(_vector); \
+      mips_default_isr(_vector); \
   } while (0)
 
 #include <bspIo.h>  /* for printk */
 
-void mips_default_exception( int vector )
-{
-  printk( "Unhandled exception %d\n", vector );
-  rtems_fatal_error_occurred(1);
-}
-
-void mips_vector_isr_handlers( void )
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
 {
   unsigned int sr;
   unsigned int cause;
@@ -39,16 +32,30 @@ void mips_vector_isr_handlers( void )
   cause >>= CAUSE_IPSHIFT;
 
   if ( cause & 0x80 )       /* IP[5] ==> INT0 */
-    CALL_ISR( TX3904_IRQ_INT0 );
+    CALL_ISR( TX3904_IRQ_INT0, frame );
 
   if ( cause & 0x40 ) {     /* (IP[4] == 1) ==> IP[0-3] are valid */
     unsigned int v = (cause >> 2) & 0x0f;
-    CALL_ISR( v );
+    CALL_ISR( MIPS_INTERRUPT_BASE + v, frame );
   }
    
   if ( cause & 0x02 )       /* SW[0] */
-    CALL_ISR( TX3904_IRQ_SOFTWARE_1 );
+    CALL_ISR( TX3904_IRQ_SOFTWARE_1, frame );
 
   if ( cause & 0x01 )       /* IP[1] */
-    CALL_ISR( TX3904_IRQ_SOFTWARE_2 );
+    CALL_ISR( TX3904_IRQ_SOFTWARE_2, frame );
 }
+
+void mips_default_isr( int vector )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+      vector, cause, sr );
+  rtems_fatal_error_occurred(1);
+}
+