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-rw-r--r--c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c4
-rw-r--r--c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S6
2 files changed, 10 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c b/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c
index b216e21066..6f692e1aba 100644
--- a/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c
+++ b/c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c
@@ -10,10 +10,13 @@ void mips_install_isr_entries( void )
{
#if __mips == 1
void exc_utlb_code(void);
+ void exc_dbg_code(void);
void exc_norm_code(void);
memcpy( (void *)UT_VEC, exc_utlb_code, 40 ); /* utlbmiss vector */
+ memcpy( (void *)DB_VEC, exc_dbg_code, 40 );
memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vevtor */
+
#elif __mips == 3
void exc_tlb_code(void);
void exc_xtlb_code(void);
@@ -25,5 +28,6 @@ void mips_install_isr_entries( void )
memcpy( (void *)C_VEC, exc_cache_code, 40 ); /* cache error vector */
memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vector */
#endif
+
rtems_cache_flush_entire_data();
}
diff --git a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S
index e27b35e984..25ee7793d5 100644
--- a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S
+++ b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S
@@ -27,6 +27,12 @@ FRAME(exc_norm_code,sp,0,ra)
nop
ENDFRAME(exc_norm_code)
+FRAME(exc_dbg_code,sp,0,ra)
+ la k0, _DBG_Handler /* debug interrupt */
+ j k0
+ nop
+ENDFRAME(exc_dbg_code)
+
/* XXX this is dependent on IDT/SIM and needs to be addressed */
FRAME(exc_utlb_code,sp,0,ra)
la k0, (R_VEC+((48)*8))