3 files changed, 95 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/i960/i960rp/Makefile.am b/c/src/lib/libcpu/i960/i960rp/Makefile.am
new file mode 100644
index 0000000000..459716912c
--- /dev/null
+++ b/c/src/lib/libcpu/i960/i960rp/Makefile.am
@@ -0,0 +1,27 @@
+##
+## $Id$
+##
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../automake/lib.am
+
+C_FILES = cpu_install_intr_stack.c cpu_install_raw_isr.c
+C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
+
+H_FILES = 
+
+OBJS = $(C_O_FILES)
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+if i960rp
+all-local: $(ARCH) $(OBJS)
+endif
+
+EXTRA_DIST = cpu_install_intr_stack.c cpu_install_raw_isr.c
+
+include $(top_srcdir)/../../../../../automake/local.am
diff --git a/c/src/lib/libcpu/i960/i960rp/cpu_install_intr_stack.c b/c/src/lib/libcpu/i960/i960rp/cpu_install_intr_stack.c
new file mode 100644
index 0000000000..9e1deca598
--- /dev/null
+++ b/c/src/lib/libcpu/i960/i960rp/cpu_install_intr_stack.c
@@ -0,0 +1,31 @@
+/*
+ *  Install interrupt stack i960RP
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <libcpu/i960RP.h>
+
+extern i960_PRCB *Prcb;
+
+void _CPU_Install_interrupt_stack( void )
+{
+  i960_PRCB *prcb = Prcb;
+  unsigned32   level;
+  unsigned32 *isp = (int *) ISP_ADDR;
+  
+  /*  
+   *  Set the Interrupt Stack in the on-CPU memory.
+   *  Interrupts are disabled for safety.
+   */
+
+  _CPU_ISR_Disable( level );
+
+    prcb->intr_stack = _CPU_Interrupt_stack_low;
+
+    *isp = (unsigned32) prcb->intr_stack;
+
+  _CPU_ISR_Enable( level );
+}
+
diff --git a/c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c b/c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c
new file mode 100644
index 0000000000..9ee56993a5
--- /dev/null
+++ b/c/src/lib/libcpu/i960/i960rp/cpu_install_raw_isr.c
@@ -0,0 +1,37 @@
+/*
+ *  Install raw interrupt vector for i960RP
+ *
+ *  $Id$
+ */
+
+#include <rtems.h>
+#include <libcpu/i960RP.h>
+
+#define i960_vector_caching_enabled( _prcb ) \
+   ((*((unsigned int *) ICON_ADDR)) & 0x2000)
+
+extern i960_PRCB *Prcb;
+
+void _CPU_ISR_install_raw_handler(
+  unsigned32  vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  i960_PRCB   *prcb = &Prcb;
+  proc_ptr    *cached_intr_tbl = NULL;
+
+  /*  The i80960RP does not support vectors 0-7.  The first 9 entries
+   *  in the Interrupt Table are used to manage pending interrupts.
+   *  Thus vector 8, the first valid vector number, is actually in
+   *  slot 9 in the table.
+   */
+
+  *old_handler = prcb->intr_tbl[ vector + 1 ];
+
+  prcb->intr_tbl[ vector + 1 ] = new_handler;
+
+  if ( i960_vector_caching_enabled( prcb ) )
+    if ( (vector & 0xf) == 0x2 )       /* cacheable? */
+      cached_intr_tbl[ vector >> 4 ] = new_handler;
+}