1 files changed, 15 insertions, 131 deletions

diff --git a/c/src/lib/libcpu/arm/shared/arm920/mmu.c b/c/src/lib/libcpu/arm/shared/arm920/mmu.c
index 752314723d..a9f90a8fa6 100644
--- a/c/src/lib/libcpu/arm/shared/arm920/mmu.c
+++ b/c/src/lib/libcpu/arm/shared/arm920/mmu.c
@@ -7,26 +7,12 @@
  *  $Id$
  */
 #include <libcpu/mmu.h>
+#include <libcpu/arm-cp15.h>
 
 typedef uint32_t mmu_lvl1_t;
 
 extern uint32_t _ttbl_base;
 
-static inline uint32_t mmu_get_id(void);
-static inline uint32_t mmu_get_ctrl(void);
-static inline void mmu_set_ctrl(uint32_t val);
-static inline uint32_t mmu_get_trans_tbl(void);
-static inline void mmu_set_trans_tbl(uint32_t val);
-static inline uint32_t mmu_get_domain_ctrl(void);
-static inline void mmu_set_domain_ctrl(uint32_t val);
-static inline uint32_t mmu_get_fault_stat(void);
-static inline void mmu_set_fault_stat(uint32_t val);
-static inline uint32_t mmu_get_fault_addr(void);
-static inline void mmu_set_fault_addr(uint32_t val);
-static inline void mmu_set_cache_inval(void);
-static inline void mmu_set_tlb_inval(void);
-static inline uint32_t mmu_get_proc_id(void);
-static inline void mmu_set_proc_id(uint32_t val);
 static void mmu_set_map_inval(mmu_lvl1_t *base);
 
 #define MMU_CTRL_MMU_EN             (1 << 0)
@@ -54,25 +40,23 @@ static void mmu_set_map_inval(mmu_lvl1_t *base);
 
 #define MMU_SECT_AP_ALL (0x3 << 10)
 
-#define NOP ( { asm volatile ("nop\n" ); } )
-
 void mmu_init(mmu_sect_map_t *map)
 {
     mmu_lvl1_t *lvl1_base;
     int i;
 
     /* flush the cache and TLB */
-    mmu_set_cache_inval();
-    mmu_set_tlb_inval();
+    arm_cp15_cache_invalidate();
+    arm_cp15_tlb_invalidate();
 
     /* set manage mode access for all domains */
-    mmu_set_domain_ctrl(0xffffffff);
+    arm_cp15_set_domain_access_control(0xffffffff);
 
     lvl1_base = (mmu_lvl1_t *)&_ttbl_base;
 
     /* set up the trans table */
     mmu_set_map_inval(lvl1_base);
-    mmu_set_trans_tbl((uint32_t) lvl1_base);
+    arm_cp15_set_translation_table_base(lvl1_base);
 
     /* create a 1:1 mapping of the entire address space */
     i = 0;
@@ -120,118 +104,20 @@ void mmu_init(mmu_sect_map_t *map)
     }
 
     /* flush the cache and TLB */
-    mmu_set_cache_inval();
-    mmu_set_tlb_inval();
-
-    NOP;
-    NOP;
+    arm_cp15_cache_invalidate();
+    arm_cp15_tlb_invalidate();
 
     /*  I & D caches turned on */
-    mmu_set_ctrl(MMU_CTRL_DEFAULT |
-                 MMU_CTRL_D_CACHE_EN |
-                 MMU_CTRL_I_CACHE_EN |
-                 MMU_CTRL_ALIGN_FAULT_EN |
-                 MMU_CTRL_LITTLE_ENDIAN |
-                 MMU_CTRL_MMU_EN);
-
-    NOP;
-    NOP;
+    arm_cp15_set_control(MMU_CTRL_DEFAULT |
+                         MMU_CTRL_D_CACHE_EN |
+                         MMU_CTRL_I_CACHE_EN |
+                         MMU_CTRL_ALIGN_FAULT_EN |
+                         MMU_CTRL_LITTLE_ENDIAN |
+                         MMU_CTRL_MMU_EN);
 
     return;
 }
 
-
-static inline uint32_t mmu_get_id(void)
-{
-    uint32_t val;
-    asm volatile ("msr 15, 0, %0, cr0, cr0\n" : "=r" (val));
-    return val;
-}
-
-static inline uint32_t mmu_get_ctrl(void)
-{
-    uint32_t val;
-    asm volatile ("mrc 15, 0, %0, cr1, cr0\n" : "=r" (val));
-    return val;
-}
-
-static inline void mmu_set_ctrl(uint32_t val)
-{
-    asm volatile ("mcr 15, 0, %0, cr1, cr0, 0\n" : :"r" (val));
-}
-
-static inline uint32_t mmu_get_trans_tbl(void)
-{
-    uint32_t val;
-    asm volatile ("msr 15, 0, %0, cr2, cr0\n" : "=r" (val));
-    return val;
-}
-
-static inline void mmu_set_trans_tbl(uint32_t val)
-{
-    asm volatile ("mcr 15, 0, %0, cr2, cr0, 0\n" : :"r" (val));
-}
-
-static inline uint32_t mmu_get_domain_ctrl(void)
-{
-    uint32_t val;
-    asm volatile ("msr 15, 0, %0, cr3, cr0\n" : "=r" (val));
-    return val;
-}
-
-static inline void mmu_set_domain_ctrl(uint32_t val)
-{
-    asm volatile ("mcr 15, 0, %0, cr3, cr0, 0\n" : :"r" (val));
-}
-
-static inline uint32_t mmu_get_fault_stat(void)
-{
-    uint32_t val;
-    asm volatile ("msr 15, 0, %0, cr5, cr0\n" : "=r" (val));
-    return val;
-}
-
-static inline void mmu_set_fault_stat(uint32_t val)
-{
-    asm volatile ("mcr 15, 0, %0, cr5, cr0, 0\n" : :"r" (val));
-}
-
-static inline uint32_t mmu_get_fault_addr(void)
-{
-    uint32_t val;
-    asm volatile ("msr 15, 0, %0, cr6, cr0\n" : "=r" (val));
-    return val;
-}
-
-static inline void mmu_set_fault_addr(uint32_t val)
-{
-    asm volatile ("mcr 15, 0, %0, cr6, cr0, 0\n" : :"r" (val));
-}
-
-static inline void mmu_set_cache_inval(void)
-{
-    uint32_t val = 0;
-    asm volatile ("mcr 15, 0, %0, cr7, cr7, 0\n" : :"r" (val));
-}
-
-static inline void mmu_set_tlb_inval(void)
-{
-    uint32_t val = 0;
-    asm volatile ("mcr 15, 0, %0, cr8, cr7, 0\n" : :"r" (val));
-}
-
-static inline uint32_t mmu_get_proc_id(void)
-{
-    uint32_t val;
-    asm volatile ("msr 15, 0, %0, cr13, cr0\n" : "=r" (val));
-    return val;
-}
-
-static inline void mmu_set_proc_id(uint32_t val)
-{
-    asm volatile ("mcr 15, 0, %0, cr13, cr0, 0\n" : :"r" (val));
-}
-
 /* set all the level 1 entrys to be invalid descriptors */
 static void mmu_set_map_inval(mmu_lvl1_t *base)
 {
@@ -241,12 +127,10 @@ static void mmu_set_map_inval(mmu_lvl1_t *base)
     }
 }
 
-
 void mmu_set_cpu_async_mode(void)
 {
     uint32_t reg;
-    reg = mmu_get_ctrl();
+    reg = arm_cp15_get_control();
     reg |= 0xc0000000;
-    mmu_set_ctrl(reg);
+    arm_cp15_set_control(reg);
 }
-