diff options
Diffstat (limited to 'c/src/lib/libbsp/shared')
-rw-r--r-- | c/src/lib/libbsp/shared/include/zilog/z8036.h | 106 | ||||
-rw-r--r-- | c/src/lib/libbsp/shared/include/zilog/z8530.h | 97 |
2 files changed, 203 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/shared/include/zilog/z8036.h b/c/src/lib/libbsp/shared/include/zilog/z8036.h new file mode 100644 index 0000000000..fea1493905 --- /dev/null +++ b/c/src/lib/libbsp/shared/include/zilog/z8036.h @@ -0,0 +1,106 @@ +/** + * @file + * + * @brief Zilog Z8036 Counter/Timer/IO Chip + * + * This include file defines information related to a Zilog Z8036 + * Counter/Timer/IO Chip. It is a memory mapped part. + * + * @note This file shares as much as possible with the include file + * for the Z8536 via z8x36.h. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_ZILOG_Z8036_H +#define _RTEMS_ZILOG_Z8036_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* macros */ + +#define Z8036( ptr ) ((volatile struct z8036_map *)(ptr)) + +#define Z8x36_STATE0 ( z8036 ) \ + { /*char *garbage = *(Z8036(z8036))->???; */ } + + +#define Z8x36_WRITE( z8036, reg, data ) \ + (Z8036(z8036))->reg = (data) + + +#define Z8x36_READ( z8036, reg, data ) \ + (Z8036(z8036))->reg = (data) + +/* structures */ + +struct z8036_map { +/* MAIN CONTROL REGISTERS (0x00-0x07) */ + uint8_t MASTER_INTR; /* Master Interrupt Ctl Reg */ + uint8_t MASTER_CFG; /* Master Configuration Ctl Reg */ + uint8_t PORTA_VECTOR; /* Port A - Interrupt Vector */ + uint8_t PORTB_VECTOR; /* Port B - Interrupt Vector */ + uint8_t CNT_TMR_VECTOR; /* Counter/Timer Interrupt Vector */ + uint8_t PORTC_DATA_POLARITY; /* Port C - Data Path Polarity */ + uint8_t PORTC_DIRECTION; /* Port C - Data Direction */ + uint8_t PORTC_SPECIAL_IO_CTL; /* Port C - Special IO Control */ +/* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */ + uint8_t PORTA_CMD_STATUS; /* Port A - Command Status Reg */ + uint8_t PORTB_CMD_STATUS; /* Port B - Command Status Reg */ + uint8_t CT1_CMD_STATUS; /* Ctr/Timer 1 - Command Status Reg */ + uint8_t CT2_CMD_STATUS; /* Ctr/Timer 2 - Command Status Reg */ + uint8_t CT3_CMD_STATUS; /* Ctr/Timer 3 - Command Status Reg */ + uint8_t PORTA_DATA; /* Port A - Data */ + uint8_t PORTB_DATA; /* Port B - Data */ + uint8_t PORTC_DATA; /* Port C - Data */ +/* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */ + uint8_t CT1_CUR_CNT_MSB; /* Ctr/Timer 1 - Current Count (MSB) */ + uint8_t CT1_CUR_CNT_LSB; /* Ctr/Timer 1 - Current Count (LSB) */ + uint8_t CT2_CUR_CNT_MSB; /* Ctr/Timer 2 - Current Count (MSB) */ + uint8_t CT2_CUR_CNT_LSB; /* Ctr/Timer 2 - Current Count (LSB) */ + uint8_t CT3_CUR_CNT_MSB; /* Ctr/Timer 3 - Current Count (MSB) */ + uint8_t CT3_CUR_CNT_LSB; /* Ctr/Timer 3 - Current Count (LSB) */ + uint8_t CT1_TIME_CONST_MSB; /* Ctr/Timer 1 - Time Constant (MSB) */ + uint8_t CT1_TIME_CONST_LSB; /* Ctr/Timer 1 - Time Constant (LSB) */ + uint8_t CT2_TIME_CONST_MSB; /* Ctr/Timer 2 - Time Constant (MSB) */ + uint8_t CT2_TIME_CONST_LSB; /* Ctr/Timer 2 - Time Constant (LSB) */ + uint8_t CT3_TIME_CONST_MSB; /* Ctr/Timer 3 - Time Constant (MSB) */ + uint8_t CT3_TIME_CONST_LSB; /* Ctr/Timer 3 - Time Constant (LSB) */ + uint8_t CT1_MODE_SPEC; /* Ctr/Timer 1 - Mode Specification */ + uint8_t CT2_MODE_SPEC; /* Ctr/Timer 2 - Mode Specification */ + uint8_t CT3_MODE_SPEC; /* Ctr/Timer 3 - Mode Specification */ + uint8_t CURRENT_VECTOR; /* Current Vector */ +/* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */ + uint8_t PORTA_MODE; /* Port A - Mode Specification */ + uint8_t PORTA_HANDSHAKE; /* Port A - Handshake Specification */ + uint8_t PORTA_DATA_POLARITY; /* Port A - Data Path Polarity */ + uint8_t PORTA_DIRECTION; /* Port A - Data Direction */ + uint8_t PORTA_SPECIAL_IO_CTL; /* Port A - Special IO Control */ + uint8_t PORTA_PATT_POLARITY; /* Port A - Pattern Polarity */ + uint8_t PORTA_PATT_TRANS; /* Port A - Pattern Transition */ + uint8_t PORTA_PATT_MASK; /* Port A - Pattern Mask */ +/* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */ + uint8_t PORTB_MODE; /* Port B - Mode Specification */ + uint8_t PORTB_HANDSHAKE; /* Port B - Handshake Specification */ + uint8_t PORTB_DATA_POLARITY; /* Port B - Data Path Polarity */ + uint8_t PORTB_DIRECTION; /* Port B - Data Direction */ + uint8_t PORTB_SPECIAL_IO_CTL; /* Port B - Special IO Control */ + uint8_t PORTB_PATT_POLARITY; /* Port B - Pattern Polarity */ + uint8_t PORTB_PATT_TRANS; /* Port B - Pattern Transition */ + uint8_t PORTB_PATT_MASK; /* Port B - Pattern Mask */ +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/lib/libbsp/shared/include/zilog/z8530.h b/c/src/lib/libbsp/shared/include/zilog/z8530.h new file mode 100644 index 0000000000..161b9a022c --- /dev/null +++ b/c/src/lib/libbsp/shared/include/zilog/z8530.h @@ -0,0 +1,97 @@ +/** + * @file + * + * @brief Information Related to a Zilog Z8530 SCC Chip + * + * This include file defines information related to a Zilog Z8530 + * SCC Chip. It is a IO mapped part. + */ + +/* + * COPYRIGHT (c) 1989-2011. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_ZILOG_Z8530_H +#define _RTEMS_ZILOG_Z8530_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* macros */ + +#define VOL8( ptr ) ((volatile uint8_t *)(ptr)) + +#define Z8x30_STATE0 ( z8530 ) \ + { char *garbage; \ + (garbage) = *(VOL8(z8530)) \ + } + +#define Z8x30_WRITE_CONTROL( z8530, reg, data ) \ + *(VOL8(z8530)) = (reg); \ + *(VOL8(z8530)) = (data) + +#define Z8x30_READ_CONTROL( z8530, reg, data ) \ + *(VOL8(z8530)) = (reg); \ + (data) = *(VOL8(z8530)) + +#define Z8x30_WRITE_DATA( z8530, data ) \ + *(VOL8(z8530)) = (data); + +#define Z8x30_READ_DATA( z8530, data ) \ + (data) = *(VOL8(z8530)); + + +/* RR_0 Bit Definitions */ + +#define RR_0_TX_BUFFER_EMPTY 0x04 +#define RR_0_RX_DATA_AVAILABLE 0x01 + +/* read registers */ + +#define RR_0 0x00 +#define RR_1 0x01 +#define RR_2 0x02 +#define RR_3 0x03 +#define RR_4 0x04 +#define RR_5 0x05 +#define RR_6 0x06 +#define RR_7 0x07 +#define RR_8 0x08 +#define RR_9 0x09 +#define RR_10 0x0A +#define RR_11 0x0B +#define RR_12 0x0C +#define RR_13 0x0D +#define RR_14 0x0E +#define RR_15 0x0F + +/* write registers */ + +#define WR_0 0x00 +#define WR_1 0x01 +#define WR_2 0x02 +#define WR_3 0x03 +#define WR_4 0x04 +#define WR_5 0x05 +#define WR_6 0x06 +#define WR_7 0x07 +#define WR_8 0x08 +#define WR_9 0x09 +#define WR_10 0x0A +#define WR_11 0x0B +#define WR_12 0x0C +#define WR_13 0x0D +#define WR_14 0x0E +#define WR_15 0x0F + +#ifdef __cplusplus +} +#endif + +#endif |