diff options
Diffstat (limited to 'c/src/lib/libbsp/sh/gensh2/startup')
| -rw-r--r-- | c/src/lib/libbsp/sh/gensh2/startup/Makefile.in | 77 | ||||
| -rw-r--r-- | c/src/lib/libbsp/sh/gensh2/startup/bspclean.c | 43 | ||||
| -rw-r--r-- | c/src/lib/libbsp/sh/gensh2/startup/bspstart.c | 138 | ||||
| -rw-r--r-- | c/src/lib/libbsp/sh/gensh2/startup/hw_init.c | 140 | ||||
| -rw-r--r-- | c/src/lib/libbsp/sh/gensh2/startup/linkcmds | 216 | ||||
| -rw-r--r-- | c/src/lib/libbsp/sh/gensh2/startup/linkcmds.ram | 216 | ||||
| -rw-r--r-- | c/src/lib/libbsp/sh/gensh2/startup/linkcmds.rom | 217 |
7 files changed, 1047 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/sh/gensh2/startup/Makefile.in b/c/src/lib/libbsp/sh/gensh2/startup/Makefile.in new file mode 100644 index 0000000000..5b758601f5 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/Makefile.in @@ -0,0 +1,77 @@ +## +## $Id$ +## + +@SET_MAKE@ +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +top_builddir = ../../.. +subdir = sh/gensh2/startup + +RTEMS_ROOT = @RTEMS_ROOT@ +PROJECT_ROOT = @PROJECT_ROOT@ + +VPATH = @srcdir@:@srcdir@/../../shared:@srcdir@/../../../shared + +PGM = ${ARCH}/startup.rel + +# C source names, if any, go here -- minus the .c +C_PIECES = hw_init bsplibc bsppost bspstart bspclean sbrk bootcard main \ + gnatinstallhandler +C_FILES = $(C_PIECES:%=%.c) +C_O_FILES = $(C_PIECES:%=${ARCH}/%.o) + +H_FILES = + +# Assembly source names, if any, go here -- minus the .s +S_PIECES = +S_FILES = $(S_PIECES:%=%.S) +S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o) + +SRCS = linkcmds $(C_FILES) $(H_FILES) $(S_FILES) +OBJS = $(C_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +INSTALL_CHANGE = @INSTALL_CHANGE@ +mkinstalldirs = $(SHELL) $(top_srcdir)/@RTEMS_TOPdir@/mkinstalldirs + +INSTALLDIRS = $(PROJECT_RELEASE)/lib + +$(INSTALLDIRS): + @$(mkinstalldirs) $(INSTALLDIRS) + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += $(BSP_CPPFLAGS) +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + $(INSTALL_CHANGE) -m 644 $(srcdir)/linkcmds $(PROJECT_RELEASE)/lib + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile + +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) \ + && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status diff --git a/c/src/lib/libbsp/sh/gensh2/startup/bspclean.c b/c/src/lib/libbsp/sh/gensh2/startup/bspclean.c new file mode 100644 index 0000000000..fed966fdb4 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/bspclean.c @@ -0,0 +1,43 @@ +/* bsp_cleanup() + * + * This routine normally is part of start.s and usually returns + * control to a monitor. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, write to the Free Software Foundation, + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> + +void bsp_cleanup( void ) +{ +#if 0 + rtems_fatal_error_occurred(0); +#endif +} diff --git a/c/src/lib/libbsp/sh/gensh2/startup/bspstart.c b/c/src/lib/libbsp/sh/gensh2/startup/bspstart.c new file mode 100644 index 0000000000..abf97c3a86 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/bspstart.c @@ -0,0 +1,138 @@ +/* + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <bsp.h> +#include <rtems/libio.h> + +#include <libcsupport.h> + +#include <string.h> + +/* + * The original table from the application and our copy of it with + * some changes. + */ + +extern void hw_initialize(void); + +extern rtems_configuration_table Configuration; + +rtems_configuration_table BSP_Configuration; + +rtems_cpu_table Cpu_table; + +char *rtems_progname; + +/* + * Use the shared implementations of the following routines + */ + +void bsp_postdriver_hook(void); +void bsp_libc_init( void *, unsigned32, int ); + +/* + * Function: bsp_pretasking_hook + * + * Description: + * BSP pretasking hook. Called just before drivers are initialized. + * Used to setup libc and install any BSP extensions. + * + * NOTES: + * Must not use libc (to do io) from here, since drivers are + * not yet initialized. + * + */ + +void bsp_pretasking_hook(void) +{ + bsp_libc_init(&HeapStart, sizeof(unsigned32) * (&HeapEnd - &HeapStart), 0); + +#ifdef RTEMS_DEBUG + rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); +#endif +} + +/* + * bsp_start + * + * This routine does the bulk of the system initialization. + */ + +void bsp_start(void) +{ + /* + For real boards you need to setup the hardware + and need to copy the vector table from rom to ram. + + Depending on the board this can ether be done from inside the rom + startup code, rtems startup code or here. + */ + hw_initialize(); + + /* + * Allocate the memory for the RTEMS Work Space. This can come from + * a variety of places: hard coded address, malloc'ed from outside + * RTEMS world (e.g. simulator or primitive memory manager), or (as + * typically done by stock BSPs) by subtracting the required amount + * of work space from the last physical address on the CPU board. + */ + + /* + * Need to "allocate" the memory for the RTEMS Workspace and + * tell the RTEMS configuration where it is. This memory is + * not malloc'ed. It is just "pulled from the air". + */ + + BSP_Configuration.work_space_start = (void *) &WorkSpaceStart ; + BSP_Configuration.work_space_size = + (unsigned32) &WorkSpaceEnd - + (unsigned32) &WorkSpaceStart ; + + /* + * initialize the CPU table for this BSP + */ + +#if ( CPU_ALLOCATE_INTERRUPT_STACK == FALSE ) + _CPU_Interrupt_stack_low = &CPU_Interrupt_stack_low ; + _CPU_Interrupt_stack_high = &CPU_Interrupt_stack_high ; + + /* This isn't used anywhere */ + Cpu_table.interrupt_stack_size = + (unsigned32) (&CPU_Interrupt_stack_high) - + (unsigned32) (&CPU_Interrupt_stack_low) ; +#endif + + + Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ + Cpu_table.postdriver_hook = bsp_postdriver_hook; + +#if ( CPU_ALLOCATE_INTERRUPT_STACK == TRUE ) + Cpu_table.interrupt_stack_size = 4096; +#endif + + Cpu_table.clicks_per_second = HZ ; +} diff --git a/c/src/lib/libbsp/sh/gensh2/startup/hw_init.c b/c/src/lib/libbsp/sh/gensh2/startup/hw_init.c new file mode 100644 index 0000000000..be2cdab35b --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/hw_init.c @@ -0,0 +1,140 @@ +/* + * hw_init.c: set up sh7045F internal subunits + * + * Author: John M. Mills (jmills@tga.com) + * COPYRIGHT(c) 1999, TGA Technologies, Inc + * Norcross, GA 30071 U.S.A + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Adapted from Hitachi EVB7045F tutorial files by: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * + * This file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +#include <bsp.h> + +#include <stdlib.h> + +#include <rtems/libio.h> +#include <iosupp.h> +#include <rtems/score/sh_io.h> +#include <rtems/score/iosh7045.h> + +/* exported entry */ +extern void hw_initialize (void); + +/* STANDALONE_EVB sets up bus, DRAM, PFC, and SCI0 */ +/* no STANDALONE_EVB accepts defaults, adds RESET, SCI1, WDT */ + +/***************************************************/ +/* Inline function to access CPU features */ +/* from C. This makes use of GNU extensions. */ +/***************************************************/ + +__inline__ void set_interrupt_mask(unsigned char mask) +{ + asm("mov.l r0,@-r15"); + asm("mov %0,r0"::"r"(mask)); + asm("and #0xF,r0"); + asm("rotl r0"); + asm("rotl r0"); + asm("rotl r0"); + asm("rotl r0"); + asm("ldc r0,sr"); + asm("mov.l @r15+,r0"); +} + +void hw_initialize (void) +{ + int a; + unsigned8 temp8; + unsigned16 temp16; + +#ifdef STANDALONE_EVB + write16(0x2020, BSC_BCR1); /* Bus width access - 32-bit on CS1 */ + write16(0xF3DD, BSC_BCR2); /* Idle cycles CS3-CS0 - 0 idle cycles*/ + write16(0xFF3F, BSC_WCR1); /* Waits for CS3-CS0 - 3 waits on CS1 */ + write16(0x000F, BSC_WCR2); /* Waits for DRAM/DMA access - default */ + write16(0x0000, BSC_DCR); /* DRAM control - default */ + write16(0x0000, BSC_RTCSR); /* DRAM refresh - default */ + write16(0x0000, BSC_RTCNT); /* DRAM refresh counter - default*/ + write16(0x0000, BSC_RTCOR); /* DRAM refresh compare match - default */ + + write16(0x5000, PFC_PACRH); /* Pin function controller - WRHH, WRHL */ + write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */ + write16(0x0000, PFC_PBCR1); /* Pin function controller - default */ + write16(0x2005, PFC_PBCR2); /* Pin function controller - A18,A17,A16 */ + write16(0xFFFF, PFC_PCCR); /* Pin function controller - A15-A0 */ + write16(0x5555, PFC_PDCRH1; /* Pin function controller - D31-D24 */ + write16(0x5555, PFC_PDCRH2); /* Pin function controller - D23-D16 */ + write16(0xFFFF, PFC_PDCRL); /* Pin function controller - D15-D0 */ + write16(0x0000, PFC_IFCR); /* Pin function controller - default */ + write16(0x0005, PFC_PACRL2); /* Pin function controller - Tx0, Rx0 */ + + /* SCI0 */ +/* FIXME: This doesn't belong here */ + write8(0x00, SCI_SCR0); /* Clear SCR */ + write8(0x00, SCI_SMR0); /* Clear SMR */ + write8(0x5F, SCI_BRR0); /* Default 9600 baud rate */ +#if 0 + write8(0x1F, SCI_BRR0); /* 28800 baud */ +#endif +/* FIXME: Will get optimized away */ + for(a=0;a<00000L;a++); /* One bit delay */ + write8(0x30, SCI_SCR0); /* Enable clock output */ + temp8 = read8(SCI_RDR0); /* Clear out old input */ + +#endif + + /* default hardware setup */ + + /* PFC: General I/O except pin 13 (reset): */ + temp16 = read16(PFC_PECR1) | 0x0800; + write16(temp16, PFC_PECR1); + + /* All I/O lines bits 7-0: */ + write16(0x00, PFC_PECR2); + + /* P5 out, all other pins in: */ + temp16 = read16(PFC_PEIOR) | 0x0020; + write16(temp16, PFC_PEIOR); + + /* PFC - pins for Tx0-1, Rx0-1: */ + temp16 = read16(PFC_PACRL2) | 0x0145; + write16(temp16, PFC_PACRL2); + + /* SCI1 - Default RTEMS console */ +#if FIXME + /* write8(0x00, SCI_SCR1); /* Clear SCR */ + /* write8(0x00, SCI_SMR1); /* Clear SMR */ + /* write8(0x5F, SCI_BRR1); /* Default 9600 baud rate */ + /* write8(0x1F, SCI_BRR1); /* 28800 baud */ +/* FIXME: Will get optimized away */ + /* for(a=0;a<10000L;a++); /* One bit delay */ + /* write8(0x30, SCI_SCR1); /* Enable clock output */ + /* temp8 = read8(SCI_RDR1); /* Clear out old input */ + + /* INTC setup */ + /* set_interrupt_mask(0); /* enable interrupts */ + /* INTC_IPRF &= ~(SCI1_IPMSK); /* set SIO1 priority at INTC */ + /* INTC_IPRF |= SCI1_LOWIP; */ +#endif +} diff --git a/c/src/lib/libbsp/sh/gensh2/startup/linkcmds b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds new file mode 100644 index 0000000000..71258d7fe8 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds @@ -0,0 +1,216 @@ +/* + * This is an adapted linker script from egcs-1.0.1 + * + * Memory layout for an SH7045F with main memory in area 2 + * This memory layout it very similar to that used for Hitachi's + * EVB with CMON in FLASH + * + * NOTE: The ram start address may vary, all other start addresses are fixed + * Not suiteable for gdb's simulator + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Modified to reflect SH7045F processor and EVB: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +OUTPUT_FORMAT("coff-sh") +OUTPUT_ARCH(sh) +ENTRY(_start) + +/* These assignments load code into SH7045F EVB SRAM for monitor debugging */ + +MEMORY +{ + rom : o = 0x00400000, l = 0x00040000 + ram : o = 0x00440000, l = 0x00040000 + onchip_peri : o = 0xFFFF8000, l = 0x00000800 + onchip_ram : o = 0xFFFFF000, l = 0x00001000 +} + +/* Sections are defined for RAM loading and monitor debugging */ +SECTIONS +{ + /* boot vector table */ + .monvects 0x00400000 (NOLOAD): { + _monvects = . ; + } > rom + + /* monitor play area */ + .monram 0x00440000 (NOLOAD) : + { + _ramstart = .; + } > ram + + /* monitor vector table */ + .vects 0x00442000 (NOLOAD) : { + _vectab = . ; + *(.vects); + } + + /* Read-only sections, merged into text segment: */ + + . = 0x00444000 ; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.text : + { *(.rel.text) *(.rel.gnu.linkonce.t*) } + .rela.text : + { *(.rela.text) *(.rela.gnu.linkonce.t*) } + .rel.data : + { *(.rel.data) *(.rel.gnu.linkonce.d*) } + .rela.data : + { *(.rela.data) *(.rela.gnu.linkonce.d*) } + .rel.rodata : + { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } + .rela.rodata : + { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } =0 + .plt : { *(.plt) } + .text . : + { + *(.text) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + } > ram + _etext = .; + PROVIDE (etext = .); + .fini . : { *(.fini) } =0 + .rodata . : { *(.rodata) *(.gnu.linkonce.r*) } + .rodata1 . : { *(.rodata1) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(128) + (. & (128 - 1)); + .data . : + { + *(.data) + *(.gnu.linkonce.d*) + CONSTRUCTORS + } > ram + .data1 . : { *(.data1) } + .ctors . : + { + ___ctors = .; + *(.ctors) + ___ctors_end = .; + } + .dtors . : + { + ___dtors = .; + *(.dtors) + ___dtors_end = .; + } + .got . : { *(.got.plt) *(.got) } + .dynamic . : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata . : { *(.sdata) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss . : { *(.sbss) *(.scommon) } + .bss . : + { + *(.dynbss) + *(.bss) + *(COMMON) + } > ram + _end = . ; + PROVIDE (end = .); + + _HeapStart = . ; + . = . + 1024 * 20 ; + PROVIDE( _HeapEnd = . ); + + _WorkSpaceStart = . ; + . = 0x00480000 ; + PROVIDE(_WorkSpaceEnd = .); + + _CPU_Interrupt_stack_low = 0xFFFFF000 ; + _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram + /* These must appear regardless of . */ +} diff --git a/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.ram b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.ram new file mode 100644 index 0000000000..71258d7fe8 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.ram @@ -0,0 +1,216 @@ +/* + * This is an adapted linker script from egcs-1.0.1 + * + * Memory layout for an SH7045F with main memory in area 2 + * This memory layout it very similar to that used for Hitachi's + * EVB with CMON in FLASH + * + * NOTE: The ram start address may vary, all other start addresses are fixed + * Not suiteable for gdb's simulator + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Modified to reflect SH7045F processor and EVB: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +OUTPUT_FORMAT("coff-sh") +OUTPUT_ARCH(sh) +ENTRY(_start) + +/* These assignments load code into SH7045F EVB SRAM for monitor debugging */ + +MEMORY +{ + rom : o = 0x00400000, l = 0x00040000 + ram : o = 0x00440000, l = 0x00040000 + onchip_peri : o = 0xFFFF8000, l = 0x00000800 + onchip_ram : o = 0xFFFFF000, l = 0x00001000 +} + +/* Sections are defined for RAM loading and monitor debugging */ +SECTIONS +{ + /* boot vector table */ + .monvects 0x00400000 (NOLOAD): { + _monvects = . ; + } > rom + + /* monitor play area */ + .monram 0x00440000 (NOLOAD) : + { + _ramstart = .; + } > ram + + /* monitor vector table */ + .vects 0x00442000 (NOLOAD) : { + _vectab = . ; + *(.vects); + } + + /* Read-only sections, merged into text segment: */ + + . = 0x00444000 ; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.text : + { *(.rel.text) *(.rel.gnu.linkonce.t*) } + .rela.text : + { *(.rela.text) *(.rela.gnu.linkonce.t*) } + .rel.data : + { *(.rel.data) *(.rel.gnu.linkonce.d*) } + .rela.data : + { *(.rela.data) *(.rela.gnu.linkonce.d*) } + .rel.rodata : + { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } + .rela.rodata : + { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } =0 + .plt : { *(.plt) } + .text . : + { + *(.text) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + } > ram + _etext = .; + PROVIDE (etext = .); + .fini . : { *(.fini) } =0 + .rodata . : { *(.rodata) *(.gnu.linkonce.r*) } + .rodata1 . : { *(.rodata1) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(128) + (. & (128 - 1)); + .data . : + { + *(.data) + *(.gnu.linkonce.d*) + CONSTRUCTORS + } > ram + .data1 . : { *(.data1) } + .ctors . : + { + ___ctors = .; + *(.ctors) + ___ctors_end = .; + } + .dtors . : + { + ___dtors = .; + *(.dtors) + ___dtors_end = .; + } + .got . : { *(.got.plt) *(.got) } + .dynamic . : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata . : { *(.sdata) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss . : { *(.sbss) *(.scommon) } + .bss . : + { + *(.dynbss) + *(.bss) + *(COMMON) + } > ram + _end = . ; + PROVIDE (end = .); + + _HeapStart = . ; + . = . + 1024 * 20 ; + PROVIDE( _HeapEnd = . ); + + _WorkSpaceStart = . ; + . = 0x00480000 ; + PROVIDE(_WorkSpaceEnd = .); + + _CPU_Interrupt_stack_low = 0xFFFFF000 ; + _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram + /* These must appear regardless of . */ +} diff --git a/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.rom b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.rom new file mode 100644 index 0000000000..54d28e5552 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh2/startup/linkcmds.rom @@ -0,0 +1,217 @@ +/* + * This is an adapted linker script from egcs-1.0.1 + * + * Memory layout for an SH7045F with main memory in area 2 + * This memory layout it very similar to that used for Hitachi's + * EVB with CMON in FLASH + * + * NOTE: The ram start address may vary, all other start addresses are fixed + * Not suiteable for gdb's simulator + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * Modified to reflect SH7045F processor and EVB: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + * + * $Id$ + */ + +OUTPUT_FORMAT("coff-sh") +OUTPUT_ARCH(sh) +ENTRY(_start) + +/* These asignments represent actual SH7045F EVB architecture */ + +MEMORY +{ + rom : o = 0x00000000, l = 0x00040000 + ram : o = 0x00400000, l = 0x00080000 + onchip_peri : o = 0xFFFF8000, l = 0x00000800 + onchip_ram : o = 0xFFFFF000, l = 0x00001000 +} + + +/* Sections are defined for RAM loading and monitor debugging */ +SECTIONS +{ + /* boot vector table */ + .monvects 0x00000000 (NOLOAD): { + _monvects = . ; + } > rom + + /* monitor play area */ + .monram 0x00400000 (NOLOAD) : + { + _ramstart = .; + } > ram + + /* monitor vector table */ + .vects 0x00402000 (NOLOAD) : { + _vectab = . ; + *(.vects); + } + + /* Read-only sections, merged into text segment: */ + + . = 0x00404000 ; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.text : + { *(.rel.text) *(.rel.gnu.linkonce.t*) } + .rela.text : + { *(.rela.text) *(.rela.gnu.linkonce.t*) } + .rel.data : + { *(.rel.data) *(.rel.gnu.linkonce.d*) } + .rela.data : + { *(.rela.data) *(.rela.gnu.linkonce.d*) } + .rel.rodata : + { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } + .rela.rodata : + { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } =0 + .plt : { *(.plt) } + .text . : + { + *(.text) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + } > ram + _etext = .; + PROVIDE (etext = .); + .fini . : { *(.fini) } =0 + .rodata . : { *(.rodata) *(.gnu.linkonce.r*) } + .rodata1 . : { *(.rodata1) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(128) + (. & (128 - 1)); + .data . : + { + *(.data) + *(.gnu.linkonce.d*) + CONSTRUCTORS + } > ram + .data1 . : { *(.data1) } + .ctors . : + { + ___ctors = .; + *(.ctors) + ___ctors_end = .; + } + .dtors . : + { + ___dtors = .; + *(.dtors) + ___dtors_end = .; + } + .got . : { *(.got.plt) *(.got) } + .dynamic . : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata . : { *(.sdata) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss . : { *(.sbss) *(.scommon) } + .bss . : + { + *(.dynbss) + *(.bss) + *(COMMON) + } > ram + _end = . ; + PROVIDE (end = .); + + _HeapStart = . ; + . = . + 1024 * 20 ; + PROVIDE( _HeapEnd = . ); + + _WorkSpaceStart = . ; + . = 0x00480000 ; + PROVIDE(_WorkSpaceEnd = .); + + _CPU_Interrupt_stack_low = 0xFFFFF000 ; + _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram + /* These must appear regardless of . */ +} |