diff options
Diffstat (limited to 'c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c | 260 |
1 files changed, 130 insertions, 130 deletions
diff --git a/c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c b/c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c index 05e1a4d466..62e0ae27fa 100644 --- a/c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c +++ b/c/src/lib/libbsp/powerpc/ppcn_60x/universe/universe.c @@ -34,108 +34,108 @@ ********************************************************************/ typedef struct { - rtems_unsigned32 PCI_ID; /* Offset 0x0000 */ - rtems_unsigned32 PCI_CSR; /* Offset 0x0004 */ - rtems_unsigned32 PCI_CLASS; /* Offset 0x0008 */ - rtems_unsigned32 PCI_MISC0; /* Offset 0x000C */ - rtems_unsigned32 PCI_BS; /* Offset 0x0010 */ - rtems_unsigned32 Buf_Offset_0x0014[ 0x0A ]; /* Offset 0x0014 */ - rtems_unsigned32 PCI_MISC1; /* Offset 0x003C */ - rtems_unsigned32 Buf_Offset_0x0040[ 0x30 ]; /* Offset 0x0040 */ - rtems_unsigned32 LSI0_CTL; /* Offset 0x0100 */ - rtems_unsigned32 LSI0_BS; /* Offset 0x0104 */ - rtems_unsigned32 LSI0_BD; /* Offset 0x0108 */ - rtems_unsigned32 LSI0_TO; /* Offset 0x010C */ - rtems_unsigned32 Buf_Offset_0x0110; /* Offset 0x0110 */ - rtems_unsigned32 LSI1_CTL; /* Offset 0x0114 */ - rtems_unsigned32 LSI1_BS; /* Offset 0x0118 */ - rtems_unsigned32 LSI1_BD; /* Offset 0x011C */ - rtems_unsigned32 LSI1_TO; /* Offset 0x0120 */ - rtems_unsigned32 Buf_Offset_0x0124; /* Offset 0x0124 */ - rtems_unsigned32 LSI2_CTL; /* Offset 0x0128 */ - rtems_unsigned32 LSI2_BS; /* Offset 0x012C */ - rtems_unsigned32 LSI2_BD; /* Offset 0x0130 */ - rtems_unsigned32 LSI2_TO; /* Offset 0x0134 */ - rtems_unsigned32 Buf_Offset_0x0138; /* Offset 0x0138 */ - rtems_unsigned32 LSI3_CTL; /* Offset 0x013C */ - rtems_unsigned32 LSI3_BS; /* Offset 0x0140 */ - rtems_unsigned32 LSI3_BD; /* Offset 0x0144 */ - rtems_unsigned32 LSI3_TO; /* Offset 0x0148 */ - rtems_unsigned32 Buf_Offset_0x014C[ 0x09 ]; /* Offset 0x014C */ - rtems_unsigned32 SCYC_CTL; /* Offset 0x0170 */ - rtems_unsigned32 SCYC_ADDR; /* Offset 0x0174 */ - rtems_unsigned32 SCYC_EN; /* Offset 0x0178 */ - rtems_unsigned32 SCYC_CMP; /* Offset 0x017C */ - rtems_unsigned32 SCYC_SWP; /* Offset 0x0180 */ - rtems_unsigned32 LMISC; /* Offset 0x0184 */ - rtems_unsigned32 SLSI; /* Offset 0x0188 */ - rtems_unsigned32 L_CMDERR; /* Offset 0x018C */ - rtems_unsigned32 LAERR; /* Offset 0x0190 */ - rtems_unsigned32 Buf_Offset_0x0194[ 0x1B ]; /* Offset 0x0194 */ - rtems_unsigned32 DCTL; /* Offset 0x0200 */ - rtems_unsigned32 DTBC; /* Offset 0x0204 */ - rtems_unsigned32 DLA; /* Offset 0x0208 */ - rtems_unsigned32 Buf_Offset_0x020C; /* Offset 0x020C */ - rtems_unsigned32 DVA; /* Offset 0x0210 */ - rtems_unsigned32 Buf_Offset_0x0214; /* Offset 0x0214 */ - rtems_unsigned32 DCPP; /* Offset 0x0218 */ - rtems_unsigned32 Buf_Offset_0x021C; /* Offset 0x021C */ - rtems_unsigned32 DGCS; /* Offset 0x0220 */ - rtems_unsigned32 D_LLUE; /* Offset 0x0224 */ - rtems_unsigned32 Buf_Offset_0x0228[ 0x36 ]; /* Offset 0x0228 */ - rtems_unsigned32 LINT_EN; /* Offset 0x0300 */ - rtems_unsigned32 LINT_STAT; /* Offset 0x0304 */ - rtems_unsigned32 LINT_MAP0; /* Offset 0x0308 */ - rtems_unsigned32 LINT_MAP1; /* Offset 0x030C */ - rtems_unsigned32 VINT_EN; /* Offset 0x0310 */ - rtems_unsigned32 VINT_STAT; /* Offset 0x0314 */ - rtems_unsigned32 VINT_MAP0; /* Offset 0x0318 */ - rtems_unsigned32 VINT_MAP1; /* Offset 0x031C */ - rtems_unsigned32 STATID; /* Offset 0x0320 */ - rtems_unsigned32 V1_STATID; /* Offset 0x0324 */ - rtems_unsigned32 V2_STATID; /* Offset 0x0328 */ - rtems_unsigned32 V3_STATID; /* Offset 0x032C */ - rtems_unsigned32 V4_STATID; /* Offset 0x0330 */ - rtems_unsigned32 V5_STATID; /* Offset 0x0334 */ - rtems_unsigned32 V6_STATID; /* Offset 0x0338 */ - rtems_unsigned32 V7_STATID; /* Offset 0x033C */ - rtems_unsigned32 Buf_Offset_0x0340[ 0x30 ]; /* Offset 0x0340 */ - rtems_unsigned32 MAST_CTL; /* Offset 0x0400 */ - rtems_unsigned32 MISC_CTL; /* Offset 0x0404 */ - rtems_unsigned32 MISC_STAT; /* Offset 0x0408 */ - rtems_unsigned32 USER_AM; /* Offset 0x040C */ - rtems_unsigned32 Buf_Offset_0x0410[ 0x2bc ];/* Offset 0x0410 */ - rtems_unsigned32 VSI0_CTL; /* Offset 0x0F00 */ - rtems_unsigned32 VSI0_BS; /* Offset 0x0F04 */ - rtems_unsigned32 VSI0_BD; /* Offset 0x0F08 */ - rtems_unsigned32 VSI0_TO; /* Offset 0x0F0C */ - rtems_unsigned32 Buf_Offset_0x0f10; /* Offset 0x0F10 */ - rtems_unsigned32 VSI1_CTL; /* Offset 0x0F14 */ - rtems_unsigned32 VSI1_BS; /* Offset 0x0F18 */ - rtems_unsigned32 VSI1_BD; /* Offset 0x0F1C */ - rtems_unsigned32 VSI1_TO; /* Offset 0x0F20 */ - rtems_unsigned32 Buf_Offset_0x0F24; /* Offset 0x0F24 */ - rtems_unsigned32 VSI2_CTL; /* Offset 0x0F28 */ - rtems_unsigned32 VSI2_BS; /* Offset 0x0F2C */ - rtems_unsigned32 VSI2_BD; /* Offset 0x0F30 */ - rtems_unsigned32 VSI2_TO; /* Offset 0x0F34 */ - rtems_unsigned32 Buf_Offset_0x0F38; /* Offset 0x0F38 */ - rtems_unsigned32 VSI3_CTL; /* Offset 0x0F3C */ - rtems_unsigned32 VSI3_BS; /* Offset 0x0F40 */ - rtems_unsigned32 VSI3_BD; /* Offset 0x0F44 */ - rtems_unsigned32 VSI3_TO; /* Offset 0x0F48 */ - rtems_unsigned32 Buf_Offset_0x0F4C[ 0x9 ]; /* Offset 0x0F4C */ - rtems_unsigned32 VRAI_CTL; /* Offset 0x0F70 */ - rtems_unsigned32 VRAI_BS; /* Offset 0x0F74 */ - rtems_unsigned32 Buf_Offset_0x0F78[ 0x2 ]; /* Offset 0x0F78 */ - rtems_unsigned32 VCSR_CTL; /* Offset 0x0F80 */ - rtems_unsigned32 VCSR_TO; /* Offset 0x0F84 */ - rtems_unsigned32 V_AMERR; /* Offset 0x0F88 */ - rtems_unsigned32 VAERR; /* Offset 0x0F8C */ - rtems_unsigned32 Buf_Offset_0x0F90[ 0x19 ]; /* Offset 0x0F90 */ - rtems_unsigned32 VCSR_CLR; /* Offset 0x0FF4 */ - rtems_unsigned32 VCSR_SET; /* Offset 0x0FF8 */ - rtems_unsigned32 VCSR_BS; /* Offset 0x0FFC */ + uint32_t PCI_ID; /* Offset 0x0000 */ + uint32_t PCI_CSR; /* Offset 0x0004 */ + uint32_t PCI_CLASS; /* Offset 0x0008 */ + uint32_t PCI_MISC0; /* Offset 0x000C */ + uint32_t PCI_BS; /* Offset 0x0010 */ + uint32_t Buf_Offset_0x0014[ 0x0A ]; /* Offset 0x0014 */ + uint32_t PCI_MISC1; /* Offset 0x003C */ + uint32_t Buf_Offset_0x0040[ 0x30 ]; /* Offset 0x0040 */ + uint32_t LSI0_CTL; /* Offset 0x0100 */ + uint32_t LSI0_BS; /* Offset 0x0104 */ + uint32_t LSI0_BD; /* Offset 0x0108 */ + uint32_t LSI0_TO; /* Offset 0x010C */ + uint32_t Buf_Offset_0x0110; /* Offset 0x0110 */ + uint32_t LSI1_CTL; /* Offset 0x0114 */ + uint32_t LSI1_BS; /* Offset 0x0118 */ + uint32_t LSI1_BD; /* Offset 0x011C */ + uint32_t LSI1_TO; /* Offset 0x0120 */ + uint32_t Buf_Offset_0x0124; /* Offset 0x0124 */ + uint32_t LSI2_CTL; /* Offset 0x0128 */ + uint32_t LSI2_BS; /* Offset 0x012C */ + uint32_t LSI2_BD; /* Offset 0x0130 */ + uint32_t LSI2_TO; /* Offset 0x0134 */ + uint32_t Buf_Offset_0x0138; /* Offset 0x0138 */ + uint32_t LSI3_CTL; /* Offset 0x013C */ + uint32_t LSI3_BS; /* Offset 0x0140 */ + uint32_t LSI3_BD; /* Offset 0x0144 */ + uint32_t LSI3_TO; /* Offset 0x0148 */ + uint32_t Buf_Offset_0x014C[ 0x09 ]; /* Offset 0x014C */ + uint32_t SCYC_CTL; /* Offset 0x0170 */ + uint32_t SCYC_ADDR; /* Offset 0x0174 */ + uint32_t SCYC_EN; /* Offset 0x0178 */ + uint32_t SCYC_CMP; /* Offset 0x017C */ + uint32_t SCYC_SWP; /* Offset 0x0180 */ + uint32_t LMISC; /* Offset 0x0184 */ + uint32_t SLSI; /* Offset 0x0188 */ + uint32_t L_CMDERR; /* Offset 0x018C */ + uint32_t LAERR; /* Offset 0x0190 */ + uint32_t Buf_Offset_0x0194[ 0x1B ]; /* Offset 0x0194 */ + uint32_t DCTL; /* Offset 0x0200 */ + uint32_t DTBC; /* Offset 0x0204 */ + uint32_t DLA; /* Offset 0x0208 */ + uint32_t Buf_Offset_0x020C; /* Offset 0x020C */ + uint32_t DVA; /* Offset 0x0210 */ + uint32_t Buf_Offset_0x0214; /* Offset 0x0214 */ + uint32_t DCPP; /* Offset 0x0218 */ + uint32_t Buf_Offset_0x021C; /* Offset 0x021C */ + uint32_t DGCS; /* Offset 0x0220 */ + uint32_t D_LLUE; /* Offset 0x0224 */ + uint32_t Buf_Offset_0x0228[ 0x36 ]; /* Offset 0x0228 */ + uint32_t LINT_EN; /* Offset 0x0300 */ + uint32_t LINT_STAT; /* Offset 0x0304 */ + uint32_t LINT_MAP0; /* Offset 0x0308 */ + uint32_t LINT_MAP1; /* Offset 0x030C */ + uint32_t VINT_EN; /* Offset 0x0310 */ + uint32_t VINT_STAT; /* Offset 0x0314 */ + uint32_t VINT_MAP0; /* Offset 0x0318 */ + uint32_t VINT_MAP1; /* Offset 0x031C */ + uint32_t STATID; /* Offset 0x0320 */ + uint32_t V1_STATID; /* Offset 0x0324 */ + uint32_t V2_STATID; /* Offset 0x0328 */ + uint32_t V3_STATID; /* Offset 0x032C */ + uint32_t V4_STATID; /* Offset 0x0330 */ + uint32_t V5_STATID; /* Offset 0x0334 */ + uint32_t V6_STATID; /* Offset 0x0338 */ + uint32_t V7_STATID; /* Offset 0x033C */ + uint32_t Buf_Offset_0x0340[ 0x30 ]; /* Offset 0x0340 */ + uint32_t MAST_CTL; /* Offset 0x0400 */ + uint32_t MISC_CTL; /* Offset 0x0404 */ + uint32_t MISC_STAT; /* Offset 0x0408 */ + uint32_t USER_AM; /* Offset 0x040C */ + uint32_t Buf_Offset_0x0410[ 0x2bc ];/* Offset 0x0410 */ + uint32_t VSI0_CTL; /* Offset 0x0F00 */ + uint32_t VSI0_BS; /* Offset 0x0F04 */ + uint32_t VSI0_BD; /* Offset 0x0F08 */ + uint32_t VSI0_TO; /* Offset 0x0F0C */ + uint32_t Buf_Offset_0x0f10; /* Offset 0x0F10 */ + uint32_t VSI1_CTL; /* Offset 0x0F14 */ + uint32_t VSI1_BS; /* Offset 0x0F18 */ + uint32_t VSI1_BD; /* Offset 0x0F1C */ + uint32_t VSI1_TO; /* Offset 0x0F20 */ + uint32_t Buf_Offset_0x0F24; /* Offset 0x0F24 */ + uint32_t VSI2_CTL; /* Offset 0x0F28 */ + uint32_t VSI2_BS; /* Offset 0x0F2C */ + uint32_t VSI2_BD; /* Offset 0x0F30 */ + uint32_t VSI2_TO; /* Offset 0x0F34 */ + uint32_t Buf_Offset_0x0F38; /* Offset 0x0F38 */ + uint32_t VSI3_CTL; /* Offset 0x0F3C */ + uint32_t VSI3_BS; /* Offset 0x0F40 */ + uint32_t VSI3_BD; /* Offset 0x0F44 */ + uint32_t VSI3_TO; /* Offset 0x0F48 */ + uint32_t Buf_Offset_0x0F4C[ 0x9 ]; /* Offset 0x0F4C */ + uint32_t VRAI_CTL; /* Offset 0x0F70 */ + uint32_t VRAI_BS; /* Offset 0x0F74 */ + uint32_t Buf_Offset_0x0F78[ 0x2 ]; /* Offset 0x0F78 */ + uint32_t VCSR_CTL; /* Offset 0x0F80 */ + uint32_t VCSR_TO; /* Offset 0x0F84 */ + uint32_t V_AMERR; /* Offset 0x0F88 */ + uint32_t VAERR; /* Offset 0x0F8C */ + uint32_t Buf_Offset_0x0F90[ 0x19 ]; /* Offset 0x0F90 */ + uint32_t VCSR_CLR; /* Offset 0x0FF4 */ + uint32_t VCSR_SET; /* Offset 0x0FF8 */ + uint32_t VCSR_BS; /* Offset 0x0FFC */ } Universe_Memory; volatile Universe_Memory *UNIVERSE; @@ -144,18 +144,18 @@ volatile Universe_Memory *UNIVERSE; * PCI_bus_write */ void PCI_bus_write( - volatile rtems_unsigned32 * _addr, /* IN */ - rtems_unsigned32 _data /* IN */ + volatile uint32_t * _addr, /* IN */ + uint32_t _data /* IN */ ) { outport_32(_addr, _data); } -rtems_unsigned32 PCI_bus_read( - volatile rtems_unsigned32 * _addr /* IN */ +uint32_t PCI_bus_read( + volatile uint32_t * _addr /* IN */ ) { - rtems_unsigned32 data; + uint32_t data; inport_32(_addr, data); return data; @@ -177,8 +177,8 @@ rtems_unsigned32 PCI_bus_read( void InitializeUniverse() { - rtems_unsigned32 pci_id; - rtems_unsigned32 universe_temp_value; + uint32_t pci_id; + uint32_t universe_temp_value; /* * Verify the UNIVERSE CHIP ID @@ -309,10 +309,10 @@ void InitializeUniverse() * Slave Image 0 registers. */ void set_vme_base_address ( - rtems_unsigned32 base_address + uint32_t base_address ) { - volatile rtems_unsigned32 temp; + volatile uint32_t temp; /* * Calculate the current size of the Slave VME image 0 @@ -341,18 +341,18 @@ void set_vme_base_address ( /* * Gets the VME base address */ -rtems_unsigned32 get_vme_base_address () +uint32_t get_vme_base_address () { - volatile rtems_unsigned32 temp; + volatile uint32_t temp; temp = PCI_bus_read( &UNIVERSE->VSI0_BS ); temp &= 0xFFFFF000; return (temp); } -rtems_unsigned32 get_vme_slave_size() +uint32_t get_vme_slave_size() { - volatile rtems_unsigned32 temp; + volatile uint32_t temp; temp = PCI_bus_read( &UNIVERSE->VSI0_BD); temp &= 0xFFFFF000; temp = temp - get_vme_base_address (); @@ -363,9 +363,9 @@ rtems_unsigned32 get_vme_slave_size() * Set the size of the VME slave image * Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF) */ -void set_vme_slave_size (rtems_unsigned32 size) +void set_vme_slave_size (uint32_t size) { - volatile rtems_unsigned32 temp; + volatile uint32_t temp; if (size<0) size = 0; @@ -391,13 +391,13 @@ void set_vme_slave_size (rtems_unsigned32 size) * Returns the 16 bit location specified by vme_ptr, which must be a * pointer to VME D16 space */ -rtems_unsigned16 get_vme( - rtems_unsigned16 *vme_ptr +uint16_t get_vme( + uint16_t *vme_ptr ) { - rtems_unsigned16 result; + uint16_t result; - if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF) + if (vme_ptr > (uint16_t*)0x3EFFFFFF) { /* * LSI0_TO register to 0x3EFFF000 if it had not been updated already @@ -405,13 +405,13 @@ rtems_unsigned16 get_vme( if (( PCI_bus_read( &UNIVERSE->LSI0_TO ) & 0xFFFFF000) != 0x3EFFF000) PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 ); - result = (*(rtems_unsigned16 *)( - ((rtems_unsigned32)vme_ptr - 0x3EFFF000)+ + result = (*(uint16_t*)( + ((uint32_t)vme_ptr - 0x3EFFF000)+ PPCN_60X_PCI_MEM_BASE) ); } else - result = (*(rtems_unsigned16 *) - ((rtems_unsigned32)vme_ptr+PPCN_60X_PCI_MEM_BASE)); + result = (*(uint16_t*) + ((uint32_t)vme_ptr+PPCN_60X_PCI_MEM_BASE)); return result; } @@ -421,23 +421,23 @@ rtems_unsigned16 get_vme( * be a pointer to VME D16 space */ void put_vme( - rtems_unsigned16 *vme_ptr, - rtems_unsigned16 value + uint16_t *vme_ptr, + uint16_t value ) { - if (vme_ptr > (rtems_unsigned16 *)0x3EFFFFFF) { + if (vme_ptr > (uint16_t*)0x3EFFFFFF) { /* * LSI0_TO register to 0x3EFFF000 if it had not been updated already */ if (( PCI_bus_read( &UNIVERSE->LSI0_TO) & 0xFFFFF000) != 0x3EFFF000) PCI_bus_write( &UNIVERSE->LSI0_TO, 0x3EFFF000 ); - *(rtems_unsigned16 *) (((rtems_unsigned32)vme_ptr - 0x3EFFF000) + + *(uint16_t*) (((uint32_t)vme_ptr - 0x3EFFF000) + PPCN_60X_PCI_MEM_BASE) = value; } else - *(rtems_unsigned16 *)((rtems_unsigned32)vme_ptr + + *(uint16_t*)((uint32_t)vme_ptr + PPCN_60X_PCI_MEM_BASE) = value; } #endif |