diff options
Diffstat (limited to 'c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S')
| -rw-r--r-- | c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S | 374 |
1 files changed, 160 insertions, 214 deletions
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S index 1e26ebd1b2..ee18d41a5f 100644 --- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S +++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S @@ -7,15 +7,19 @@ */ /* - * Copyright (c) 2008 - * Embedded Brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * rtems@embedded-brains.de + * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. * - * The license and distribution terms for this file may be found in the file - * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ */ /** @@ -24,267 +28,209 @@ * @ingroup mpc55xx */ +#include <bspopts.h> + #include <libcpu/powerpc-utility.h> + #include <mpc55xx/reg-defs.h> -#include <bspopts.h> + +#include <bsp/vectors.h> + +#define HAS_CACHE (BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED) + + .extern mpc55xx_fmpll_config + .extern mpc55xx_fmpll_init + .extern mpc55xx_flash_init + .extern mpc55xx_early_init + .extern bsp_start_zero + .extern bsp_ram_start + .extern bsp_ram_size + .extern bsp_ram_end + .extern __eabi + .extern boot_card + + .globl _start -.section ".bsp_start_text", "ax" #ifdef MPC55XX_BOOTFLAGS -PUBLIC_VAR (mpc55xx_bootflag_0) -PUBLIC_VAR (mpc55xx_bootflag_1) + .globl mpc55xx_bootflag_0 + .globl mpc55xx_bootflag_1 #endif -PUBLIC_VAR (start) -.globl fmpll_syncr_vals -bam_rchw: -/* - * BAM - */ + + .section ".bsp_start_text", "ax" /* BAM: RCHW */ .int 0x005a0000 -#ifdef MPC55XX_BOOTFLAGS - /* BAM: Address of start instruction - * We skip over the next two boot flag words to the next - * 64-bit aligned start address. It is 64-bit aligned - * to play well with FLASH programming. - * These boot flags can be set by debuggers and emulators to - * customize boot. - * Currently bit0 of bootflag_0 means to "skip setting up the MMU", - * allowing external MMU setup in a debugger before branching - * to 0x10. This can be used e.g., to map FLASH into RAM. - */ - .int 0x00000010 /* Start address is 0x10. */ + /* BAM: Address of start instruction */ + .int _start +#ifdef MPC55XX_BOOTFLAGS + /* + * We skip over the next two boot flag words to the next 64-bit + * aligned start address. It is 64-bit aligned to play well with + * FLASH programming. These boot flags can be set by debuggers + * and emulators to customize boot. Currently bit0 of + * bootflag_0 means to "skip setting up the MMU", allowing + * external MMU setup in a debugger before branching to 0x10. + * This can be used e.g., to map FLASH into RAM. + */ mpc55xx_bootflag_0: - .int 0xffffffff + .int 0xffffffff mpc55xx_bootflag_1: - .int 0xffffffff - -#else - .int 0x00000008 /* Start address is 0x08. */ + .int 0xffffffff #endif -/* - * Enable time base - */ -start: - li r0, 0 - mtspr TBWU, r0 - mtspr TBWL, r0 - mfspr r2, HID0 - ori r2, r2, 0x4000 - mtspr HID0, r2 +_start: -/* - * System clock - */ - - LWI r3,fmpll_syncr_vals - bl SYM (mpc55xx_fmpll_reset_config) - -/* - * Enable branch prediction - */ + /* Enable time base */ + li r0, 0 + mtspr TBWU, r0 + mtspr TBWL, r0 + mfspr r2, HID0 + ori r2, r2, 0x4000 + mtspr HID0, r2 - LWI r2, BUCSR_BBFI | BUCSR_BPEN - mtspr BUCSR, r2 + /* FMPLL setup */ + LWI r3, mpc55xx_fmpll_config + bl mpc55xx_fmpll_init -/* - * Basics - */ + /* Enable branch prediction */ + LWI r2, BUCSR_BBFI | BUCSR_BPEN + mtspr BUCSR, r2 - /* Set stack start to end of ram */ - LA r1, bsp_ram_end - addi r1, r1, -8 + /* Set intermediate stack start to end of internal SRAM */ + LA r1, bsp_ram_end + subi r1, r1, 16 /* Enable SPE */ - mfmsr r2 - oris r2, r2, 0x200 - mtmsr r2 + mfmsr r2 + oris r2, r2, 0x200 + mtmsr r2 /* Config internal flash */ - bl SYM (mpc55xx_flash_config) + bl mpc55xx_flash_init -#if BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED - /* FIXME: Config cache */ +#if HAS_CACHE bl config_cache -#endif /* BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED */ - -/* - * TODO, FIXME: Enable cache in the MMU for the SRAM - */ -.equ MAS0, 624 -.equ MAS1, 625 -.equ MAS2, 626 -.equ MAS3, 627 - -/* Read back MMU TLB1 entry 3 (internal SRAM) and enable the cache. - */ - LWI r3, 0x10030000 - mtspr MAS0, r3 - tlbre - LWI r4, ~0x00000008 - mfspr r3, MAS2 - and r3, r3, r4 - mtspr MAS2, r3 - tlbwe - -/* - * TODO, FIXME: Set MMU for the external SRAM - */ - -/* Read back MMU TLB1 entry 2 (external SRAM) and set the - * logical address to the external RAM start. - */ - LWI r3, 0x10020000 - mtspr MAS0, r3 + /* Enable cache in the MMU for the internal SRAM */ + LWI r3, 0x10030000 + mtspr FSL_EIS_MAS0, r3 tlbre - LWI r4, 0xfff - mfspr r3, MAS3 - and r3, r3, r4 - LA r4, bsp_external_ram_start - or r3, r3, r4 - mtspr MAS3, r3 + LWI r4, ~0x00000008 + mfspr r3, FSL_EIS_MAS2 + and r3, r3, r4 + mtspr FSL_EIS_MAS2, r3 tlbwe +#endif -/* Read back MMU TLB1 entry 1 (internal flash) and disable - * write access. - */ - LWI r3, 0x10010000 - mtspr MAS0, r3 - tlbre - LWI r4, ~0x0000000C - mfspr r3, MAS3 - and r3, r3, r4 - mtspr MAS3, r3 - tlbwe - -/* - * Zero RAM (needed to get proper ECC) - */ - - /* Addresses */ - LA r3, bsp_ram_start - LA r4, bsp_ram_size - - /* Zero */ - bl SYM (bsp_start_zero) - -/* - * Copy data - */ - - /* Addresses */ - LA r3, bsp_section_text_end - LA r4, bsp_section_data_start - LA r5, bsp_section_data_end - - /* Assert: Proper alignment of source start */ - andi. r6, r3, 0x7 - bne twiddle + /* Zero internal SRAM (needed to get proper ECC) */ + LA r3, bsp_ram_start + LA r4, bsp_ram_size + bl bsp_start_zero - /* Assert: Proper alignment of destination start */ - andi. r6, r4, 0x7 - bne twiddle + /* Initialize intermediate start stack */ + li r0, 0 + stw r0, 0(r1) + stw r0, 4(r1) - /* Assert: Proper alignment of destination end */ - andi. r6, r5, 0x7 - bne twiddle + /* Do early initialization */ + bl mpc55xx_early_init - /* Data size = destination end - destination start */ - subf r5, r4, r5 + /* Set up EABI and SYSV environment */ + bl __eabi - /* Copy */ - bl SYM (mpc55xx_copy_8) + /* Initialize start stack */ + LWI r1, start_stack_end + subi r1, r1, 16 + li r0, 0 + stw r0, 0(r1) - /* Save time and get time delta */ - mftb r26 - subf r25, r25, r26 + /* Clear command line */ + li r3, 0 -/* - * Prepare high level initialization - */ + /* Start RTEMS */ + bl boot_card - /* Create NULL */ - li r0, 0 + /* Spin around */ +twiddle: + b twiddle - /* Return address */ - stw r0, 4(r1) +#if HAS_CACHE +config_cache: - /* Back chain */ - stw r0, 0(r1) + /* Load zero, CINV, and CABT) */ + li r0, 0 + li r3, 0x2 + li r4, 0x4 - /* Read-only small data */ - LA r2, _SDA2_BASE_ +#if MPC55XX_CHIP_TYPE / 10 == 567 +start_instruction_cache_invalidation: - /* Read-write small data */ - LA r13, _SDA_BASE_ + /* Clear instruction cache invalidation abort */ + mtspr FSL_EIS_L1CSR1, r0 -/* - * Start RTEMS - */ + /* Start instruction cache invalidation */ + mtspr FSL_EIS_L1CSR1, r3 - /* Clear command line */ - xor r3, r3, r3 +get_instruction_cache_invalidation_status: - /* Start RTEMS */ - bl SYM (boot_card) + /* Get instruction cache invalidation status */ + mfspr r5, FSL_EIS_L1CSR1 - /* Spin around */ - b twiddle + /* Check CABT */ + and. r6, r5, r4 + bne start_instruction_cache_invalidation -.equ L1CSR0, 1010 -.equ L1CSR0_CINV, 0x2 -.equ L1CSR0_CABT, 0x4 -/* FIXME: CORG??? .equ L1CSR0_SETTINGS, 0x00180011 */ -.equ L1CSR0_SETTINGS, 0x00100001 + /* Check CINV */ + and. r6, r5, r3 + bne get_instruction_cache_invalidation_status -/* - * Configure cache - */ -config_cache: - /* Start cache invalidation */ - LWI r5, L1CSR0_CINV - mtspr L1CSR0, r5 + /* Save instruction cache settings */ + LWI r6, 0x00010001 + isync + msync + mtspr FSL_EIS_L1CSR1, r6 +#endif /* MPC55XX_CHIP_TYPE / 10 == 567 */ - /* Bit masks to test and clear invalidation abortion (CABT) */ - LWI r6, L1CSR0_CABT - not r7, r6 +start_data_cache_invalidation: - /* Wait for cache invalidation to complete */ -check_cache_invalidation: - mfspr r9, L1CSR0 + /* Clear data cache invalidation abort */ + mtspr FSL_EIS_L1CSR0, r0 - /* Check if the invalidate was aborted */ - and. r10, r9, r6 - beq no_chache_invalidation_abort + /* Start data cache invalidation */ + mtspr FSL_EIS_L1CSR0, r3 - /* Clear CABT bit */ - and r10, r9, r7 - mtspr L1CSR0, r10 +get_data_cache_invalidation_status: - /* Retry invalidation */ - b config_cache + /* Get data cache invalidation status */ + mfspr r5, FSL_EIS_L1CSR0 -no_chache_invalidation_abort: - /* Check CINV bit */ - and. r10, r5, r9 + /* Check CABT */ + and. r6, r5, r4 + bne start_data_cache_invalidation - /* Wait? */ - bne check_cache_invalidation + /* Check CINV */ + and. r6, r5, r3 + bne get_data_cache_invalidation_status - /* Enable cache */ - LWI r6, L1CSR0_SETTINGS - mfspr r5, L1CSR0 - or r5, r5, r6 - msync + /* Save data cache settings */ +#if MPC55XX_CHIP_TYPE / 10 != 567 + /* FIXME: CORG??? 0x00180011 */ + LWI r6, 0x00100001 +#else + LWI r6, 0x00190001 +#endif isync - mtspr L1CSR0, r5 + msync + mtspr FSL_EIS_L1CSR0, r6 /* Return */ blr +#endif /* HAS_CACHE */ -twiddle: - b twiddle + /* Start stack area */ + .section ".bsp_rwextra", "aw", @nobits + .align 4 + .space 4096 +start_stack_end: |