diff options
Diffstat (limited to 'c/src/lib/libbsp/mips/shared/irq/vectorexceptions.c')
-rw-r--r-- | c/src/lib/libbsp/mips/shared/irq/vectorexceptions.c | 118 |
1 files changed, 118 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/mips/shared/irq/vectorexceptions.c b/c/src/lib/libbsp/mips/shared/irq/vectorexceptions.c new file mode 100644 index 0000000000..475527e941 --- /dev/null +++ b/c/src/lib/libbsp/mips/shared/irq/vectorexceptions.c @@ -0,0 +1,118 @@ +/** + * @file + * + * Common Code for Vectoring MIPS Exceptions + * + * The actual decoding of the cause register and vector number assignment + * is CPU model specific. + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems.h> +#include <stdlib.h> +#include <string.h> +#include <rtems/mips/iregdef.h> +#include <rtems/mips/idtcpu.h> +#include <rtems/bspIo.h> +#include <bsp/irq-generic.h> + +void mips_vector_exceptions( CPU_Interrupt_frame *frame ); + +static const char *cause_strings[32] = +{ + /* 0 */ "Int", + /* 1 */ "TLB Mods", + /* 2 */ "TLB Load", + /* 3 */ "TLB Store", + /* 4 */ "Address Load", + /* 5 */ "Address Store", + /* 6 */ "Instruction Bus Error", + /* 7 */ "Data Bus Error", + /* 8 */ "Syscall", + /* 9 */ "Breakpoint", + /* 10 */ "Reserved Instruction", + /* 11 */ "Coprocessor Unuseable", + /* 12 */ "Overflow", + /* 13 */ "Trap", + /* 14 */ "Instruction Virtual Coherency Error", + /* 15 */ "FP Exception", + /* 16 */ "Reserved 16", + /* 17 */ "Reserved 17", + /* 18 */ "Reserved 18", + /* 19 */ "Reserved 19", + /* 20 */ "Reserved 20", + /* 21 */ "Reserved 21", + /* 22 */ "Reserved 22", + /* 23 */ "Watch", + /* 24 */ "Reserved 24", + /* 25 */ "Reserved 25", + /* 26 */ "Reserved 26", + /* 27 */ "Reserved 27", + /* 28 */ "Reserved 28", + /* 29 */ "Reserved 29", + /* 30 */ "Reserved 30", + /* 31 */ "Data Virtual Coherency Error" +}; + +struct regdef +{ + int offset; + char *name; +}; + +static const struct regdef dumpregs[]= { + { R_RA, "R_RA" }, { R_V0, "R_V0" }, { R_V1, "R_V1" }, + { R_A0, "R_A0" }, { R_A1, "R_A1" }, { R_A2, "R_A2" }, + { R_A3, "R_A3" }, { R_T0, "R_T0" }, { R_T1, "R_T1" }, + { R_T2, "R_T2" }, { R_T3, "R_T3" }, { R_T4, "R_T4" }, + { R_T5, "R_T5" }, { R_T6, "R_T6" }, { R_T7, "R_T7" }, + { R_T8, "R_T8" }, { R_MDLO, "R_MDLO" }, { R_MDHI, "R_MDHI" }, + { R_GP, "R_GP" }, { R_FP, "R_FP" }, { R_AT, "R_AT" }, + { R_EPC,"R_EPC"}, { -1, NULL } +}; + +static void mips_dump_exception_frame( CPU_Interrupt_frame *frame ) +{ + uint32_t *frame_u32; + int i, j; + + frame_u32 = (uint32_t *)frame; + for(i=0; dumpregs[i].offset > -1; i++) + { + printk(" %s", dumpregs[i].name); + for(j=0; j< 7-strlen(dumpregs[i].name); j++) printk(" "); +#if (__mips == 1 ) || (__mips == 32) + printk(" %08X%c", frame_u32[dumpregs[i].offset], (i%3) ? '\t' : '\n' ); +#elif __mips == 3 + printk(" %08X", frame_u32[2 * dumpregs[i].offset + 1] ); + printk("%08X%c", frame_u32[2 * dumpregs[i].offset], (i%2) ? '\t' : '\n' ); +#endif + } + printk( "\n" ); +} + +/* + * There are constants defined for these but they should basically + * all be close to the same set. + */ + +void mips_vector_exceptions( CPU_Interrupt_frame *frame ) +{ + uint32_t cause; + uint32_t exc; + + mips_get_cause( cause ); + exc = (cause >> 2) & 0x1f; + + bsp_interrupt_handler_dispatch( exc ); +} |