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-rw-r--r--c/src/lib/libbsp/m68k/csb360/startup/.cvsignore2
-rw-r--r--c/src/lib/libbsp/m68k/csb360/startup/bspclean.c38
-rw-r--r--c/src/lib/libbsp/m68k/csb360/startup/bspstart.c90
-rw-r--r--c/src/lib/libbsp/m68k/csb360/startup/init5272.c173
-rw-r--r--c/src/lib/libbsp/m68k/csb360/startup/linkcmds149
5 files changed, 452 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/m68k/csb360/startup/.cvsignore b/c/src/lib/libbsp/m68k/csb360/startup/.cvsignore
new file mode 100644
index 0000000000..282522db03
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/csb360/startup/.cvsignore
@@ -0,0 +1,2 @@
+Makefile
+Makefile.in
diff --git a/c/src/lib/libbsp/m68k/csb360/startup/bspclean.c b/c/src/lib/libbsp/m68k/csb360/startup/bspclean.c
new file mode 100644
index 0000000000..9e82bffade
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/csb360/startup/bspclean.c
@@ -0,0 +1,38 @@
+/*
+ * CSB360 cleanu code.
+ *
+ * This routine returns control from RTEMS to the dBUG monitor.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia.
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * COPYRIGHT (c) 1989-1998.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * bspclean.c,v 1.1 2001/10/26 19:30:11 joel Exp
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+
+/* bsp_cleanup --
+ * This function called when RTEMS execution is finished. bsp_cleanup
+ * for MCF5206eLITE evaluation board throw execution to the dBUG
+ * monitor.
+ *
+ * PARAMETERS:
+ * none
+ *
+ * RETURNS:
+ * none
+ */
+void
+bsp_cleanup(void)
+{
+}
diff --git a/c/src/lib/libbsp/m68k/csb360/startup/bspstart.c b/c/src/lib/libbsp/m68k/csb360/startup/bspstart.c
new file mode 100644
index 0000000000..e04f4bd65c
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/csb360/startup/bspstart.c
@@ -0,0 +1,90 @@
+/*
+ * BSP startup
+ *
+ * This routine starts the application. It includes application,
+ * board, and monitor specific initialization and configuration.
+ * The generic CPU dependent initialization has been performed
+ * before this routine is invoked.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * Based on work:
+ * Author:
+ * David Fiddes, D.J@fiddes.surfaid.org
+ * http://www.calm.hw.ac.uk/davidf/coldfire/
+ *
+ * COPYRIGHT (c) 1989-1998.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * bspstart.c,v 1.2 2002/11/04 14:26:32 joel Exp
+ */
+
+#include <bsp.h>
+#include <rtems/libio.h>
+
+#include <rtems/libcsupport.h>
+
+#include <string.h>
+
+/*
+ * The original table from the application and our copy of it with
+ * some changes.
+ */
+
+extern rtems_configuration_table Configuration;
+rtems_configuration_table BSP_Configuration;
+
+rtems_cpu_table Cpu_table;
+
+extern unsigned int _RamSize;
+
+
+char *rtems_progname;
+
+/*
+ * Use the shared implementations of the following routines
+ */
+
+void bsp_postdriver_hook(void);
+void bsp_libc_init( void *, unsigned32, int );
+void bsp_pretasking_hook(void); /* m68k version */
+
+/* bsp_start --
+ * This routine does the bulk of the system initialisation.
+ */
+void bsp_start( void )
+{
+ extern void *_WorkspaceBase;
+ extern unsigned long _M68k_Ramsize;
+ _M68k_Ramsize = (unsigned long)&_RamSize; /* size set in linker script */
+
+
+ /*
+ * Need to "allocate" the memory for the RTEMS Workspace and
+ * tell the RTEMS configuration where it is. This memory is
+ * not malloc'ed. It is just "pulled from the air".
+ */
+
+ BSP_Configuration.work_space_start = (void *)&_WorkspaceBase;
+
+ /*
+ * initialize the CPU table for this BSP
+ */
+ Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
+
+ Cpu_table.postdriver_hook = bsp_postdriver_hook;
+
+ Cpu_table.do_zero_of_workspace = TRUE;
+
+ Cpu_table.interrupt_stack_size = 4096;
+
+ Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
+
+}
diff --git a/c/src/lib/libbsp/m68k/csb360/startup/init5272.c b/c/src/lib/libbsp/m68k/csb360/startup/init5272.c
new file mode 100644
index 0000000000..c2d4e442ce
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/csb360/startup/init5272.c
@@ -0,0 +1,173 @@
+/*
+ * CSB360 hardware startup routines
+ *
+ * This is where the real hardware setup is done. A minimal stack
+ * has been provided by the start.S code. No normal C or RTEMS
+ * functions can be called from here.
+ *
+ * This initialization code based on hardware settings of dBUG
+ * monitor. This must be changed if you like to run it immediately
+ * after reset.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * Based on work:
+ * Author:
+ * David Fiddes, D.J@fiddes.surfaid.org
+ * http://www.calm.hw.ac.uk/davidf/coldfire/
+ *
+ * COPYRIGHT (c) 1989-1998.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * init5206e.c,v 1.1 2001/10/26 19:30:11 joel Exp
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <mcf5272/mcf5272.h>
+
+/* Set the pointers to the modules */
+sim_regs_t *g_sim_regs = (void *) MCF5272_SIM_BASE(BSP_MBAR);
+intctrl_regs_t *g_intctrl_regs = (void *) MCF5272_INT_BASE(BSP_MBAR);
+chipsel_regs_t *g_chipsel_regs = (void *) MCF5272_CS_BASE(BSP_MBAR);
+gpio_regs_t *g_gpio_regs = (void *) MCF5272_GPIO_BASE(BSP_MBAR);
+qspi_regs_t *g_qspi_regs = (void *) MCF5272_QSPI_BASE(BSP_MBAR);
+pwm_regs_t *g_pwm_regs = (void *) MCF5272_PWM_BASE(BSP_MBAR);
+dma_regs_t *g_dma_regs = (void *) MCF5272_DMAC_BASE(BSP_MBAR);
+uart_regs_t *g_uart0_regs = (void *) MCF5272_UART0_BASE(BSP_MBAR);
+uart_regs_t *g_uart1_regs = (void *) MCF5272_UART1_BASE(BSP_MBAR);
+timer_regs_t *g_timer_regs = (void *) MCF5272_TIMER_BASE(BSP_MBAR);
+plic_regs_t *g_plic_regs = (void *) MCF5272_PLIC_BASE(BSP_MBAR);
+enet_regs_t *g_enet_regs = (void *) MCF5272_ENET_BASE(BSP_MBAR);
+usb_regs_t *g_usb_regs = (void *) MCF5272_USB_BASE(BSP_MBAR);
+
+#define m68k_set_cacr( _cacr ) \
+ asm volatile ( "movec %0,%%cacr\n\t" \
+ "nop\n" \
+ : : "d" (_cacr) )
+
+#define m68k_set_acr0( _acr0 ) \
+ asm volatile ( "movec %0,%%acr0\n\t" \
+ "nop\n\t" \
+ : : "d" (_acr0) )
+
+#define m68k_set_acr1( _acr1 ) \
+ asm volatile ( "movec %0,%%acr1\n\t" \
+ "nop\n\t" \
+ : : "d" (_acr1) )
+
+#define m68k_set_srambar( _rambar0 ) \
+ asm volatile ( "movec %0,%%rambar0\n\t" \
+ "nop\n\t" \
+ : : "d" (_rambar0) )
+
+#define m68k_set_mbar( _mbar ) \
+ asm volatile ( "movec %0,%%mbar\n\t" \
+ "nop\n\t" \
+ : : "d" (_mbar) )
+
+#define mcf5272_enable_cache() \
+ m68k_set_cacr( MCF5272_CACR_CENB )
+
+
+#define mcf5272_disable_cache() \
+ asm volatile ( "nop\n\t" \
+ "movec %0,%%cacr\n\t" \
+ "nop\n\t" \
+ "movec %0,%%cacr\n\t" \
+ "nop\n\t" \
+ : : "d" (MCF5272_CACR_CINV) )
+
+/* init5272 --
+ * Initialize MCF5272 on-chip modules
+ *
+ * PARAMETERS:
+ * none
+ *
+ * RETURNS:
+ * none
+ */
+void
+init5272(void)
+{
+ extern void clear_bss(void);
+ extern void start_csb360(void);
+ int i;
+
+ /* Invalidate the cache - WARNING: It won't complete for 64 clocks */
+ m68k_set_cacr(MCF5272_CACR_CINV);
+
+ /* Set Module Base Address register */
+ m68k_set_mbar((BSP_MBAR & MCF5272_MBAR_BA) | MCF5272_MBAR_V);
+
+ /* Set RAM Base Address register */
+ m68k_set_srambar((BSP_RAMBAR & MCF5272_RAMBAR_BA) | MCF5272_RAMBAR_V);
+
+ /* Set System Control Register:
+ * Enet has highest priority, 16384 bus cycles before timeout
+ */
+ g_sim_regs->scr = (MCF5272_SCR_HWR_16384);
+
+ /* System Protection Register:
+ * Enable Hardware watchdog timer.
+ */
+ g_sim_regs->spr = MCF5272_SPR_HWTEN;
+
+ /* Clear and mask all interrupts */
+ g_intctrl_regs->icr1 = 0x88888888;
+ g_intctrl_regs->icr2 = 0x88888888;
+ g_intctrl_regs->icr3 = 0x88888888;
+ g_intctrl_regs->icr4 = 0x88880000;
+
+ /* Copy the interrupt vector table to SRAM */
+ {
+ extern void INTERRUPT_VECTOR();
+ rtems_unsigned32 *inttab = (rtems_unsigned32 *)&INTERRUPT_VECTOR;
+ rtems_unsigned32 *intvec = (rtems_unsigned32 *)BSP_RAMBAR;
+ register int i;
+ for (i = 0; i < 256; i++)
+ {
+ *(intvec++) = *(inttab++);
+ }
+ }
+ m68k_set_vbr(BSP_RAMBAR);
+
+
+ /*
+ * Setup ACRs so that if cache turned on, periphal accesses
+ * are not messed up. (Non-cacheable, serialized)
+ */
+
+ m68k_set_acr0(MCF5272_ACR_BASE(BSP_MEM_ADDR_SDRAM) |
+ MCF5272_ACR_MASK(BSP_MEM_MASK_SDRAM) |
+ MCF5272_ACR_EN |
+ MCF5272_ACR_SM_ANY);
+
+/*
+ m68k_set_acr1 (MCF5206E_ACR_BASE(BSP_MEM_ADDR_FLASH) |
+ MCF5206E_ACR_MASK(BSP_MEM_MASK_FLASH) |
+ MCF5206E_ACR_EN |
+ MCF5206E_ACR_SM_ANY);
+*/
+
+ /* Enable the caches */
+ m68k_set_cacr(MCF5272_CACR_CENB |
+ MCF5272_CACR_DCM); /* Default is not cached */
+
+ /*
+ * Copy data, clear BSS, switch stacks and call boot_card()
+ */
+/*
+ CopyDataClearBSSAndStart(BSP_MEM_SIZE_ESRAM - 0x400);
+*/
+ clear_bss();
+ start_csb360();
+
+}
diff --git a/c/src/lib/libbsp/m68k/csb360/startup/linkcmds b/c/src/lib/libbsp/m68k/csb360/startup/linkcmds
new file mode 100644
index 0000000000..2ff43f115a
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/csb360/startup/linkcmds
@@ -0,0 +1,149 @@
+/*
+ * This file contains GNU linker directives for the Cogent
+ * CSB360 development board.
+ *
+ * Copyright (C) 2004 Cogent Computer Systems
+ * Author: Jay Monkman <jtm@lopingdog.com>
+ *
+ * linkcmds,v 1.4 2003/01/20 20:19:50 joel Exp
+ */
+
+/*
+ * Declare size of heap.
+ * A heap size of 0 means "Use all available memory for the heap".
+ * Initial stack located in on-chip SRAM and not declared there.
+ */
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 31M;
+
+/* This is needed for _CPU_ISR_install_vector -
+* WARNING: it MUST match BSP_RAMBAR !!!!!!!!!!! */
+_VBR = 0x20000000;
+
+/*
+ * Setup the memory map of the CSB360 board
+ *
+ * The "ram" section is placed in RAM after the space used by umon.
+ *
+ */
+MEMORY
+{
+ ram : ORIGIN = 0x00100000, LENGTH = 31M
+}
+
+SECTIONS
+{
+
+ /*
+ * Text, data and bss segments
+ */
+ .text :
+ {
+ _RamBase = .;
+ __RamBase = .;
+ CREATE_OBJECT_SYMBOLS
+ *(.text)
+
+ /*
+ * C++ constructors/destructors
+ */
+ *(.gnu.linkonce.t.*)
+
+ /*
+ * Initialization and finalization code.
+ */
+ . = ALIGN (16);
+ PROVIDE (_init = .);
+ *crti.o(.init)
+ *(.init)
+ *crtn.o(.init)
+ . = ALIGN (16);
+ PROVIDE (_fini = .);
+ *crti.o(.fini)
+ *(.fini)
+ *crtn.o(.fini)
+
+ /*
+ * Special FreeBSD sysctl sections.
+ */
+ . = ALIGN (16);
+ __start_set_sysctl_set = .;
+ *(set_sysctl_*);
+ __stop_set_sysctl_set = ABSOLUTE(.);
+ *(set_domain_*);
+ *(set_pseudo_*);
+
+ /*
+ * C++ constructors/destructors
+ */
+ . = ALIGN (16);
+ *crtbegin.o(.ctors)
+ *(.ctors)
+ *crtend.o(.ctors)
+ *crtbegin.o(.dtors)
+ *(.dtors)
+ *crtend.o(.dtors)
+
+ /*
+ * Exception frame info
+ */
+ . = ALIGN (16);
+ *(.eh_frame)
+
+ /*
+ * Read-only data
+ */
+ . = ALIGN (16);
+ _rodata_start = .;
+ *(.rodata*)
+ *(.gnu.linkonce.r*)
+
+ . = ALIGN (16);
+ PROVIDE (etext = .);
+
+ } > ram
+
+ .data :
+ {
+ copy_start = .;
+ *(.shdata)
+ . = ALIGN (0x10);
+ *(.data)
+ . = ALIGN (0x10);
+ *(.gcc_exc)
+ *(.gcc_except_table)
+ *(.jcr)
+ . = ALIGN (0x10);
+ *(.gnu.linkonce.d*)
+ . = ALIGN (0x10);
+ _edata = .;
+ copy_end = .;
+ } > ram
+
+ .bss :
+ {
+ clear_start = . ;
+ *(.shbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(0x10);
+ _end = .;
+
+ clear_end = .;
+
+ _WorkspaceBase = .;
+ __WorkspaceBase = .;
+
+ } > ram
+
+ .stab 0 (NOLOAD) :
+ {
+ *(.stab)
+ }
+
+ .stabstr 0 (NOLOAD) :
+ {
+ *(.stabstr)
+ }
+
+}
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