diff options
Diffstat (limited to 'c/src/lib/libbsp/i960/rxgen960/startup')
48 files changed, 4614 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/Makefile.in b/c/src/lib/libbsp/i960/rxgen960/startup/Makefile.in new file mode 100644 index 0000000000..c55bc8b4e8 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/Makefile.in @@ -0,0 +1,82 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@:@srcdir@/../../../shared +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGM=${ARCH}/startup.rel +IPGM=${ARCH}/startup.indv + + +# C source names, if any, go here -- minus the .c +# OLD:C_PIECES=bspclean bsplibc bsppost bspstart main sbrk setvec +# we assume to get the following sources from bsplib/shared +C_PIECES=bspstart bsppost bspclean bsplibc main sbrk setvec kkprintf frmstr nmi XtInt +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +# C individual source names, if any, go here -- minus the .c +CI_PIECES=cntrltbl flttbl intrtbl prcb sctns fault nulsystbl systbl rom_cntrltbl rom_prcb rom_ibr +CI_FILES=$(CI_PIECES:%=%.c) +CI_O_FILES=$(CI_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .s +S_PIECES= +S_FILES=$(S_PIECES:%=%.s) +S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) + +# Assembly individual source names, if any, go here -- minus the .s +SI_PIECES=rxgen_romld asmfault asmstub ihandler +SI_FILES=$(SI_PIECES:%=%.s) +SI_O_FILES=$(SI_FILES:%.s=${ARCH}/%.o) + +SRCS=$(C_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(S_O_FILES) + +ISRCS=$(CI_FILES) $(H_FILES) $(SI_FILES) +IOBJS=$(CI_O_FILES) $(SI_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +${IPGM}: ${ISRCS} ${IOBJS} + touch ${IPGM} + +all: ${ARCH} $(SRCS) $(PGM) $(ISRCS) $(IPGM) + $(INSTALL) $(srcdir)/linkcmds ${PROJECT_RELEASE}/lib + i960-rtems-strip --strip-debug ${ARCH}/rom_ibr.o + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all + + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/asmfault.h b/c/src/lib/libbsp/i960/rxgen960/startup/asmfault.h new file mode 100644 index 0000000000..1cb6c601af --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/asmfault.h @@ -0,0 +1,16 @@ +/*-------------------------------------*/ +/* asmfault.h */ +/* Last change : 3.11.94 */ +/*-------------------------------------*/ +#ifndef _ASMFAULT_H_ +#define _ASMFAULT_H_ + + /* Fault handler start point. + */ +extern void faultHndlEntry(void); + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/asmfault.s b/c/src/lib/libbsp/i960/rxgen960/startup/asmfault.s new file mode 100644 index 0000000000..666f09e967 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/asmfault.s @@ -0,0 +1,44 @@ +/* + * asmfault.s + * Last change : 31. 1.95 + */ + + .text + .globl _faultHndlEntry + + .text + +_faultHndlEntry : + /* Raise priority. */ + ldconst 0x1F0000, r4 + ldconst 0xFFFFFFFF, r5 + modpc r4, r4, r5 + /* Where to keep state of the faulted code. */ + ldconst _faultBuffer, r3 + /* Save global registers. */ + stq g0, 64+0(r3) + stq g4, 64+16(r3) + stq g8, 64+32(r3) + stt g12, 64+48(r3) + /* Faulted code's fp (g15) is our pfp. */ + st pfp, 64+60(r3) + /* Make sure locals are in stack. */ + flushreg + /* g3 = & previosFrame[0] */ + andnot 0xF, pfp, g3 + /* Save local registers of faulted procedure. */ + ldq 0(g3), r4 + stq r4, 0(r3) + ldq 16(g3), r4 + stq r4, 16(r3) + ldq 32(g3), r4 + stq r4, 32(r3) + ldq 48(g3), r4 + stq r4, 48(r3) + /* To handling. */ + mov fp, g0 + mov r3, g1 + callx _faultTblHandler + /* This point will never be reached ... */ + +/* End of file */ diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/asmstub.h b/c/src/lib/libbsp/i960/rxgen960/startup/asmstub.h new file mode 100644 index 0000000000..bd7147c015 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/asmstub.h @@ -0,0 +1,34 @@ +/*-------------------------------------*/ +/* asmstub.h */ +/* Last change : 20. 1.95 */ +/*-------------------------------------*/ +#ifndef _ASMSTUB_H_ +#define _ASMSTUB_H_ + +#include "prcb.h" + + /* Reset Processor taking Start Point and Prcb + * as parameters. + */ +extern void asm_exit(void (* start)(void), struct PRCB * prcb); + /* Call SYSCTL instruction. + */ +extern void asm_sysctl(unsigned int cmd, unsigned int a1, unsigned int a2); + /* Alter a bit in the interrupt pending register. + */ +extern void asm_ipend(unsigned int iNmbr, unsigned int toSet); + /* Alter a bit in the interrupt mask register. + */ +extern void asm_imask(unsigned int iNmbr, unsigned int toSet); + /* Call MODPC instruction. + */ +extern int asm_modpc(unsigned int val, unsigned int mask); + /* Change a cached interrupt vector. + */ +extern void asm_ivector(unsigned int vctr, void (* hndl)(void)); + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/asmstub.s b/c/src/lib/libbsp/i960/rxgen960/startup/asmstub.s new file mode 100644 index 0000000000..3e499a70c6 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/asmstub.s @@ -0,0 +1,141 @@ +####################################### +# asmstub.s # +# Last change : 20. 1.95 # +####################################### + +######################################################################## +# +# PURPOSE: resets processor +# +# ARGUMENTS: g0 = start point +# g1 = prcb +# +# RETURNS: none +######################################################################## + + .text + .globl _asm_exit + + .text +_asm_exit: + ldconst 0x300, g2 +# ldconst _start, g1 +# ldconst _ram_prcb, g2 + sysctl g2, g0, g1 + ret + +######################################################################## +# +# PURPOSE: execute sysctl instruction +# +# ARGUMENTS: g0 = message type (0x300 for reinitialize) +# g1 = depends on type (inst addr for reinitialize) +# g2 = depends on type (prcb addr for reinitialize) +# +# RETURNS: none +######################################################################## + + .text + .globl _asm_sysctl + + .text +_asm_sysctl: + b _asm_sysctl + sysctl g0, g1, g2 + ret + +######################################################################## +# +# PURPOSE: alter a bit in the interrupt pending register +# +# ARGUMENTS: g0 = interrupt number +# g1 = 1 to set, 0 to clear +# +# RETURNS: none +######################################################################## + + .text + .globl _asm_ipend + + .text +_asm_ipend: + chkbit 0, g1 + alterbit g0, sf0, sf0 + ret +######################################################################## +# +# PURPOSE: alter a bit in the interrupt mask register +# +# ARGUMENTS: g0 = interrupt number +# g1 = 1 to set, 0 to clear +# +# RETURNS: none +######################################################################## + + .text + .globl _asm_imask + + .text +_asm_imask: + chkbit 0, g1 + alterbit g0, sf1, sf1 + ret + + +######################################################################## +# +# PURPOSE: get the value of the interrupt mask register +# +# ARGUMENTS: none +# +# RETURNS: value of IMASK reg +######################################################################## + + .text + .globl _asm_get_imask + + .text +_asm_get_imask: + mov sf1, g0 + ret + +######################################################################## +# +# PURPOSE: modify process-controls register +# +# ARGUMENTS: g0 = value masked/stored in PC reg +# g1 = mask of bits to be modified +# +# RETURNS: g0 = initial value of PC reg +######################################################################## + + .text + .globl _asm_modpc + + .text +_asm_modpc: + modpc g1, g1, g0 + ret + +######################################################################## +# +# PURPOSE: change a cached interrupt vector +# +# ARGUMENTS: g0 = interrupt number +# g1 = new interrupt vector +# +# RETURNS: none +######################################################################## + + .text + .globl _asm_ivector + + .text +_asm_ivector: + addo 1, g0, g0 + st g1, [g0 * 4] + ret + +############### +# End of file # +############### diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/bspstart.c b/c/src/lib/libbsp/i960/rxgen960/startup/bspstart.c new file mode 100644 index 0000000000..00f2b009dc --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/bspstart.c @@ -0,0 +1,180 @@ +/* bsp_start() + * + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <bsp.h> +#include <rtems/libio.h> + +#include <libcsupport.h> + +#include <string.h> +#include <fcntl.h> +#include <stdio.h> +#include "i960RP.h" +#include <rtems/libio.h> + +#ifdef STACK_CHECKER_ON +#include <stackchk.h> +#endif + +#define HEAP_SIZE 1024*1024*2 + +/* + * The original table from the application and our copy of it with + * some changes. + */ + +extern int putnum(unsigned int); + +extern rtems_configuration_table Configuration; +extern void bsp_postdriver_hook(void); /* defined in shared directory */ + +rtems_configuration_table BSP_Configuration; + +rtems_cpu_table Cpu_table; + +char *rtems_progname; +unsigned int top_of_used_memory; + +/* + * Function: bsp_pretasking_hook + * Created: 95/03/10 + * + * Description: + * BSP pretasking hook. Called just before drivers are initialized. + * Used to setup libc and install any BSP extensions. + * + * NOTES: + * Must not use libc (to do io) from here, since drivers are + * not yet initialized. + * + */ + +void +bsp_pretasking_hook(void) +{ + + extern int end; + rtems_unsigned32 heap_start; + +*(unsigned char *)(0x120f) = 0xd; +/* heap_start = (rtems_unsigned32) &end; */ + heap_start = (rtems_unsigned32) top_of_used_memory; + if (heap_start & (CPU_ALIGNMENT-1)) + heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); + + bsp_libc_init((void *) heap_start, 64 * 1024, 0); + + +#ifdef STACK_CHECKER_ON + /* + * Initialize the stack bounds checker + * We can either turn it on here or from the app. + */ + +*(unsigned char *)(0x120f) = 0xe; + Stack_check_Initialize(); +#endif + +#ifdef RTEMS_DEBUG + rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); +#endif +*(unsigned char *)(0x120f) = 0xf; +} + + +/* we need to have the top of memory remembered later to start libc_init with + the correct values +*/ +int rx_boot_card( int argc, char **argv, char **environp) +{ + extern int end; + top_of_used_memory = (rtems_unsigned32) &end + 0x1000; + if ((argc > 0) && argv && argv[0]) + rtems_progname = argv[0]; + else + rtems_progname = "RTEMS/RP"; + + boot_card(argc, argv); + +} + +bsp_start(void) +{ + + *(unsigned int *)OIMR_ADDR = 0xff; /* Mask all primary PCI Interrupts*/ + Prcb = get_prcb(); + Ctl_tbl = Prcb->control_tbl; + +*(unsigned char *)(0x120f) = 8; + /* + * we do not use the pretasking_hook. + */ + + Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ + Cpu_table.postdriver_hook = bsp_postdriver_hook; + Cpu_table.do_zero_of_workspace = TRUE; + Cpu_table.interrupt_stack_size = 8192; + Cpu_table.extra_mpci_receive_server_stack = 0; + Cpu_table.Prcb = Prcb; + + /* just trying to get along */ + Cpu_table.stack_allocate_hook = 0; + Cpu_table.stack_free_hook = 0; + + /* + * Add 1 region for the RTEMS Malloc + */ + + BSP_Configuration.RTEMS_api_configuration->maximum_regions++; + + /* + * Add 1 extension for newlib libc + */ + +#ifdef RTEMS_NEWLIB + BSP_Configuration.maximum_extensions++; +#endif + + /* + * Add another extension if using the stack checker + */ + +#ifdef STACK_CHECKER_ON + BSP_Configuration.maximum_extensions++; +#endif + + + /* + * Tell libio how many fd's we want and allow it to tweak config + */ + +*(unsigned char *)(0x120f) = 0x09; + + BSP_Configuration.work_space_start = (void *) top_of_used_memory; + top_of_used_memory += (BSP_Configuration.work_space_size + 0x1000); + + +*(unsigned char *)(0x120f) = 0x0a; + + return 0; +} + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.c b/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.c new file mode 100644 index 0000000000..8bbe2d773d --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.c @@ -0,0 +1,85 @@ +/*-------------------------------------*/ +/* cntrltbl.c */ +/* Last change : 7.10.94 */ +/*-------------------------------------*/ +#include "i960RP.h" +#include "cntrltbl.h" +/*-------------------------------------*/ + /* Control Table. + */ + /* Interrupt Map Registers Initial. + */ +#define IMAP0 0x4321 +#define IMAP1 0x8765 +#define IMAP2 0xA90000 +#define ICON (VECTOR_CACHE | MSK_UNCHNG | I_ENABLE) + + +/* Bus configuration */ +#define RP_CONFIG_REGS BUS_WIDTH_32 +#define FLASH BUS_WIDTH_8 +#define DRAM BUS_WIDTH_32 +#define UART_LED BUS_WIDTH_8 +#define DEFAULT BUS_WIDTH_32 + +/* Region Configuration */ +#define REGION_0_CONFIG RP_CONFIG_REGS +#define REGION_2_CONFIG DEFAULT +#define REGION_4_CONFIG DEFAULT +#define REGION_6_CONFIG DEFAULT +#define REGION_8_CONFIG DEFAULT +#define REGION_A_CONFIG DRAM +#define REGION_C_CONFIG UART_LED + +#define REGION_E_CONFIG DEFAULT +#define REGION_BOOT_CONFIG DRAM + + /* Trace Control Initial. */ +#define TC 0 + +/*Bus Control Initial value */ +#define BCON CONF_TBL_VALID + + + +ControlTblEntry controlTbl[] = { + /* --group 0 -- */ + 0, + 0, + 0, + 0, + /* --group 1 -- */ + IMAP0, + IMAP1, + IMAP2, + ICON, + /* --group 2 -- */ + REGION_0_CONFIG, + 0, + REGION_2_CONFIG, + 0, + /* --group 3 -- */ + REGION_4_CONFIG, + 0, + REGION_6_CONFIG, + 0, + /* --group 4 -- */ + REGION_8_CONFIG, + 0, + REGION_A_CONFIG, + 0, + /* --group 5 -- */ + REGION_C_CONFIG, + 0, + REGION_BOOT_CONFIG, + 0, + /* --group 6 -- */ + 0, /* Reserved */ + 0, + TC, + BCON +}; +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.h b/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.h new file mode 100644 index 0000000000..aafca23b03 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.h @@ -0,0 +1,48 @@ +/*-------------------------------------*/ +/* cntrltbl.h */ +/* Last change : 11. 1.95 */ +/*-------------------------------------*/ +#ifndef _CNTRLTBL_H_ +#define _CNTRLTBL_H_ + + /* Control Table Entry. + */ +typedef unsigned int ControlTblEntry; + /* Control Table itself. + */ +extern ControlTblEntry controlTbl[]; +extern ControlTblEntry rom_controlTbl[]; + + /* Interrupt Registers Initial. + */ +#define IPB0 0 +#define IPB1 0 +#define DAB0 0 +#define DAB1 0 + +#define I_DISABLE (0x1<<10) +#define I_ENABLE 0 + +#define MSK_UNCHNG 0 +#define MSK_CLEAR (0x1<<11) + +#define VECTOR_CACHE (0x1<<13) + + + + /* BreakPoint Control Register Initial. + */ +#define BPCON 0 + /* Bus Controller Mode Comstants. + */ +#define CONF_TBL_VALID 0x1 +#define PROTECT_RAM 0x2 +#define PROTECT_RAM_SUP 0x4 + + + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/dram.ld b/c/src/lib/libbsp/i960/rxgen960/startup/dram.ld new file mode 100644 index 0000000000..f0161bd062 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/dram.ld @@ -0,0 +1,150 @@ +/*------------------------------------*/ +/* rom.ld */ +/* Last change : 19. 4.95 */ +/*------------------------------------* + * To build ROM based i960 image. + *------------------------------------*/ + + +MEMORY +{ + dram : org = 0xa2000000, len = 120K +} + + +_bootAddr = 0xa0200000; +_HEAP = 0xA0100000 ; + +SECTIONS +{ + /* Only monitor start point and fault handler + * will live in ROM as far as text is concerned. + * Only fault table will live in ROM as far as data + * is concerned. + */ + romCode : + { + /* Make sure that the monitor start point + * is the first location in EPROM. + */ + rommon.o960(.text) + /* Procedures to copy code and + * initialize bss in RAM. + */ + sctns.o960(.text) + /* Make Sure Fault Table (and its handler's data) + * live here so that they wouldn't get destroyed). + */ + asmfault.o960 + flttbl.o960 + /* 16 byte aligned PRCB. + */ + . = ALIGN(16); + rom_prcb.o960(.data) + /* 16 byte aligned Control Table. + */ + . = ALIGN(16); + rom_cntrltbl.o960(.data) + . = ALIGN(16); + intrtbl.o960(.data) + . = ALIGN(16); + nulsystbl.o960(.data) + . = ALIGN(16); + /* I need this symbol to know where code which is + * to be copied reside in ROM. Align it on a 16 + * boundary. + */ + . = ALIGN(16); + _codeRomStart = .; + } > dram + + /* All the rest of the code will live in RAM. + * Relocation are created as though code resides + * in RAM, while code is placed right after romCode. + * This is responsiblity of the ROM monitor to + * copy code into ROM. + */ + ramCode : AT(ADDR(romCode) + SIZEOF(romCode)) + { + /* RAM-based code section start. + * I need this symbol to know where to copy code + * at initialization time . + */ + _codeRamStart = .; + /* RAM based fault recovery stuff. + */ + _faultStart = .; + fault.o960 + _faultEnd = .; + /* Check sum to gurantee that + * the above section wasn't broken. + */ + . = ALIGN(16); + _faultCheckSum = .; + . += 4; + /* Fault Buffer to keep the state of + * the fauled procedure. + */ + _faultBuffer = .; + . += 256; + /* All the rest of the text goes here. + */ + . = ALIGN(16); + *(.text) + /* 16 byte aligned PRCB. + */ + . = ALIGN(16); + prcb.o960(.data) + /* 16 byte aligned Control Table. + */ + . = ALIGN(16); + cntrltbl.o960(.data) + . = ALIGN(16); + systbl.o960(.data) + /* All the rest of program defined data goes here. + */ + *(.data) + /* RAM-based code section end. + * I need this symbol to know where to copy code + * at initialization time . + */ + _codeRamEnd = .; + } > sram + + /* RAM based uninitialized data. + */ + bss (NOLOAD) : + { + /* BSS section start. I need this symbol to + * zero BSS on initialization. + */ + _bssStart = .; + /* Supervisor Stack. Aligned on a 16 boundary. + */ + . = ALIGN(16); + _svrStackPtr = .; + . += 4K; + /* Interrupt Stack. Aligned on a 16 boundary. + */ + . = ALIGN(16); + _intStackPtr = .; + . += 4K; + /* Program defined BSS. + */ + *(.bss) + /* Program defined COMMON. + */ + *(COMMON) + /* BSS section end. I need this symbol to + * zero BSS on initialization. + */ + _bssEnd = .; + _bssStart_1 = .; + _bssEnd_1 = .; + } > dram + +} + +/*-------------*/ +/* End of file */ +/*-------------*/ diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/exit.c b/c/src/lib/libbsp/i960/rxgen960/startup/exit.c new file mode 100644 index 0000000000..12aa1ab480 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/exit.c @@ -0,0 +1,38 @@ +/* exit + * + * This routine is used to return control to the NINDY monitor + * and is automatically invoked by the STDIO exit() routine. + * + * INPUT: + * status - exit status + * + * OUTPUT: NONE + * + * NOTES: DOES NOT RETURN!!! + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <rtems.h> +#include "bsp.h" + +void _exit( ) +{ + asm volatile( "mov 0,g0; \ + fmark ; \ + syncf ; \ + .word 0xfeedface ; \ + bx start" : : ); + /* The constant 0xfeedface is a magic word for break which + * is defined by NINDY. The branch extended restarts the + * application if the user types "go". + */ +} diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/fault.c b/c/src/lib/libbsp/i960/rxgen960/startup/fault.c new file mode 100644 index 0000000000..02373c3260 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/fault.c @@ -0,0 +1,322 @@ +/*-------------------------------------*/ +/* fault.c */ +/* Last change : 13. 7.95 */ +/*-------------------------------------*/ +#include "prcb.h" +#include "i960.h" +#include "flttbl.h" +#include "fault.h" +#include "asmstub.h" +#include <stdio.h> +#include <string.h> + +extern void romFaultStart(void); + +/*-------------------------------------*/ + /* Table of user-registered fault handler entry. + */ +typedef struct { + UserFaultHandler hndl; /* Handler itself. */ + int cnt; /* Handler is valid for cnt times. */ +} UserFaultEntry; + /* Table itself. + */ +static UserFaultEntry userFaultTable[] = { + {0, 0}, /* Parallel */ + {0, 0}, /* Trace */ + {0, 0}, /* Operation */ + {0, 0}, /* Arithmetic */ + {0, 0}, /* Reserved */ + {0, 0}, /* Constraint */ + {0, 0}, /* Reserved */ + {0, 0}, /* Protection */ + {0, 0}, /* Reserved */ + {0, 0} /* Type */ +}; + /* Number of Faults. + */ +#define FaultNmbr (sizeof(userFaultTable)/sizeof(UserFaultEntry)) + +int faultRegister(int fault, UserFaultHandler hndl, int cnt) +{ + static unsigned int faultNewCheckSum(void); + int rsl = 0; + + if (0 <= fault && fault <= FaultNmbr) { + /* Register handler. + */ + userFaultTable[fault].hndl = hndl; + userFaultTable[fault].cnt = cnt; + /* Checksum has changed. + */ + faultCheckSum = faultNewCheckSum(); + rsl = 1; + } + return rsl; +} +int faultOk(int fault) +{ + static unsigned int faultNewCheckSum(void); + int rsl = 0; + + if (0 <= fault && fault <= FaultNmbr) { + /* Fault handler recovered successfully. + * Can use it at least once more. + */ + userFaultTable[fault].cnt ++; + /* Check sum has changed. + */ +#ifdef 0 + faultCheckSum = faultNewCheckSum(); +#endif + faultCheckSum ++; + rsl = 1; + } + return rsl; +} +void faultBad(int invokedFromRom, + unsigned int inst, unsigned int * faultBuffer, + unsigned int type, unsigned int sbtp) +{ + static void faultInfo(int invokedFromRom, + unsigned int inst, unsigned int * faultBuffer, + unsigned int type, unsigned int sbtp); + + /* Close the mem channel nicely. + */ +/* memChnlI960Fault();*/ + /* Give some panic message. + */ + faultInfo(invokedFromRom, inst, faultBuffer, type, sbtp); + /* At this point RAM is repaired. Do + * whatever you want. + */ +# ifdef 0 + if (OsfIsUp) { + asm_exit(romFaultStart, & ram_prcb); + } + else { + asm_exit(romStart, & ram_prcb); + } +# endif + asm_exit(romFaultStart, & ram_prcb); +} +void faultGood(unsigned int inst, unsigned int * faultBuffer, + unsigned int type, unsigned int sbtp) +{ + static unsigned int faultNewCheckSum(void); + + if (userFaultTable[type].hndl != 0 && userFaultTable[type].cnt > 0) { + /* This is done to avoid the situation when + * handler causes a fault and, thus, infinite recursion. + */ + userFaultTable[type].cnt --; + /* Check sum has changed. + */ +#ifdef 0 + faultCheckSum = faultNewCheckSum(); +#endif + faultCheckSum --; + /* Invoke handler. + */ + (* userFaultTable[type].hndl)(inst, faultBuffer, type, sbtp); + /* If this returns => fault is bad. + */ + } + faultBad(0, inst, faultBuffer, type, sbtp); +} +static unsigned int faultNewCheckSum(void) +{ + unsigned int * f = faultStart; + unsigned int * l = faultEnd; + unsigned int sum; + + for (sum = 0; f < l; f ++) { + sum += * f; + } + return sum; +} +static void faultInfo(int invokedFromRom, + unsigned int inst, unsigned int * faultBuffer, + unsigned int type, unsigned int sbtp) +{ + char * typeStr; + char * sbtpStr; + static char * faultParallelSbtpStr(unsigned int); + static char * faultTraceSbtpStr(unsigned int); + static char * faultOperationSbtpStr(unsigned int); + static char * faultArithmeticSbtpStr(unsigned int); + static char * faultReservedSbtpStr(unsigned int); + static char * faultConstraintSbtpStr(unsigned int); + static char * faultProtectionSbtpStr(unsigned int); + static char * faultTypeSbtpStr(unsigned int); + static char * faultUnknownSbtpStr(unsigned int); + static struct { + char * name; + char * (* sbtpStr)(unsigned int); + } faultInfo[] = { + {"Parallel", faultParallelSbtpStr}, + {"Trace", faultTraceSbtpStr}, + {"Operation", faultOperationSbtpStr}, + {"Arithmetic", faultArithmeticSbtpStr}, + {"Reserved", faultReservedSbtpStr}, + {"Constraint", faultConstraintSbtpStr}, + {"Reserved", faultReservedSbtpStr}, + {"Protection", faultProtectionSbtpStr}, + {"Reserved", faultReservedSbtpStr}, + {"Type", faultTypeSbtpStr}, + {"Unknown", faultUnknownSbtpStr} + }; + unsigned int ix; + +/* console_set_channel(CHANNEL_B);*/ + ix = type >= FaultNmbr ? FaultNmbr : type; + typeStr = faultInfo[ix].name; + sbtpStr = (* faultInfo[ix].sbtpStr)(sbtp); + printf("\nFault at 0x%08x: %s[%s]\n", + faultBuffer[IP_REGNUM], typeStr, sbtpStr); + printf("Bad instruction: 0x%08x\n", inst); + printf("AC=0x%08x PC=0x%08x\n", + faultBuffer[ACW_REGNUM], + faultBuffer[PCW_REGNUM]); + printf("g0=0x%08x g1=0x%08x g2=0x%08x g3=0x%08x\n", + faultBuffer[G0_REGNUM+0], faultBuffer[G0_REGNUM+1], + faultBuffer[G0_REGNUM+2], faultBuffer[G0_REGNUM+3]); + printf("g4=0x%08x g5=0x%08x g6=0x%08x g7=0x%08x\n", + faultBuffer[G0_REGNUM+4], faultBuffer[G0_REGNUM+5], + faultBuffer[G0_REGNUM+6], faultBuffer[G0_REGNUM+7]); + printf("g8=0x%08x g9=0x%08x gA=0x%08x gB=0x%08x\n", + faultBuffer[G0_REGNUM+8], faultBuffer[G0_REGNUM+9], + faultBuffer[G0_REGNUM+10], faultBuffer[G0_REGNUM+11]); + printf("gC=0x%08x gD=0x%08x gE=0x%08x gF=0x%08x\n", + faultBuffer[G0_REGNUM+12], faultBuffer[G0_REGNUM+13], + faultBuffer[G0_REGNUM+14], faultBuffer[G0_REGNUM+15]); + printf("r0=0x%08x r1=0x%08x r2=0x%08x r3=0x%08x\n", + faultBuffer[R0_REGNUM+0], faultBuffer[R0_REGNUM+1], + faultBuffer[R0_REGNUM+2], faultBuffer[R0_REGNUM+3]); + printf("r4=0x%08x r5=0x%08x r6=0x%08x r7=0x%08x\n", + faultBuffer[R0_REGNUM+4], faultBuffer[R0_REGNUM+5], + faultBuffer[R0_REGNUM+6], faultBuffer[R0_REGNUM+7]); + printf("r8=0x%08x r9=0x%08x rA=0x%08x rB=0x%08x\n", + faultBuffer[R0_REGNUM+8], faultBuffer[R0_REGNUM+9], + faultBuffer[R0_REGNUM+10], faultBuffer[R0_REGNUM+11]); + printf("rC=0x%08x rD=0x%08x rE=0x%08x rF=0x%08x\n", + faultBuffer[R0_REGNUM+12], faultBuffer[R0_REGNUM+13], + faultBuffer[R0_REGNUM+14], faultBuffer[R0_REGNUM+15]); + if (invokedFromRom) { + printf("RAM image damaged. No chance to recover\n"); + } + else { + printf("RAM image not damaged. Still no recovery\n"); + } +} +static char * faultParallelSbtpStr(unsigned int sbtp) +{ + static char buf[10]; + + sprintf(buf, "%d", sbtp); + return buf; +} +static char * faultTraceSbtpStr(unsigned int sbtp) +{ + static char buf[256]; + int notEmpty; + + buf[0] = '\0'; + notEmpty = 0; + if (sbtp & 0x2) { + strcat(buf, "Instruction"); + notEmpty = 1; + } + if (sbtp & 0x4) { + if (notEmpty) strcat(buf, ":"); + strcat(buf, "Branch"); + notEmpty = 1; + } + if (sbtp & 0x8) { + if (notEmpty) strcat(buf, ":"); + strcat(buf, "Call"); + notEmpty = 1; + } + if (sbtp & 0x10) { + if (notEmpty) strcat(buf, ":"); + strcat(buf, "Return"); + notEmpty = 1; + } + if (sbtp & 0x20) { + if (notEmpty) strcat(buf, ":"); + strcat(buf, "Prereturn"); + notEmpty = 1; + } + if (sbtp & 0x40) { + if (notEmpty) strcat(buf, ":"); + strcat(buf, "Supervisor"); + notEmpty = 1; + } + if (sbtp & 0x80) { + if (notEmpty) strcat(buf, ":"); + strcat(buf, "Breakpoint"); + notEmpty = 1; + } + if (! notEmpty) { + strcat(buf, "Unknown"); + } + return buf; +} +static char * faultOperationSbtpStr(unsigned int sbtp) +{ + char * rsl; + + if (sbtp == 0x1) rsl = "Invalid Opcode"; + else if (sbtp == 0x2) rsl = "Unimplemented"; + else if (sbtp == 0x3) rsl = "Unaligned"; + else if (sbtp == 0x4) rsl = "Invalid Operand"; + else rsl = "Unknown"; + return rsl; +} +static char * faultArithmeticSbtpStr(unsigned int sbtp) +{ + char * rsl; + + if (sbtp == 0x1) rsl = "Integer Overflow"; + else if (sbtp == 0x2) rsl = "Arithmetic Zero-Divide"; + else rsl = "Unknown"; + return rsl; +} +static char * faultReservedSbtpStr(unsigned int sbtp) +{ + return "Unknown"; +} +static char * faultConstraintSbtpStr(unsigned int sbtp) +{ + char * rsl; + + if (sbtp == 0x1) rsl = "Constraint Range"; + else if (sbtp == 0x2) rsl = "Priveleged"; + else rsl = "Unknown"; + return rsl; +} +static char * faultProtectionSbtpStr(unsigned int sbtp) +{ + char * rsl; + + if (sbtp == 0x1) rsl = "Length"; + else rsl = "Unknown"; + return rsl; +} +static char * faultTypeSbtpStr(unsigned int sbtp) +{ + char * rsl; + + if (sbtp == 0x1) rsl = "Type Mismatch"; + else rsl = "Unknown"; + return rsl; +} +static char * faultUnknownSbtpStr(unsigned int sbtp) +{ + return "Unknown"; +} +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/fault.h b/c/src/lib/libbsp/i960/rxgen960/startup/fault.h new file mode 100644 index 0000000000..b068fdde1d --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/fault.h @@ -0,0 +1,54 @@ +/*-------------------------------------*/ +/* fault.h */ +/* Last change : 2.11.94 */ +/*-------------------------------------*/ +#ifndef _FAULT_H_ +#define _FAULT_H_ + + /* (RAM-based) Fault Handler. + * Is invoked when there is no chance to repair current state. + */ +extern void faultBad(int invokedFromRom, + unsigned int inst, unsigned int * faultBuffer, + unsigned int type, unsigned int sbtp); + /* (RAM-based) Fault Handler. + * Is invoked when there is a chance to repair current state. + */ +extern void faultGood(unsigned int instr, unsigned int * faultBuffer, + unsigned int type, unsigned int sbtp); + /* Some addresses that are defined in rom.ld. + */ +extern unsigned int faultCheckSum; + +extern unsigned int faultBuffer[]; + +extern unsigned int faultStart[]; +extern unsigned int faultEnd[]; + /* Interface for user to register fault handlers of his own. + * Fault names. + */ +#define ParallelFLT 0 +#define TraceFLT 1 +#define OperationFLT 2 +#define ArithmeticFLT 3 +#define ConstraintFLT 5 +#define ProtectionFLT 7 +#define TypeFLT 9 + /* User-registered fault handler. + */ +typedef void (* UserFaultHandler)(unsigned int inst, unsigned int * faultBuf, + unsigned int type, unsigned int sbtp); + /* Register user-defined fault handler. The third argument is + * how many times this fault handler will be valid. This to avoid + * the situation when handler is bad and it causes a fault itself. + */ +extern int faultRegister(int fault, UserFaultHandler, int cnt); + /* Validate handler for one more time. + */ +extern int faultOk(int fault); + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/faultret.h b/c/src/lib/libbsp/i960/rxgen960/startup/faultret.h new file mode 100644 index 0000000000..986c563b82 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/faultret.h @@ -0,0 +1,17 @@ +/*-------------------------------------*/ +/* faultret.h */ +/* Last change : 3.11.94 */ +/*-------------------------------------*/ +#ifndef _FAULTRET_H_ +#define _FAULTRET_H_ + + /* Return to the point where fault happened. + * Fault state keeps all registers. + */ +extern void faultRet(unsigned int * faultState); + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/flttbl.c b/c/src/lib/libbsp/i960/rxgen960/startup/flttbl.c new file mode 100644 index 0000000000..dc55584619 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/flttbl.c @@ -0,0 +1,117 @@ +/*-------------------------------------*/ +/* flttbl.c */ +/* Last change : 3.11.94 */ +/*-------------------------------------*/ +#include "i960.h" +#include "string.h" +#include "sctns.h" +#include "fault.h" +#include "asmfault.h" +#include "flttbl.h" +/*-------------------------------------*/ + /* Fault Table. It (as well as all the rest of the + * code of this file will always stay in ROM, so + * that it wouldn't be destroyed by silly user code. + * Thus, at least faults will be always caugth, + */ +FaultTblEntry faultTbl[] = { + {faultHndlEntry + LOCAL_FH, LOCAL_FW}, /* Parallel */ + {faultHndlEntry + LOCAL_FH, LOCAL_FW}, /* Trace */ + {faultHndlEntry + LOCAL_FH, LOCAL_FW}, /* Operation */ + {faultHndlEntry + LOCAL_FH, LOCAL_FW}, /* Arithmetic */ + {0, 0}, /* Reserved */ + {faultHndlEntry + LOCAL_FH, LOCAL_FW}, /* Constraint */ + {0, 0}, /* Reserved */ + {faultHndlEntry + LOCAL_FH, LOCAL_FW}, /* Protection */ + {0, 0}, /* Reserved */ + {faultHndlEntry + LOCAL_FH, LOCAL_FW} /* Type */ +}; + +void fltTblInit(void) +{ + static unsigned int fltTblCheckSum(void); + + faultCheckSum = fltTblCheckSum(); +} +static unsigned int fltTblCheckSum(void) +{ + unsigned int * f = faultStart; + unsigned int * l = faultEnd; + unsigned int sum; + + for (sum = 0; f < l; f ++) { + sum += * f; + } + return sum; +} +void faultTblHandler(unsigned int * fp, unsigned int * faultBuffer) +{ + unsigned int * ip; + struct typeWord { + unsigned int sbtp : 8; + unsigned int : 8; + unsigned int type : 8; + unsigned int : 8; + } tw; + unsigned int type; + unsigned int sbtp; + unsigned int ac; + unsigned int pc; + unsigned int inst; + + char nib; + unsigned int i; + + /* Address of faulting instruction. + */ + ip = (unsigned int *) fp[-1]; + /* Type/Subtype word. + */ + + /* put address of faulting instruction to console */ + kkprintf("Fault: %x\n", ip); + + tw = * (struct typeWord *) & fp[-2]; + /* Type and subtype. + */ + type = tw.type; + sbtp = tw.sbtp; + /* Arithmetic controls. + */ + ac = fp[-3]; + /* Process controls. + */ + pc = fp[-4]; + /* Global and local registers are in faultBuffer + * already. Save the rest. Change RIP to IP. + */ + faultBuffer[IP_REGNUM] = (unsigned int) ip; + faultBuffer[ACW_REGNUM] = ac; + faultBuffer[PCW_REGNUM] = pc; + /* Bad instruction itself. We do + * this here since it may be repaired (by copying from PROM). + */ + inst = * ip; + /* Now, to handling. + */ + if (faultCheckSum != fltTblCheckSum()) { + /* RAM-based fault repair stuff + * is broken. No chance to recover. + * Repair RAM memory which is + * destroyed by silly user. + */ + copyCodeToRom(); + /* And call RAM-based fault handler. + */ + faultBad(1, inst, faultBuffer, type, sbtp); + } + else { + /* There exist a chance to recover. + */ + faultGood(inst, faultBuffer, type, sbtp); + } +} +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/flttbl.h b/c/src/lib/libbsp/i960/rxgen960/startup/flttbl.h new file mode 100644 index 0000000000..2111ddb255 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/flttbl.h @@ -0,0 +1,36 @@ +/*-------------------------------------*/ +/* fltbl.h */ +/* Last change : 3.11.94 */ +/*-------------------------------------*/ +#ifndef _FLTTBL_H_ +#define _FLTTBL_H_ + + /* FaultTable Entry. + */ +typedef struct { + void (* hndl)(void); /* Fault Handle */ + unsigned int type; /* Fault Table Type */ +} FaultTblEntry; + /* Fault Handler Type. + */ +#define LOCAL_FH 0 +#define SYSTEM_FH 0x10 + +#define LOCAL_FW 0 +#define SYSTEM_FW 0x027F + /* FaultTable Itself. + */ +extern FaultTblEntry faultTbl[]; + /* To initialize fault handling. + */ +extern void faultTblInit(void); + /* Fault handler. Invoked from low-level handler. + */ +extern void faultTblHandler(unsigned int * fp, + unsigned int * faultBuffer); + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/frmstr.c b/c/src/lib/libbsp/i960/rxgen960/startup/frmstr.c new file mode 100644 index 0000000000..48c18415dd --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/frmstr.c @@ -0,0 +1,616 @@ +/*-------------------------------------*/ +/* frmstr.c */ +/* Last change : 14.10.94 */ +/*-------------------------------------*/ +#include "frmstr.h" +/*-------------------------------------*/ + /* How to treat the rest. + */ +#define FOR_CONSOLE 1 +#define DO_LONG 1 + + /* To Store a byte. + */ +#ifdef _STORE_BYTE +# define STORE_BYTE(a, b) (store_byte(a, b)) + long store_byte(void); +#else +# define STORE_BYTE(a, b) (* (a) = (b)) +#endif + /* Some decalrations. + */ +static void geta(ArgType *, int); +static const char * gnum(const char *, ArgType * ); +static char * i_compute(unsigned val, int, char *); +#ifdef DO_LONG +static char * l_compute(long, int, char *); +#endif +static ArgType * nextarg; + /* And macros. + */ +#define wsize(par) ((sizeof par) / sizeof(ArgType)) +#define signbit(par) (1L<<(sizeof par * 8 - 1)) + +int format_string(const char * fmt, ArgType * args, char * buffer) +{ + char * s; +# ifdef DO_LONG + long l; + int lflag; +# else +# define lflag 0 +# endif +# ifdef DO_FLOAT + double dbl; +# endif + ArgType inte; + ArgType_U uint; + ArgType width, ndigit; + int i, j, c, rjust, ndfnd, zfill; + const char * oldfmt; + char * s1, buf[64]; + + nextarg = args; + while (c = * fmt ++) { + if (c != '%') { +# ifdef FOR_CONSOLE + if (c == '\n') STORE_BYTE(buffer ++, '\r'); +# endif + STORE_BYTE(buffer ++, c); + continue; + } +# ifdef DO_LONG + lflag = 0 ; +# endif + j = 10 ; + rjust = 0; + if (* fmt == '-') { + fmt ++; + rjust ++; + } + zfill = ' '; + if (* fmt == '0') { + fmt ++; + zfill = '0'; + } + fmt = gnum(fmt, & width); + ndigit = 0; ndfnd = 0; + if (* fmt == '.') { + fmt ++; oldfmt = fmt; + fmt = gnum(fmt, & ndigit); + ndfnd = (int)(fmt != oldfmt); + } + s = s1 = buf; +# ifdef DO_LONG + if (* fmt == 'l' || * fmt == 'L') { + fmt ++; lflag ++; + } +# endif + switch (c = * fmt ++) { + default: +# ifdef FOR_CONSOLE + if (c == '\n') STORE_BYTE(buffer ++, '\r'); +# endif + STORE_BYTE(buffer ++, c); + continue; + case 's': + geta((ArgType *) & s1, wsize(s1)); + s = s1; + do { + if (s == 0) break; + if (* s == 0) + break; + s ++; + } while (-- ndigit); + break; + case 'b': + j = 2; + case 'u': + getu: + + if (! lflag) { + geta(& inte, wsize(inte)); + goto i_unsignd; + } +# ifdef DO_LONG + case 'U': + getlu: + + geta((ArgType *) & l, wsize(l)); + goto l_unsignd; + case 'B': + j = 2 ; + goto getlu; + case 'X': + j = 16; + goto getlu; + case 'O': + j = 8; + goto getlu ; + case 'D': + l_signed: + + geta((ArgType *) & l, wsize(l)); + if (l < 0) { + STORE_BYTE(s ++, '-'); + l = -l; + } + goto do_l; + + l_unsignd: + + if (l && ndigit) + STORE_BYTE(s ++, '0'); + + do_l: + + s = l_compute(l, j, s); + break; +# endif + case 'x': + j = 16; + goto getu; + case 'o': + j = 8; + goto getu; + case 'd': + if (lflag) goto l_signed; + geta(& inte, wsize(inte)); + if (inte < 0) { + STORE_BYTE(s ++, '-'); + inte = - inte; + } + goto do_i; + + i_unsignd: + + if (inte && ndigit) + STORE_BYTE(s ++, '0'); + + do_i: + + s = i_compute(inte, j, s); + break; + case 'c': + geta ((ArgType *) & uint, wsize(uint)); + for (i = sizeof uint - 1; i >= 0; i --) { + if (STORE_BYTE(s, uint % 256)) s ++; + uint /= 256 ; + } + break; +# ifdef DO_FLOAT + case 'e': + geta((ArgType *) & dbl, wsize(dbl)); + s = _pscien(dbl, s, ndigit, ndfnd); + break; + case 'f': + geta((ArgType *) &dbl,wsize(dbl)); + s = _pfloat(dbl, s, ndigit, ndfnd); + break; +# endif + case 'r': + geta((ArgType *) & nextarg, wsize(nextarg)); + geta((ArgType *) & oldfmt, wsize(fmt)); + fmt = oldfmt; + continue; + } + j = s - s1; + if ((c = width - j) > 0) { + if (rjust == 0) { + do STORE_BYTE(buffer ++, zfill); + while (-- c); + } + } + while (-- j >= 0) + STORE_BYTE(buffer ++, * s1 ++); + while (-- c >= 0) + STORE_BYTE(buffer ++, zfill); + } + STORE_BYTE(buffer, 0); + return 0; +} +static void geta(ArgType * p, int size) +{ + if ((ArgType *) & p - (ArgType *) & size > 0) { + p += size; + while (size --) { + * -- p = * nextarg --; + } + } + else { + while (size --) { + * p ++ = * nextarg ++ ; + } + } +} +static const char * gnum(const char * f, ArgType * ip) +{ + ArgType i; + int c; + + if (* f == '*') { + geta(ip, wsize(i)) ; + f ++; + } + else { + i = 0; + while ((c = * f - '0') >= 0 && c <= 9) { + i = i * 10 + c; + f ++; + } + * ip = i; + } + return f; +} +static char * i_compute(unsigned int val, int base, char * s) +{ + int c; + + c = val % base; + val /= base; + if (val) + s = i_compute(val, base, s); + STORE_BYTE(s ++, c>9 ? c-10+'a' : c+'0'); + return s; +} +#ifdef DO_LONG +static char *l_compute(long l1,int d, char * s) +{ + int c; + long l2; + + if (l1 < 0) { + c = l1 & 1; + l2 = ((l1>>1) & ~signbit(l1)); + l1 = l2 / (d>>1); + c += (l2%(d>>1))<<1; + } + else { + c = l1 % d; + l1 = l1 / d; + } + if (l1) + s = l_compute(l1, d, s); + STORE_BYTE(s ++, c>9 ? c-10+'A' : c+'0'); + return s; +} +#endif +#ifdef _STORE_BYTE +long store_byte(char * cp, long c) +{ + long shift, reg, * ptr; + + shift = ((long) cp & 3) * 8; + ptr = (long *) ((long) cp & ~3); + reg = * ptr; + reg &= ~(0xff << shift); + reg |= c << shift; + * ptr = reg; + + return c; +} +#endif + +#define SPC 01 +#define STP 02 + +#define NULL 0 +#define EOF 0 +#define SHORT 0 +#define REGULAR 1 +#define LONG 2 +#define INT 0 +#define FLOAT 1 + +static int new_c(void); +static void unnew_c(char); +static int _innum(int ** ptr, int type, int len, int size, int * eofptr); +static int _instr(char * ptr, int type, int len, int * eofptr); +static const char * _getccl(const char *); +static int vme_isupper(char); +static int vme_tolower(char); +static int vme_isdigit(char); + +static char _sctab[128] = { + 0,0,0,0,0,0,0,0, + 0,SPC,SPC,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + SPC,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, +}; +static const char * line; +static char * linep; + +int unformat_string(const char * fmt, int ** argp, const char * buffer) +{ + int ch; + int nmatch, len, ch1; + int ** ptr, fileended, size; + + line = buffer; + linep = (char*)line; + + nmatch = 0; + fileended = 0; + for (;;) switch (ch = * fmt ++) { + case '\0': + return (nmatch); + case '%': + if ((ch = * fmt ++) == '%') + goto def; + ptr = 0; + if (ch != '*') + ptr = argp ++; + else + ch = * fmt ++; + len = 0; + size = REGULAR; + while (vme_isdigit(ch)) { + len = len*10 + ch - '0'; + ch = * fmt ++; + } + if (len == 0) + len = 30000; + if (ch == 'l') { + ch = * fmt ++; + size = LONG; + } + else if (ch == 'h') { + size = SHORT; + ch = * fmt ++; + } + else if (ch=='[') + fmt = _getccl(fmt); + if (vme_isupper(ch)) { + ch = vme_tolower(ch); + size = LONG; + } + if (ch == '\0') + return -1; + if (_innum(ptr, ch, len, size, & fileended) && ptr) + nmatch ++; + if (fileended) + return nmatch? nmatch: -1; + break; + case ' ': + case '\n': + case '\t': + while ((ch1 = new_c())==' ' || ch1=='\t' || ch1=='\n') + ; + if (ch1 != EOF) + unnew_c(ch1); + break; + default: + + def: + + ch1 = new_c(); + if (ch1 != ch) { + if (ch1==EOF) + return -1 ; + unnew_c(ch1); + return nmatch; + } + } +} +static int new_c() +{ + char c; + + if (linep) { + c = * linep ++; + return c; + } + else { + return 0; + } +} +static void unnew_c(char ch) +{ + if (linep > line) + * (-- linep) = ch; +} +static int _innum(int ** ptr, int type, int len, int size, int * eofptr) +{ +# ifdef DO_FLOAT + extern double atof(); +# endif + char * np; + char numbuf[64]; + int c, base; + int expseen, scale, negflg, c1, ndigit; + long lcval; + + if (type=='c' || type=='s' || type=='[') + return _instr(ptr? * (char **) ptr: (char *) NULL, type, len, eofptr); + lcval = 0; + ndigit = 0; + scale = INT; + if (type=='e'||type=='f') + scale = FLOAT; + base = 10; + if (type=='o') + base = 8; + else if (type=='x') + base = 16; + np = numbuf; + expseen = 0; + negflg = 0; + while ((c = new_c())==' ' || c=='\t' || c=='\n'); + if (c=='-') { + negflg ++; + * np ++ = c; + c = new_c(); + len --; + } + else if (c=='+') { + len --; + c = new_c(); + } + for ( ; -- len >= 0; * np ++ = c, c = new_c()) { + if (vme_isdigit(c) + || base==16 && ('a'<=c && c<='f' || 'A'<=c && c<='F')) { + ndigit ++; + if (base==8) + lcval <<=3; + else if (base==10) + lcval = ((lcval<<2) + lcval)<<1; + else + lcval <<= 4; + c1 = c; + if ('0'<=c && c<='9') + c -= '0'; + else if ('a'<=c && c<='f') + c -= 'a'-10; + else + c -= 'A'-10; + lcval += c; + c = c1; + continue; + } + else if (c=='.') { + if (base!=10 || scale==INT) + break; + ndigit ++; + continue; + } + else if ((c=='e'||c=='E') && expseen==0) { + if (base!=10 || scale==INT || ndigit==0) + break; + expseen ++; + * np ++ = c; + c = new_c(); + if (c!='+'&&c!='-'&&('0'>c||c>'9')) + break; + } + else + break; + } + if (negflg) + lcval = -lcval; + if (c != EOF) { + unnew_c(c); + * eofptr = 0; + } + else + * eofptr = 1; + if (ptr==NULL || np==numbuf) + return 0; + * np ++ = 0; + switch ((scale<<4) | size) { +# ifdef DO_FLOAT + + case (FLOAT<<4) | SHORT: + case (FLOAT<<4) | REGULAR: + ** (float **) ptr = atof(numbuf); + break; + + case (FLOAT<<4) | LONG: + ** (double **) ptr = atof(numbuf); + break; +# endif + case (INT<<4) | SHORT: + ** (short **) ptr = lcval; + break; + + case (INT<<4) | REGULAR: + ** (int **) ptr = lcval; + break; + + case (INT<<4) | LONG: + ** (long **) ptr = lcval; + break; + } + return 1; +} +static int _instr(char * ptr, int type, int len, int * eofptr) +{ + int ch; + char * optr; + int ignstp; + + * eofptr = 0; + optr = ptr; + if (type=='c' && len==30000) + len = 1; + ignstp = 0; + if (type=='s') + ignstp = SPC; + while (_sctab[ch = new_c()] & ignstp) + if (ch==EOF) + break; + ignstp = SPC; + if (type=='c') + ignstp = 0; + else if (type=='[') + ignstp = STP; + while (ch!=EOF && (_sctab[ch]&ignstp)==0) { + if (ptr) + * ptr ++ = ch; + if (-- len <= 0) + break; + ch = new_c(); + } + if (ch != EOF) { + if (len > 0) + unnew_c(ch); + * eofptr = 0; + } + else + * eofptr = 1; + if (ptr && ptr!=optr) { + if (type!='c') + * ptr ++ = '\0'; + return 1; + } + return 0; +} +static const char * _getccl(const char * s) +{ + int c, t; + + t = 0; + if (* s == '^') { + t ++; + s ++; + } + for (c = 0; c < 128; c++) + if (t) + _sctab[c] &= ~STP; + else + _sctab[c] |= STP; + while (((c = * s ++)&0177) != ']') { + if (t) + _sctab[c++] |= STP; + else + _sctab[c++] &= ~STP; + if (c==0) + return -- s; + } + return s; +} +static int vme_isupper(char ch) +{ + if( ch >= 'A' & ch <= 'Z') + return 1; + else + return 0; +} +static int vme_tolower(char ch) +{ + return 'a' + 'A' - ch; +} +static vme_isdigit(char ch) +{ + if (ch >= '0' & ch <= '9') + return 1; + else + return 0; +} +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/frmstr.h b/c/src/lib/libbsp/i960/rxgen960/startup/frmstr.h new file mode 100644 index 0000000000..5460aaf91e --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/frmstr.h @@ -0,0 +1,43 @@ + + /* frmstr.h + * Interface to procedures used to implement + * the printf group. + */ + +#ifndef _FRMSTR_H_ +#define _FRMSTR_H_ + +#ifdef __i960 + +typedef int ArgType; +typedef unsigned int ArgType_U; + +#else + +typedef long ArgType; +typedef unsigned long ArgType_U; + +#endif + + /* Format a string. + */ +extern int format_string(const char * frmt, ArgType * args, char * buffer); + /* Get arguments from formatted string. + */ +extern int unformat_string(const char * fmt, int ** argp, const char * buffer); + + /* Definitions for control characters. + */ +#define BELL ('G' & 0x1f) +#define BACKSPACE '\b' +#define DELETE 0x7f +#define KILL ('U' - 'A' + 1) +#define XON ('Q' & 0x1f) +#define XOFF ('S' & 0x1f) +#define CNTRL_C 0x3 + +#endif + + /* End of File + */ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/i960.h b/c/src/lib/libbsp/i960/rxgen960/startup/i960.h new file mode 100644 index 0000000000..a89afc4c37 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/i960.h @@ -0,0 +1,30 @@ +/*-------------------------------------*/ +/* i960.h */ +/* Last change : 3.11.94 */ +/*-------------------------------------*/ +#ifndef _I960_H_ +#define _I960_H_ + +#define REGISTER_SIZE 4 +#define NUM_REGS 40 + +#define R0_REGNUM 0 /* First local register */ +#define SP_REGNUM 1 /* Contains address of top of stack */ +#define RIP_REGNUM 2 /* Return instruction pointer (local r2) */ +#define R15_REGNUM 15 /* Last local register */ +#define G0_REGNUM 16 /* First global register */ +#define G13_REGNUM 29 /* g13 - holds struct return address */ +#define G14_REGNUM 30 /* g14 - ptr to arg block / leafproc return address */ +#define FP_REGNUM 31 /* Contains address of executing stack frame */ +#define PCW_REGNUM 32 /* process control word */ +#define ACW_REGNUM 33 /* arithmetic control word */ +#define TCW_REGNUM 34 /* trace control word */ +#define IP_REGNUM 35 /* instruction pointer */ +#define FP0_REGNUM 36 /* First floating point register */ + +#define REGISTER_BYTES ((36*4) + (4*10)) + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/ihandler.h b/c/src/lib/libbsp/i960/rxgen960/startup/ihandler.h new file mode 100644 index 0000000000..4d42bfc15b --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/ihandler.h @@ -0,0 +1,20 @@ +/*-------------------------------------*/ +/* ihandler.h */ +/* Last change : 12.10.94 */ +/*-------------------------------------*/ +#ifndef _IHANDLER_H_ +#define _IHANDLER_H_ + + /* Interrupt Handler for NMI. + */ +extern void nmiHandler(void); + /* Interrupt Handlers for Dedicated Interrupts. + */ +extern void intr5Handler(void); +extern void intr6Handler(void); + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/ihandler.s b/c/src/lib/libbsp/i960/rxgen960/startup/ihandler.s new file mode 100644 index 0000000000..711c1a118d --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/ihandler.s @@ -0,0 +1,50 @@ +####################################### +# ihandler.s # +# Last change : 8.11.94 # +####################################### + + .text + .globl _nmiHandler + .globl _intr5Handler + .globl _intr6Handler + .globl _clockHandler + + .text + +# NMI Handler +_nmiHandler : + ldconst 64, r4 + addo sp, r4, sp + + stq g0, -64(sp) + stq g4, -48(sp) + stq g8, -32(sp) + stt g12, -16(sp) + + callx _nmi_isr + + ldq -64(sp), g0 + ldq -48(sp), g4 + ldq -32(sp), g8 + ldt -16(sp), g12 + + ret +_clockHandler : + ldconst 64, r4 + addo sp, r4, sp + + stq g0, -64(sp) + stq g4, -48(sp) + stq g8, -32(sp) + stt g12, -16(sp) + + callx _Clock_isr + + ldq -64(sp), g0 + ldq -48(sp), g4 + ldq -32(sp), g8 + ldt -16(sp), g12 +# +# + ret + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/intrtbl.c b/c/src/lib/libbsp/i960/rxgen960/startup/intrtbl.c new file mode 100644 index 0000000000..a3e10ba62e --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/intrtbl.c @@ -0,0 +1,53 @@ +/*-------------------------------------*/ +/* intrtbl.c */ +/* Last change : 12.10.94 */ +/*-------------------------------------*/ +#include "ihandler.h" +#include "intrtbl.h" +/*-------------------------------------*/ + + + /* Interrupt Table. Dedicated Interrupts are cached. + * So NMI handler has to be defined here. + */ +InterruptTbl interruptTbl = { + 0, /* Pending Priorities */ + 0, 0, 0, 0, 0, 0, 0, 0, /* Pending Interrupts */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 8 - 15 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 16 - 23 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 24 - 31 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 32 - 39 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 40 - 47 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 48 - 55 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 56 - 63 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 64 - 71 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 72 - 79 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 80 - 87 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 88 - 95 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 96 - 103 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 104 - 111 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 112 - 119 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 120 - 127 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 128 - 135 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 136 - 143 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 144 - 151 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 152 - 159 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 160 - 167 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 168 - 175 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 176 - 183 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 184 - 191 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 192 - 199 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 200 - 207 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 208 - 215 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 216 - 223 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 224 - 231 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 232 - 239 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 240 - 247 */ + nmiHandler + NORMAL_IH, /* 248 : NMI handler */ + 0, 0, 0, 0, 0, 0, 0, /* 249 - 255 */ + +}; +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/intrtbl.h b/c/src/lib/libbsp/i960/rxgen960/startup/intrtbl.h new file mode 100644 index 0000000000..944d11960e --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/intrtbl.h @@ -0,0 +1,30 @@ +/*-------------------------------------*/ +/* intrtbl.h */ +/* Last change : 12.10.94 */ +/*-------------------------------------*/ +#ifndef _INTRTBL_H_ +#define _INTRTBL_H_ + + /* Interrupt Handler. + */ +typedef void (* IntrHndl)(void); + /* Interrupt Table. + */ +typedef struct { + unsigned int pendPrty; /* Pending Priorities */ + unsigned int pendIntr[8]; /* Pending Interrupts */ + IntrHndl intrHndl[248]; /* Interrupt Handlers */ +} InterruptTbl; + /* Interrupt Handler Type. + */ +#define NORMAL_IH 0 +#define IN_CACHE_IH 0x10 + /* Interrupt Table Itself. + */ +extern InterruptTbl interruptTbl; + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/kkprintf.c b/c/src/lib/libbsp/i960/rxgen960/startup/kkprintf.c new file mode 100644 index 0000000000..f2193ad606 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/kkprintf.c @@ -0,0 +1,65 @@ +/* + a safe version of printf that might be useful for debugging parts that + are known to have problems e.g. with printf() e.t.c. +*/ +#include <_ansi.h> +#ifdef _HAVE_STDC +#include <stdarg.h> +#else +#include <varargs.h> +#endif +char kkBuf[1024]; +/* Routine to do "console" in fully polled mode */ +void static kkputs( const char *); +format_string(char * fmt, va_list ap, char * kkBuf); +#ifdef _HAVE_STDC +void +kkprintf (const char *fmt, ...) +{ + va_list ap; + + va_start (ap, fmt); + format_string (fmt, *ap+4, kkBuf); + kkputs(kkBuf); + va_end (ap); +} +void mkvisable() +{ + kkputs("Hello"); +} +#else +void +kkprintf(fmt, va_alist) +char * fmt; +va_dcl +{ + va_list ap; + va_start(ap); + format_string(fmt, ap, kkBuf); + kkputs(kkBuf); + va_end(ap); +} +#endif +extern int DBGConsole_make_sync; +void +kkputs( const char * buf) +{ + volatile unsigned int * consoleOP; + unsigned char c; + consoleOP = (unsigned int *) 0x1318; /* Outbound Message 0 */ + while (( c = *buf++) != 0){ + while( DBGConsole_make_sync && (*consoleOP != 0)) + ; + *consoleOP = (unsigned int)c; + } +} + + +/* we have got an error during build for 'isatty()' wo/ good reason + we temporarily use this fix.... +*/ +isatty(int fd) +{ + return 1; +} + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/linkcmds b/c/src/lib/libbsp/i960/rxgen960/startup/linkcmds new file mode 100644 index 0000000000..3c1ed86488 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/linkcmds @@ -0,0 +1,185 @@ +/*------------------------------------*/ +/* rom.ld */ +/* Last change : 19. 4.95 */ +/*------------------------------------* + * To build ROM based i960 image. + *------------------------------------*/ + + +MEMORY +{ + config : org = 0xFeffFF30, len = 0xd0 + eprom : org = 0xfec00000, len = 1024K +} + + +_bootAddr = 0xa0200000; +/*_HEAP = 0xA0100000 ; */ +_rom_ibr_cksum = -(_romStart + _rom_prcb); + +SECTIONS +{ + prcb : + { + rom_ibr.o + } > config + + /* Only monitor start point and fault handler + * will live in ROM as far as text is concerned. + * Only fault table will live in ROM as far as data + * is concerned. + */ + romCode : + { + /* Make sure that the monitor start point + * is the first location in EPROM. + */ + rxgen_romld.o(.text) + /* Procedures to copy code and + * initialize bss in RAM. + */ + sctns.o(.text) + /* Make Sure Fault Table (and its handler's data) + * live here so that they wouldn't get destroyed). + */ + asmfault.o + ihandler.o + . = ALIGN(16); + flttbl.o + /* 16 byte aligned PRCB. + */ + . = ALIGN(16); + rom_prcb.o(.data) + . = ALIGN(16); + rom_cntrltbl.o(.data) + . = ALIGN(16); + intrtbl.o(.data) + . = ALIGN(16); + nulsystbl.o(.data) + . = ALIGN(16); + /* I need this symbol to know where code which is + * to be copied reside in ROM. Align it on a 16 + * boundary. + */ + . = ALIGN(16); + _codeRomStart = .; + } > eprom + + /* All the rest of the code will live in RAM. + * Relocation are created as though code resides + * in RAM, while code is placed right after romCode. + * This is responsiblity of the ROM monitor to + * copy code into ROM. + */ + ramCode : AT(ADDR(romCode) + SIZEOF(romCode)) + { + /* RAM-based code section start. + * I need this symbol to know where to copy code + * at initialization time . + */ + _codeRamStart = .; + /* RAM based fault recovery stuff. + */ + _faultStart = .; + asmstub.o + fault.o + _faultEnd = .; + /* Check sum to gurantee that + * the above section wasn't broken. + */ + . = ALIGN(16); + _faultCheckSum = .; + . += 4; + /* Fault Buffer to keep the state of + * the fauled procedure. + */ + _faultBuffer = .; + . += 256; + /* All the rest of the text goes here. + */ + . = ALIGN(16); + *(.text) +/* NEW TEST TEST TEST TEST */ + . = ALIGN (16); + + *(.eh_fram) + . = ALIGN (16); + + /* + * C++ constructors + */ + __CTOR_LIST__ = .; + LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) + *(.ctors) + LONG(0) + __CTOR_END__ = .; + __DTOR_LIST__ = .; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) + *(.dtors) + LONG(0) + __DTOR_END__ = .; + etext = ALIGN( 0x10 ) ; +/* END NEW TEST TEST TEST */ + /* 16 byte aligned PRCB. + */ + . = ALIGN(16); + prcb.o(.data) + /* 16 byte aligned Control Table. + */ + . = ALIGN(16); + cntrltbl.o(.data) + . = ALIGN(16); + systbl.o(.data) + /* All the rest of program defined data goes here. + */ + *(.data) + /* RAM-based code section end. + * I need this symbol to know where to copy code + * at initialization time . + */ + _codeRamEnd = .; + } > eprom + + /* RAM based uninitialized data. + */ + bss (NOLOAD) : + { + /* BSS section start. I need this symbol to + * zero BSS on initialization. + */ + /* Heap. Aligned on a 64 boundary */ + /* . = ALIGN(64); + _heap_initial = .; + . += 64K;*/ + /* Supervisor Stack. Aligned on a 16 boundary. + */ + . = ALIGN(16); + _svrStackPtr = .; + . += 16K; + /* Interrupt Stack. Aligned on a 16 boundary. + */ + . = ALIGN(16); + _intStackPtr = .; + . += 16K; + /* Program defined BSS. + */ + _bssStart = .; + _bss_start = .; + *(.bss) + /* Program defined COMMON. + */ + *(COMMON) + _end = .; + /* BSS section end. I need this symbol to + * zero BSS on initialization. + */ + _bssEnd = .; + _bssStart_1 = .; + _bssEnd_1 = .; + } > eprom + +} + +/*-------------*/ +/* End of file */ +/*-------------*/ diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/main.h b/c/src/lib/libbsp/i960/rxgen960/startup/main.h new file mode 100644 index 0000000000..0aabd34cca --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/main.h @@ -0,0 +1,24 @@ +/*-------------------------------------*/ +/* main.h */ +/* Last change : 2. 2.95 */ +/*-------------------------------------*/ +#ifndef _MAIN_H_ +#define _MAIN_H_ + + /* ROM monitor main function(s). + * Gets control from rommon.s. + */ +extern void romMain(void); +extern void romFaultMain(void); +extern void romTestMain(void); + +extern char * mainRevisionStr(void); +extern char * mainBuildStr(void); + +extern unsigned int bootAddr[]; + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/memchnl.h b/c/src/lib/libbsp/i960/rxgen960/startup/memchnl.h new file mode 100644 index 0000000000..35bba178e8 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/memchnl.h @@ -0,0 +1,67 @@ +/*-------------------------------------*/ +/* memchnl.h */ +/* Last change : 16. 5.95 */ +/*-------------------------------------*/ +#ifndef _MEMCHNL_H_ +#define _MEMCHNL_H_ + +/* The following is a dummy for now to be filled in + as the message passing stuff gets migrated to + I20 (or other standard ) +*/ + +typedef +struct memMsg{ + int * foo; +} IOTrCBlk, * iotrcb_ptr_t; + +typedef void * iotrcb_sgm_t; + + /* Interrupt arrived from X processor. + * This is invoked from low-level interrupt dispatcher. + */ +extern void memChnlIntrFromHost(void); + /* This IOT's processing is completed. + * Signal the host, it can take it back. + */ +extern void memChnlIotFinished(IOTrCBlk *); + /* A fault has just occured. Pass a signal over + * memory channel. + */ +extern void memChnlI960Fault(void); + /* IOT handler procedure. + */ +typedef void (* IotHandler)(IOTrCBlk *, int tr_req); + /* Register handler to process IOT's. + */ +extern void memChnlRegisterHndl(IotHandler); + /* Intermediate image buffer. + * Defined in *.ld + */ +extern unsigned int downloadStart[]; + +typedef struct { + int ptr_len; + iotrcb_ptr_t ptr_loc; + iotrcb_ptr_t * ptr_crnt; + iotrcb_sgm_t * sgm_crnt; +} BufLookupHndl; + /* Procedures to travel throughout the buffer page list. + * It should be accomplished as below: + * ... + * BufLookupHndl hndl; + * char * buf; + * if (memBufLookupInit(& hndl, iot) != 0) { + * while ((buf = memBufLookupNext(& hndl)) != 0) { + * ... buf is a buffer page address. + * } + * } + */ +extern BufLookupHndl * memBufLookupInit(BufLookupHndl *, IOTrCBlk *); +extern void * memBufLookupNext(BufLookupHndl *); + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/nmi.c b/c/src/lib/libbsp/i960/rxgen960/startup/nmi.c new file mode 100644 index 0000000000..f7a6bf9aa4 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/nmi.c @@ -0,0 +1,11 @@ +int mach_error_expected = 0; +void nmi_isr(void) +{ + if( mach_error_expected) + { + mach_error_expected = 0; + } + else{ + kkprintf("NMI Interrupt Occured \n"); + } +} diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/nulsystbl.c b/c/src/lib/libbsp/i960/rxgen960/startup/nulsystbl.c new file mode 100644 index 0000000000..294bff6152 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/nulsystbl.c @@ -0,0 +1,79 @@ +/*-------------------------------------*/ +/* systbl.c */ +/* Last change : 21. 3.95 */ +/*-------------------------------------*/ +#include "prcb.h" +#include "systbl.h" +/*-------------------------------------*/ + /* System Procedures Table. + * Dummy version that will live in ROM at all times + * RP does fetch on it, so must be present here rather than pointing + * to ram + */ +SystemTbl nulsystemTbl = { + 0, 0, 0, /* Reserved */ + svrStackPtr, /* Supervisor Stack Pointer Base */ + 0, 0, 0, 0, 0, 0, 0, 0, /* Preserved */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 0 - 7 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 8 - 15 */ + 0, 0, /* 16 - 17 */ + 0, /* 18 */ + 0, /* 19 */ + 0, /* 20 */ + 0, /* 21 */ + 0, 0, /* 22 - 23 */ + 0, /* 24 */ + 0, /* 25 */ + 0, /* 26 */ + 0, /* 27 */ + 0, /* 28 */ + 0, /* 29 */ + 0, /* 30 */ + 0, /* 31 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 32 - 39 */ + 0, /* 40 */ + 0, /* 41 */ + 0, /* 42 */ + 0, /* 43 */ + 0, /* 44 */ + 0, /* 45 */ + 0, /* 46 */ + 0, /* 47 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 48 - 55 */ + 0, /* 56 */ + 0, /* 57 */ + 0, /* 58 */ + 0, 0, 0, 0, 0, /* 59 - 63 */ + 0, /* 64 */ + 0, /* 65 */ + 0, 0, 0, 0, 0, 0, /* 66 - 71 */ + 0, /* 72 */ + 0, /* 73 */ + 0, /* 74 */ + 0, /* 75 */ + 0, /* 76 */ + 0, /* 77 */ + 0, 0, /* 78 - 79 */ + 0, /* 80 */ + 0, /* 81 */ + 0, 0, 0, 0, 0, 0, /* 82 - 87 */ + 0, /* 88 */ + 0, 0, 0, 0, 0, 0, 0, /* 89 - 95 */ + 0, /* 96 */ + 0, /* 97 */ + 0, 0, 0, 0, 0, 0, /* 98 - 103 */ + 0, /* 104 */ + 0, /* 105 */ + 0, /* 106 */ + 0, /* 107 */ + 0, /* 108 */ + 0, /* 109 */ + 0, 0, /* 110 - 111 */ + 0, /* 112 */ + 0, /* 113 */ + 0, /* 114 */ +}; +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/pmc901_memmap.h b/c/src/lib/libbsp/i960/rxgen960/startup/pmc901_memmap.h new file mode 100644 index 0000000000..51ee73dec0 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/pmc901_memmap.h @@ -0,0 +1,8 @@ +/* Memory map for the pmc901 ; works for most RAMiX PMC/CPCI modules as well */ + +#define UART_REG 0xc0000100 +#define LED_REG 0xc0000200 +#define DRAM_BASE 0xa0000000 +#define DRAM_SIZE 0x00400000 +#define DRAM_SIZE_MASK 0xffc00000 +#define FLASH_BASE 0xfe000000 diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/prcb.c b/c/src/lib/libbsp/i960/rxgen960/startup/prcb.c new file mode 100644 index 0000000000..77c0f09780 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/prcb.c @@ -0,0 +1,54 @@ +/*-------------------------------------*/ +/* prcb.c */ +/* Last change : 11.10.94 */ +/*-------------------------------------*/ +#include "flttbl.h" +#include "cntrltbl.h" +#include "intrtbl.h" +#include "systbl.h" +#include "prcb.h" +/*-------------------------------------*/ + /* RAM based PRocess Control Block + */ +#ifdef DBPRECISE_FAULTS +#define AC (INT_OVFL_DISABLE | PRECISE_FLTS) +#else +#define AC (INT_OVFL_DISABLE | IMPRECISE_FLTS) +#endif + + /* Initial Fault Configuration Word Image. + * As to this 1, I don't know why but without it + * fault hanlder wouldn't be invoked. + */ +#define FAULT_CONFIG (UNLGND_FAULT_DISABLE | 1) + + /* Initial Instruction Cache Configuration Word Image. + */ +#ifdef DBCACHE_OFF +#define INST_CACHE_CONFIG (INST_CACHE_DISABLE) +#else +#define INST_CACHE_CONFIG (INST_CACHE_ENABLE) +#endif + + /* Initial Register Cache Configuration Word Image. + */ +#define REG_CACHE_CONFIG 0x000 + + +struct PRCB ram_prcb = { + & faultTbl[0], /* Fault Table Base */ + & controlTbl[0], /* Control Table Base */ + AC, /* AC */ + FAULT_CONFIG, /* Fault Configuration Word */ + & interruptTbl, /* Interrupt Table Base */ + & systemTbl, /* System Procedure Table Base */ + 0, /* Reserved */ + & intStackPtr[0], /* Interrupt Stack Pointer */ + INST_CACHE_CONFIG, /* Instruction Cache Config */ + REG_CACHE_CONFIG, /* Reg Cache Config */ +}; + +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/prcb.h b/c/src/lib/libbsp/i960/rxgen960/startup/prcb.h new file mode 100644 index 0000000000..9b9f4c59bc --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/prcb.h @@ -0,0 +1,57 @@ +/*-------------------------------------*/ +/* prcb.h */ +/* Last change : 11. 1.95 */ +/*-------------------------------------*/ +#ifndef _PRCB_H_ +#define _PRCB_H_ + +#include "flttbl.h" +#include "cntrltbl.h" +#include "intrtbl.h" +#include "systbl.h" + + /* PRocess Control Block + */ +struct PRCB { + FaultTblEntry * faultTbl; /* Fault Table Base */ + ControlTblEntry * controlTbl; /* Control Table Base */ + unsigned int arithConfig; /* Arithmetic Control Register Image */ + unsigned int faultConfig; /* Fault Configuration Word Image */ + InterruptTbl * interruptTbl; /* Interrupt Table Base */ + SystemTbl * systemTbl; /* System Procedure Table Base */ + unsigned int reserved; /* Reserved */ + unsigned int * intStackPtr; /* Interrupt Stack Pointer */ + unsigned int instCacheConfig; /* Instruction Cache Config */ + unsigned int regCacheConfig; /* Register Cache Config */ +}; + /* Constants for Arithmetic Control Register. + */ +#define INT_OVFL_ENABLE 0 +#define INT_OVFL_DISABLE 0x1000 + +#define PRECISE_FLTS 0x8000 +#define IMPRECISE_FLTS 0 + /* Constants for Fault Configuration Word. + */ +#define UNLGND_FAULT_ENABLE 0 +#define UNLGND_FAULT_DISABLE 0x40000000 + /* Constants for Instruction Cache Configuration Word. + */ +#define INST_CACHE_ENABLE 0 +#define INST_CACHE_DISABLE 0x10000 + /* RAM-based Process Control Block. + */ +extern struct PRCB ram_prcb; +extern struct PRCB rom_prcb; + /* Supervisor Stack. Is defined directly in rom.ld. + */ +extern unsigned int svrStackPtr[]; + /* Interrupt Stack. Is defined directly in rom.ld. + */ +extern unsigned int intStackPtr[]; + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/rom.ld b/c/src/lib/libbsp/i960/rxgen960/startup/rom.ld new file mode 100644 index 0000000000..057fbbebf2 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/rom.ld @@ -0,0 +1,158 @@ +/*------------------------------------*/ +/* rom.ld */ +/* Last change : 19. 4.95 */ +/*------------------------------------* + * To build ROM based i960 image. + *------------------------------------*/ + + +MEMORY +{ + config : org = 0xFeffFF30, len = 0xd0 + eprom : org = 0xfef80000, len = 120K + sram : org = 0xA0000000, len = 128K +} + +_rom_ibr_cksum = -(_romStart + _rom_prcb); + +_bootAddr = 0xa0200000; +_HEAP = 0xA0100000 ; + +SECTIONS +{ + prcb : + { + rom_ibr.o960 + } > config + + /* Only monitor start point and fault handler + * will live in ROM as far as text is concerned. + * Only fault table will live in ROM as far as data + * is concerned. + */ + romCode : + { + /* Make sure that the monitor start point + * is the first location in EPROM. + */ + rommon.o960(.text) + /* Procedures to copy code and + * initialize bss in RAM. + */ + sctns.o960(.text) + /* Make Sure Fault Table (and its handler's data) + * live here so that they wouldn't get destroyed). + */ + asmfault.o960 + flttbl.o960 + /* 16 byte aligned PRCB. + */ + . = ALIGN(16); + rom_prcb.o960(.data) + /* 16 byte aligned Control Table. + */ + . = ALIGN(16); + rom_cntrltbl.o960(.data) + . = ALIGN(16); + intrtbl.o960(.data) + . = ALIGN(16); + nulsystbl.o960(.data) + . = ALIGN(16); + /* I need this symbol to know where code which is + * to be copied reside in ROM. Align it on a 16 + * boundary. + */ + . = ALIGN(16); + _codeRomStart = .; + } > eprom + + /* All the rest of the code will live in RAM. + * Relocation are created as though code resides + * in RAM, while code is placed right after romCode. + * This is responsiblity of the ROM monitor to + * copy code into ROM. + */ + ramCode : AT(ADDR(romCode) + SIZEOF(romCode)) + { + /* RAM-based code section start. + * I need this symbol to know where to copy code + * at initialization time . + */ + _codeRamStart = .; + /* RAM based fault recovery stuff. + */ + _faultStart = .; + fault.o960 + _faultEnd = .; + /* Check sum to gurantee that + * the above section wasn't broken. + */ + . = ALIGN(16); + _faultCheckSum = .; + . += 4; + /* Fault Buffer to keep the state of + * the fauled procedure. + */ + _faultBuffer = .; + . += 256; + /* All the rest of the text goes here. + */ + . = ALIGN(16); + *(.text) + /* 16 byte aligned PRCB. + */ + . = ALIGN(16); + prcb.o960(.data) + /* 16 byte aligned Control Table. + */ + . = ALIGN(16); + cntrltbl.o960(.data) + . = ALIGN(16); + systbl.o960(.data) + /* All the rest of program defined data goes here. + */ + *(.data) + /* RAM-based code section end. + * I need this symbol to know where to copy code + * at initialization time . + */ + _codeRamEnd = .; + } > sram + + /* RAM based uninitialized data. + */ + bss (NOLOAD) : + { + /* BSS section start. I need this symbol to + * zero BSS on initialization. + */ + _bssStart = .; + /* Supervisor Stack. Aligned on a 16 boundary. + */ + . = ALIGN(16); + _svrStackPtr = .; + . += 4K; + /* Interrupt Stack. Aligned on a 16 boundary. + */ + . = ALIGN(16); + _intStackPtr = .; + . += 4K; + /* Program defined BSS. + */ + *(.bss) + /* Program defined COMMON. + */ + *(COMMON) + /* BSS section end. I need this symbol to + * zero BSS on initialization. + */ + _bssEnd = .; + _bssStart_1 = .; + _bssEnd_1 = .; + } > sram + +} + +/*-------------*/ +/* End of file */ +/*-------------*/ diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c b/c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c new file mode 100644 index 0000000000..c9051d0296 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c @@ -0,0 +1,85 @@ +/*-------------------------------------*/ +/* cntrltbl.c */ +/* Last change : 7.10.94 */ +/*-------------------------------------*/ +#include <i960RP.h> +#include "cntrltbl.h" +/*-------------------------------------*/ + /* Control Table. + */ + /* Interrupt Map Registers Initial. + */ +#define IMAP0 0x4321 +#define IMAP1 0x8765 +#define IMAP2 0xA90000 +#define ICON (VECTOR_CACHE | MSK_UNCHNG | I_ENABLE) + + +/* Bus configuration */ +#define RP_CONFIG_REGS BUS_WIDTH_32 +#define FLASH BUS_WIDTH_8 +#define DRAM BUS_WIDTH_32 +#define UART_LED BUS_WIDTH_8 +#define DEFAULT BUS_WIDTH_32 + +/* Region Configuration */ +#define REGION_0_CONFIG RP_CONFIG_REGS +#define REGION_2_CONFIG DEFAULT +#define REGION_4_CONFIG DEFAULT +#define REGION_6_CONFIG DEFAULT +#define REGION_8_CONFIG DEFAULT +#define REGION_A_CONFIG DRAM +#define REGION_C_CONFIG UART_LED + +#define REGION_E_CONFIG DEFAULT +#define REGION_BOOT_CONFIG (DRAM ) + + /* Trace Control Initial. */ +#define TC 0 + +/*Bus Control Initial value */ +#define BCON CONF_TBL_VALID + + + +ControlTblEntry rom_controlTbl[] = { + /* --group 0 -- */ + 0, + 0, + 0, + 0, + /* --group 1 -- */ + IMAP0, + IMAP1, + IMAP2, + ICON, + /* --group 2 -- */ + REGION_0_CONFIG, + 0, + REGION_2_CONFIG, + 0, + /* --group 3 -- */ + REGION_4_CONFIG, + 0, + REGION_6_CONFIG, + 0, + /* --group 4 -- */ + REGION_8_CONFIG, + 0, + REGION_A_CONFIG, + 0, + /* --group 5 -- */ + REGION_C_CONFIG, + 0, + REGION_BOOT_CONFIG, + 0, + /* --group 6 -- */ + 0, /* Reserved */ + 0, + TC, + BCON +}; +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/rom_ibr.c b/c/src/lib/libbsp/i960/rxgen960/startup/rom_ibr.c new file mode 100644 index 0000000000..8366f4676f --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/rom_ibr.c @@ -0,0 +1,30 @@ +/*-------------------------------------*/ +/* rom_ibr.h */ +/* Last change : 23. 1.95 */ +/*-------------------------------------*/\ +#include "rom_ibr.h" +#include "prcb.h" +#include "cntrltbl.h" +#include <i960RP.h> +#include "../include/rxgen960_config.h" +/*-------------------------------------*/ +extern void romStart(void); + + +struct IBR rom_ibr = { + {((REGION_BOOT_CONFIG) & 0xff), /* Initial Bus Configuration */ + ((REGION_BOOT_CONFIG) >> 8) & 0xff, + ((REGION_BOOT_CONFIG) >> 16) & 0xff, + ((REGION_BOOT_CONFIG) >> 24) & 0xff}, + romStart, /* Start Point */ + & rom_prcb, /* PRCB */ + {-2, /* CheckSum */ + 0, + 0, + 0, + 0, + (unsigned int) rom_ibr_cksum} +}; +/*-------------*/ +/* End of file */ +/*-------------*/ diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/rom_ibr.h b/c/src/lib/libbsp/i960/rxgen960/startup/rom_ibr.h new file mode 100644 index 0000000000..4025237b4c --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/rom_ibr.h @@ -0,0 +1,29 @@ +/*-------------------------------------*/ +/* rom_ibr.h */ +/* Last change : 23. 1.95 */ +/*-------------------------------------*/ +#ifndef _ROM_IBR_H_ +#define _ROM_IBR_H_ + +#include "flttbl.h" +#include "cntrltbl.h" +#include "intrtbl.h" +#include "systbl.h" + + /* Initial Boot Record. + */ +struct IBR { + unsigned int busConfig[4]; /* Initial Bus Configuration */ + void (* start)(void); /* Start Point */ + struct PRCB * prcb; /* PRCB */ + unsigned int chckSum[6]; /* CheckSum */ +}; + /* Check sum values (defined in *.ld). + */ +extern unsigned int rom_ibr_cksum[]; + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/rom_prcb.c b/c/src/lib/libbsp/i960/rxgen960/startup/rom_prcb.c new file mode 100644 index 0000000000..21c2b92383 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/rom_prcb.c @@ -0,0 +1,55 @@ +/*-------------------------------------*/ +/* prcb.c */ +/* Last change : 11.10.94 */ +/*-------------------------------------*/ +#include "flttbl.h" +#include "cntrltbl.h" +#include "intrtbl.h" +#include "systbl.h" +#include "prcb.h" +/*-------------------------------------*/ + /* RAM based PRocess Control Block + */ +#ifdef DBPRECISE_FAULTS +#define AC (INT_OVFL_DISABLE | PRECISE_FLTS) +#else +#define AC (INT_OVFL_DISABLE | IMPRECISE_FLTS) +#endif + + /* Initial Fault Configuration Word Image. + * As to this 1, I don't know why but without it + * fault hanlder wouldn't be invoked. + */ +#define FAULT_CONFIG (UNLGND_FAULT_DISABLE | 1) +extern SystemTbl nulsystemTbl; + + /* Initial Instruction Cache Configuration Word Image. + */ +#ifdef DBCACHE_OFF +#define INST_CACHE_CONFIG (INST_CACHE_DISABLE) +#else +#define INST_CACHE_CONFIG (INST_CACHE_ENABLE) +#endif + + /* Initial Register Cache Configuration Word Image. + */ +#define REG_CACHE_CONFIG 0x200 + + +struct PRCB rom_prcb = { + & faultTbl[0], /* Fault Table Base */ + & rom_controlTbl[0], /* Control Table Base */ + AC, /* AC */ + FAULT_CONFIG, /* Fault Configuration Word */ + & interruptTbl, /* Interrupt Table Base */ + & nulsystemTbl, /* System Procedure Table Base */ + 0, /* Reserved */ + & intStackPtr[0], /* Interrupt Stack Pointer */ + INST_CACHE_CONFIG, /* Instruction Cache Config */ + REG_CACHE_CONFIG, /* Reg Cache Config */ +}; + +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/rommon.h b/c/src/lib/libbsp/i960/rxgen960/startup/rommon.h new file mode 100644 index 0000000000..22a62b2ce2 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/rommon.h @@ -0,0 +1,26 @@ +/*-------------------------------------*/ +/* rommon.h */ +/* Last change : 23. 1.95 */ +/*-------------------------------------*/ +#ifndef _ROMMON_H_ +#define _ROMMON_H_ + + /* ROM monitor start point. + * Gets control on power on. + */ +extern void romStart(void); +extern void start(void); + /* ROM monitor start point. + * Gets control on a fault. + */ +extern void romFaultStart(void); + /* ROM monitor start point. + * Gets control on a test command. + */ +extern void romTestStart(void); + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/rxgen_romld.s b/c/src/lib/libbsp/i960/rxgen960/startup/rxgen_romld.s new file mode 100644 index 0000000000..5567bf8774 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/rxgen_romld.s @@ -0,0 +1,119 @@ +#include "asm.h" + + BEGIN_CODE + + .globl _romStart + .globl _start + .globl _romFaultStart + .globl _led_array + .text +SYM(romStart ): +SYM(_romStart ): + # This line is to make compiler happy. + mov 0, g14 + ldconst 0x120f,r10 # BIST register +/* + Setup code for in memory loaded image +*/ +/* + # Interrupt stack is used by default. + # Copy all code (except Fault Table and Fault Handler) + # from EPROM into DRAM. +*/ + ldconst 0x120f,r10 //# BIST register + ldconst 0x2,r3 + stob r3,0(r10) //# 2->LED +/* + # Zero all uninitialized data +*/ + callx _zeroBss + ldconst 0x120f,r10 //# BIST register + ldconst 0x3,r3 + stob r3,0(r10) //# 3->LED +/* + # And reinitialize processor. + # _start is a few lines below. + # _prcb is RAM-based struct PRCB. +*/ + ldconst 0x300, r4 + ldconst _pmc_start, r5 + ldconst _ram_prcb, r6 + sysctl r4, r5, r6 +/* + # This point will never be reached. +*/ + +SYM(_pmc_start) : +SYM(pmc_start) : + ldconst 0x120f,r10 # BIST register + ldconst 0x4,r3 + stob r3,0(r10) //# 4->LED + mov 0, g14 +/* + # To get ready to invoke procedures. + # I'll use supervisor stack. +*/ + + ldconst _svrStackPtr, fp + lda 16*4(fp), sp + ldconst 0x5,r3 + stob r3,0(r10) //# 5->LED + + ldconst 0x1F0000, r4 + ldconst 0x1F2000, r3 + ldconst 0, r5 + modpc r4, r3, r5 + + ldconst 7,r3 + stob r3,0(r10) //# 7->LED + + callx _rx_boot_card +/* # if _romMain ever returns ... */ + b _romExit + +SYM(romFaultStart) : +SYM(_romFaultStart) : + + mov 0, g14 + + ldconst 0, sf0 +/* + # To get ready to invoke procedures. + # I'll use supervisor stack. + # _svrStackPtr is defined directly in rom.ld. +*/ + ldconst _svrStackPtr, fp + lda 16*4(fp), sp +/* + # Set processor priority to zero. +*/ + ldconst 0x1F0000, r4 + ldconst 0, r5 + modpc r4, r4, r5 +// # Now to real code +// Fix this up callx _romFaultMain + callx _rx_boot_card +// # if _romMain ever returns ... + b _romExit + +_romExit : +// # if _romMain ever returns ... +// fmark + b _romExit + + + +SYM(led_array): + .byte 99 + .byte 1 + .byte 2 + .byte 3 + .byte 4 + .byte 5 + .byte 6 + .byte 7 + .byte 8 + .byte 9 + .byte 0xa + .byte 0xb + .byte 0xc diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/save_systbl.c b/c/src/lib/libbsp/i960/rxgen960/startup/save_systbl.c new file mode 100644 index 0000000000..c0b7752373 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/save_systbl.c @@ -0,0 +1,231 @@ +/*-------------------------------------*/ +/* systbl.c */ +/* Last change : 21. 3.95 */ +/*-------------------------------------*/ +#include "prcb.h" +/*#include "uart_access.h" */ +#include "fault.h" +#include "faultret.h" +#include "memchnl.h" +#include "main.h" +/*#include "string_impl.h"*/ +#include "stdio.h" +/* #include "stdio_impl.h" */ +#include "systbl.h" +#include "time.h" +/*-------------------------------------*/ + +void sprintf_impl(void) +{ +} + +void printf_A_impl(void) +{ +} + +void printf_B_impl(void) +{ +} + +void sscanf_impl(void) +{ +} + +void console_set_channel_impl(void) +{ +} + +void kbhit_impl(void) +{ +} + +void putc_impl(void) +{ +} + +void getc_impl(void) +{ +} + +void puts_impl(void) +{ +} + +void gets_impl(void) +{ +} + +void printf_impl(void) +{ +} + +void scanf_impl(void) +{ +} + +void strlen_impl(void) +{ +} + +void strcpy_impl(void) +{ +} + +void strcat_impl(void) +{ +} + +void strcmp_impl(void) +{ +} + +void strtok_impl(void) +{ +} + +void strncmp_impl(void) +{ +} + +void strncpy_impl(void) +{ +} + +void console_register_callback_impl(void) +{ +} + +void memcpy_impl(void) +{ +} + +void memcmp_impl(void) +{ +} + +void memset_impl(void) +{ +} + +void memcpy16_impl(void) +{ +} + +void faultRet(unsigned int * faultState) +{ +} + +void memChnlIotFinished(IOTrCBlk *) +{ +} + /* A fault has just occured. Pass a signal over + * memory channel. + */ +void memChnlRegisterHndl(IotHandler) +{ +} + /* Intermediate image buffer. + * Defined in *.ld + */ + +char * mainRevisionStr(void) +{ +} + +char * mainBuildStr(void) +{ +} + +BufLookupHndl * memBufLookupInit(BufLookupHndl *, IOTrCBlk *) +{ +} + +void * memBufLookupNext(BufLookupHndl *) +{ +} + +void memBufLookupInit(void) +{ +} + +void memBufLookupNext(void) +{ +} + +void gettime_impl(void) +{ +} + +void gettime_us_impl(void) +{ +} + + /* System Procedures Table. + */ +SystemTbl systemTbl = { + {0, 0, 0}, /* Reserved */ + svrStackPtr, /* Supervisor Stack Pointer Base */ + {0, 0, 0, 0, 0, 0, 0, 0}, /* Preserved */ + {0, 0, 0, 0, 0, 0, 0, 0, /* 0 - 7 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 8 - 15 */ + 0, 0, /* 16 - 17 */ + SP(sprintf_impl + SUPERVISOR_SP), /* 18 */ + SP(printf_A_impl + SUPERVISOR_SP), /* 19 */ + SP(printf_B_impl + SUPERVISOR_SP), /* 20 */ + SP(sscanf_impl + SUPERVISOR_SP), /* 21 */ + 0, 0, /* 22 - 23 */ + SP(console_set_channel_impl + SUPERVISOR_SP), /* 24 */ + SP(kbhit_impl + SUPERVISOR_SP), /* 25 */ + SP(putc_impl + SUPERVISOR_SP), /* 26 */ + SP(getc_impl + SUPERVISOR_SP), /* 27 */ + SP(puts_impl + SUPERVISOR_SP), /* 28 */ + SP(gets_impl + SUPERVISOR_SP), /* 29 */ + SP(printf_impl + SUPERVISOR_SP), /* 30 */ + SP(scanf_impl + SUPERVISOR_SP), /* 31 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 32 - 39 */ + SP(strlen_impl + SUPERVISOR_SP), /* 40 */ + SP(strcpy_impl + SUPERVISOR_SP), /* 41 */ + SP(strcat_impl + SUPERVISOR_SP), /* 42 */ + SP(strcmp_impl + SUPERVISOR_SP), /* 43 */ + SP(strtok_impl + SUPERVISOR_SP), /* 44 */ + SP(strncmp_impl + SUPERVISOR_SP), /* 45 */ + SP(strncpy_impl + SUPERVISOR_SP), /* 46 */ + 0, /* 47 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 48 - 55 */ + SP(faultRegister + SUPERVISOR_SP), /* 56 */ + SP(faultOk + SUPERVISOR_SP), /* 57 */ + SP(faultRet + SUPERVISOR_SP), /* 58 */ + 0, 0, 0, 0, 0, /* 59 - 63 */ + SP(memChnlIotFinished + SUPERVISOR_SP), /* 64 */ + SP(memChnlRegisterHndl + SUPERVISOR_SP), /* 65 */ + 0, 0, 0, 0, 0, 0, /* 66 - 71 */ + 0, /* 72 */ + 0, /* 73 */ + 0, /* 74 */ + 0, /* 75 */ + 0, /* 76 */ + 0, /* 77 */ + 0, 0, /* 78 - 79 */ + 0, /* 80 */ + 0, /* 81 */ + 0, 0, 0, 0, 0, 0, /* 82 - 87 */ + SP(console_register_callback_impl + SUPERVISOR_SP), /* 88 */ + 0, 0, 0, 0, 0, 0, 0, /* 89 - 95 */ + SP(mainRevisionStr + SUPERVISOR_SP), /* 96 */ + SP(mainBuildStr + SUPERVISOR_SP), /* 97 */ + 0, 0, 0, 0, 0, 0, /* 98 - 103 */ + SP(memBufLookupInit + SUPERVISOR_SP), /* 104 */ + SP(memBufLookupNext + SUPERVISOR_SP), /* 105 */ + SP(memcpy_impl + SUPERVISOR_SP), /* 106 */ + SP(memcmp_impl + SUPERVISOR_SP), /* 107 */ + SP(memset_impl + SUPERVISOR_SP), /* 108 */ + SP(memcpy16_impl + SUPERVISOR_SP), /* 109 */ + 0, 0, /* 110 - 111 */ + SP(gettime_impl + SUPERVISOR_SP), /* 112 */ + SP(gettime_us_impl + SUPERVISOR_SP), /* 113 */ + 0} /* 114 */ +}; +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/sctns.c b/c/src/lib/libbsp/i960/rxgen960/startup/sctns.c new file mode 100644 index 0000000000..ee67ea72ac --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/sctns.c @@ -0,0 +1,99 @@ +/*-------------------------------------*/ +/* sctns.c */ +/* Last change : 10.10.94 */ +/*-------------------------------------*/ +#include "sctns.h" +#include "pmc901_memmap.h" +/*#include "led.h"*/ +/*-------------------------------------*/ + +/* Temporary nullation of WRITE LED */ +#define WRITE_LED(x) errval = x; +void ledcyc() +{ + register int i,t; + extern unsigned char * led_array; + register unsigned char * la; + volatile register int k,m; + la = led_array; + i = 1; +loop: + if (i > 9 ) + i = 1; + *(unsigned char *) LED_REG = la[i]; + for(t=1; t < 0x10000; t++) + k = m + 33; + i++; + goto loop; +} + +void copyCodeToRom(void) +{ + register int errval = 0; + unsigned int * s; + volatile unsigned int * d; + unsigned int t, i; + volatile unsigned char * z; +extern unsigned char * led_array; + + WRITE_LED(0x1); + d = codeRamStart; + *d = 0; + if( *d != 0) + goto error; + WRITE_LED(0x2); + *d = 0xffffffff; + if( *d != 0xffffffff) + goto error; + WRITE_LED(0x3); + t = 1; + for( i=0; i < 31; i++){ + *d = t; + if(*d != t) + goto error; + t <<= 1; + } + z = (unsigned char *)codeRamStart; + *z = 0; + if( *z != 0) + goto error; + *z = 0xf; + if( *z != 0xf) + goto error; + WRITE_LED(0x4); + for (s = codeRomStart, d = codeRamStart; d < codeRamEnd; s ++, d ++) { + * d = * s; + } + WRITE_LED(0x5); + for (s = codeRomStart, d = codeRamStart; d < codeRamEnd; s ++, d ++) { + if( * d != * s ) + goto error; + } + WRITE_LED(0x6); + return; + +error: + while(1){ + for(t=1; t < 0x100000; t++) + *(unsigned char *) LED_REG = errval; + for(t=1; t < 0x100000; t++) + *(unsigned char *) LED_REG = led_array[0]; + } + +} +void zeroBss(void) +{ + unsigned int * p; + + extern unsigned int bssStart_1[], bssEnd_1[]; + + for (p = bssStart; p < bssEnd; p ++) { + * p = 0; + } + for (p = bssStart_1; p < bssEnd_1; p ++) { + * p = 0; + } +} +/*-------------*/ +/* End of file */ +/*-------------*/ diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/sctns.h b/c/src/lib/libbsp/i960/rxgen960/startup/sctns.h new file mode 100644 index 0000000000..767545ee1b --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/sctns.h @@ -0,0 +1,33 @@ +/*-------------------------------------*/ +/* sctns.h */ +/* Last change : 10.10.94 */ +/*-------------------------------------*/ +#ifndef _SCTNS_H_ +#define _SCTNS_H_ + + /* Copy all code into SRAM. + * Fault Table and Fault Handler stays in EPROM to not be + * destroyed by a buggy user program. Beyond that only + * monitor Start point and procedures to copy code + * into RAM will be relocated in ROM. + */ +extern void copyCodeToRam(void); + /* Zero uninitialized section. + */ +extern void zeroBss(void); + + /* Some relocation symbols. These + * symbols are defined in rom.ld. + */ +extern unsigned int codeRomStart[]; +extern unsigned int codeRamStart[]; +extern unsigned int codeRamEnd[]; + +extern unsigned int bssStart[]; +extern unsigned int bssEnd[]; + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/sctns.s b/c/src/lib/libbsp/i960/rxgen960/startup/sctns.s new file mode 100644 index 0000000000..9547e74351 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/sctns.s @@ -0,0 +1,335 @@ + .file "sctns.c" +gcc2_compiled.: +___gnu_compiled_c: +.stabs "/usr/src/rtems-970904/c/src/lib/libbsp/i960/pmc901/startup/",100,0,0,Ltext0 +.stabs "sctns.c",100,0,0,Ltext0 +.text +Ltext0: +.stabs "int:t(0,1)=r(0,1);-2147483648;2147483647;",128,0,0,0 +.stabs "char:t(0,2)=r(0,2);0;255;",128,0,0,0 +.stabs "long int:t(0,3)=r(0,3);-2147483648;2147483647;",128,0,0,0 +.stabs "unsigned int:t(0,4)=r(0,4);0;-1;",128,0,0,0 +.stabs "long unsigned int:t(0,5)=r(0,5);0;-1;",128,0,0,0 +.stabs "long long int:t(0,6)=r(0,1);01000000000000000000000;0777777777777777777777;",128,0,0,0 +.stabs "long long unsigned int:t(0,7)=r(0,1);0000000000000;01777777777777777777777;",128,0,0,0 +.stabs "short int:t(0,8)=r(0,8);-32768;32767;",128,0,0,0 +.stabs "short unsigned int:t(0,9)=r(0,9);0;65535;",128,0,0,0 +.stabs "signed char:t(0,10)=r(0,10);-128;127;",128,0,0,0 +.stabs "unsigned char:t(0,11)=r(0,11);0;255;",128,0,0,0 +.stabs "float:t(0,12)=r(0,1);4;0;",128,0,0,0 +.stabs "double:t(0,13)=r(0,1);8;0;",128,0,0,0 +.stabs "long double:t(0,14)=r(0,1);8;0;",128,0,0,0 +.stabs "complex int:t(0,15)=s8real:(0,1),0,32;imag:(0,1),32,32;;",128,0,0,0 +.stabs "complex float:t(0,16)=r(0,16);4;0;",128,0,0,0 +.stabs "complex double:t(0,17)=r(0,17);8;0;",128,0,0,0 +.stabs "complex long double:t(0,18)=r(0,18);8;0;",128,0,0,0 +.stabs "void:t(0,19)=(0,19)",128,0,0,0 +.stabs "sctns.h",130,0,0,0 +.stabn 162,0,0,0 +.stabs "pmc901_memmap.h",130,0,0,0 +.stabn 162,0,0,0 + .align 4 +.stabs "ledcyc:F(0,19)",36,0,13,_ledcyc + .globl _ledcyc + # Function 'ledcyc' + # Registers used: g0 g1 g4 g5 g6 g7 cc + # +_ledcyc: +.stabn 68,0,13,LM1-_ledcyc +LM1: + addo 16,sp,sp + #Prologue stats: + # Total Frame Size: 16 bytes + # Local Variable Size: 16 bytes + #End Prologue# +.stabn 68,0,14,LM2-_ledcyc +LM2: +LBB2: +.stabn 68,0,18,LM3-_ledcyc +LM3: + ld _led_array,g1 +.stabn 68,0,19,LM4-_ledcyc +LM4: + mov 1,g6 +L9: +.stabn 68,0,21,LM5-_ledcyc +LM5: + cmpibge 9,g6,L10 +.stabn 68,0,22,LM6-_ledcyc +LM6: + mov 1,g6 +L10: +.stabn 68,0,23,LM7-_ledcyc +LM7: + ldob (g1)[g6*1],g4 +.stabn 68,0,24,LM8-_ledcyc +LM8: + mov 1,g5 + ldconst 0xffff,g0 + addo 31,2,g7 # ldconst 33,g7 +.stabn 68,0,23,LM9-_ledcyc +LM9: + stob g4,-1073741312 +L14: +.stabn 68,0,25,LM10-_ledcyc +LM10: + ld -12(sp),g4 +.stabn 68,0,24,LM11-_ledcyc +LM11: + addo g5,1,g5 +.stabn 68,0,25,LM12-_ledcyc +LM12: + addo g4,g7,g4 + st g4,-16(sp) +.stabn 68,0,24,LM13-_ledcyc +LM13: + cmpibge g0,g5,L14 +.stabn 68,0,26,LM14-_ledcyc +LM14: + addo g6,1,g6 +.stabn 68,0,27,LM15-_ledcyc +LM15: + b L9 +.stabn 68,0,28,LM16-_ledcyc +LM16: +LBE2: +.stabs "k:(0,1)",128,0,17,-16 +.stabs "m:(0,1)",128,0,17,-12 +.stabn 192,0,0,LBB2-_ledcyc +.stabn 224,0,0,LBE2-_ledcyc + .align 4 +.stabs "copyCodeToRom:F(0,19)",36,0,31,_copyCodeToRom + .globl _copyCodeToRom + # Function 'copyCodeToRom' + # Registers used: g0 g1 g2 g3 g4 g5 g6 g7 cc + # + .globl copyCodeToRom.lf + .leafproc _copyCodeToRom,copyCodeToRom.lf +_copyCodeToRom: + lda LR2,g14 +copyCodeToRom.lf: + mov g14,g3 + mov 0,g14 +.stabn 68,0,31,LM17-_copyCodeToRom +LM17: +.stabn 68,0,32,LM18-_copyCodeToRom +LM18: +LBB3: +.stabn 68,0,40,LM19-_copyCodeToRom +LM19: + ldconst _codeRamStart,g6 +.stabn 68,0,41,LM20-_copyCodeToRom +LM20: + st g14,(g6) +.stabn 68,0,42,LM21-_copyCodeToRom +LM21: + ld (g6),g4 +.stabn 68,0,39,LM22-_copyCodeToRom +LM22: + mov 1,g2 +.stabn 68,0,42,LM23-_copyCodeToRom +LM23: + cmpobne 0,g4,L18 +.stabn 68,0,45,LM24-_copyCodeToRom +LM24: + subo 1,0,g5 # ldconst -1,g5 + st g5,(g6) +.stabn 68,0,46,LM25-_copyCodeToRom +LM25: + ld (g6),g4 +.stabn 68,0,44,LM26-_copyCodeToRom +LM26: + mov 2,g2 +.stabn 68,0,46,LM27-_copyCodeToRom +LM27: + cmpobne g5,g4,L18 +.stabn 68,0,48,LM28-_copyCodeToRom +LM28: + mov 3,g2 +.stabn 68,0,49,LM29-_copyCodeToRom +LM29: + mov 1,g5 +.stabn 68,0,50,LM30-_copyCodeToRom +LM30: + mov 0,g7 +L23: +.stabn 68,0,51,LM31-_copyCodeToRom +LM31: + st g5,(g6) +.stabn 68,0,52,LM32-_copyCodeToRom +LM32: + ld (g6),g4 + cmpobne g5,g4,L18 +.stabn 68,0,54,LM33-_copyCodeToRom +LM33: + shlo 1,g5,g5 +.stabn 68,0,50,LM34-_copyCodeToRom +LM34: + addo g7,1,g7 + cmpobge 30,g7,L23 +.stabn 68,0,56,LM35-_copyCodeToRom +LM35: + ldconst _codeRamStart,g5 +.stabn 68,0,57,LM36-_copyCodeToRom +LM36: + stob g14,(g5) +.stabn 68,0,58,LM37-_copyCodeToRom +LM37: + ldob (g5),g4 + cmpobne 0,g4,L18 +.stabn 68,0,60,LM38-_copyCodeToRom +LM38: + mov 15,g4 + stob g4,(g5) +.stabn 68,0,61,LM39-_copyCodeToRom +LM39: + ldob (g5),g4 + cmpobne 15,g4,L18 +.stabn 68,0,64,LM40-_copyCodeToRom +LM40: + ldconst _codeRomStart,g7 + mov g5,g6 + ldconst _codeRamEnd,g5 + cmpoble g5,g6,L29 +L31: +.stabn 68,0,65,LM41-_copyCodeToRom +LM41: + ld (g7),g4 + st g4,(g6) +.stabn 68,0,64,LM42-_copyCodeToRom +LM42: + addo g7,4,g7 + addo g6,4,g6 + cmpobg g5,g6,L31 +L29: +.stabn 68,0,67,LM43-_copyCodeToRom +LM43: + mov 5,g2 +.stabn 68,0,68,LM44-_copyCodeToRom +LM44: + ldconst _codeRomStart,g7 + ldconst _codeRamStart,g6 + ldconst _codeRamEnd,g0 + cmpoble g0,g6,L34 +L36: +.stabn 68,0,69,LM45-_copyCodeToRom +LM45: + ld (g6),g5 + ld (g7),g4 + cmpobne g4,g5,L18 +.stabn 68,0,68,LM46-_copyCodeToRom +LM46: + addo g7,4,g7 + addo g6,4,g6 + cmpobg g0,g6,L36 +L34: +.stabn 68,0,73,LM47-_copyCodeToRom +LM47: + bx (g3) +L18: +.stabn 68,0,76,LM48-_copyCodeToRom +LM48: + ld _led_array,g0 + ldconst 0xfffff,g1 + ldconst 0xc0000200,g7 +L41: +.stabn 68,0,77,LM49-_copyCodeToRom +LM49: + mov 1,g5 +L45: +.stabn 68,0,78,LM50-_copyCodeToRom +LM50: + stob g2,(g7) +.stabn 68,0,77,LM51-_copyCodeToRom +LM51: + addo g5,1,g5 + cmpobge g1,g5,L45 +.stabn 68,0,79,LM52-_copyCodeToRom +LM52: + mov 1,g5 + mov g1,g6 +L50: +.stabn 68,0,80,LM53-_copyCodeToRom +LM53: + ldob (g0),g4 +.stabn 68,0,79,LM54-_copyCodeToRom +LM54: + addo g5,1,g5 +.stabn 68,0,80,LM55-_copyCodeToRom +LM55: + stob g4,(g7) +.stabn 68,0,79,LM56-_copyCodeToRom +LM56: + cmpobge g6,g5,L50 +.stabn 68,0,81,LM57-_copyCodeToRom +LM57: + b L41 +.stabn 68,0,83,LM58-_copyCodeToRom +LM58: +LBE3: +LR2: ret +.stabs "errval:r(0,1)",64,0,32,18 +.stabs "s:r(0,20)=*(0,4)",64,0,33,23 +.stabs "d:r(0,21)=*(0,4)",64,0,34,22 +.stabs "t:r(0,4)",64,0,35,21 +.stabs "i:r(0,4)",64,0,35,23 +.stabs "z:r(0,22)=*(0,11)",64,0,36,21 +.stabn 192,0,0,LBB3-_copyCodeToRom +.stabn 224,0,0,LBE3-_copyCodeToRom + .align 4 +.stabs "zeroBss:F(0,19)",36,0,85,_zeroBss + .globl _zeroBss + # Function 'zeroBss' + # Registers used: g0 g4 g5 cc + # + .globl zeroBss.lf + .leafproc _zeroBss,zeroBss.lf +_zeroBss: + lda LR3,g14 +zeroBss.lf: + mov g14,g0 + mov 0,g14 +.stabn 68,0,85,LM59-_zeroBss +LM59: +.stabn 68,0,86,LM60-_zeroBss +LM60: +LBB4: +.stabn 68,0,90,LM61-_zeroBss +LM61: + ldconst _bssStart,g4 + ldconst _bssEnd,g5 + cmpoble g5,g4,L65 +L67: +.stabn 68,0,91,LM62-_zeroBss +LM62: + st g14,(g4) +.stabn 68,0,90,LM63-_zeroBss +LM63: + addo g4,4,g4 + cmpobg g5,g4,L67 +L65: +.stabn 68,0,93,LM64-_zeroBss +LM64: + ldconst _bssStart_1,g4 + ldconst _bssEnd_1,g5 + cmpoble g5,g4,L70 +L72: +.stabn 68,0,94,LM65-_zeroBss +LM65: + st g14,(g4) +.stabn 68,0,93,LM66-_zeroBss +LM66: + addo g4,4,g4 + cmpobg g5,g4,L72 + bx (g0) +L70: +.stabn 68,0,96,LM67-_zeroBss +LM67: +LBE4: + bx (g0) +LR3: ret +.stabn 192,0,0,LBB4-_zeroBss +.stabn 224,0,0,LBE4-_zeroBss + .text + .stabs "",100,0,0,Letext +Letext: diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/setvec.c b/c/src/lib/libbsp/i960/rxgen960/startup/setvec.c new file mode 100644 index 0000000000..2acd706ccd --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/setvec.c @@ -0,0 +1,202 @@ +/* set_vector + * + * This routine attempts to perform all "generic" interrupt initialization + * for the specified XINT line. + * + * INPUT: + * func - interrupt handler entry point + * xint - external interrupt line + * type - 0 indicates raw hardware connect + * 1 indicates RTEMS interrupt connect + * + * RETURNS: + * address of previous interrupt handler + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ +/* + * i960rp specific function added + */ + +#include <rtems.h> +#include <bsp.h> + +#include <stdio.h> + +void print_prcb(); +void print_intr_info(); +void print_ipnd_imsk(); + +unsigned int Xint_2_Group_Map[8] = { 0, 1, 2, 5, 7, 3, 6, 4 }; + +i960_isr_entry old_set_vector( /* returns old vector */ + rtems_isr_entry func, /* isr routine */ + unsigned int xint, /* XINT number */ + unsigned int type /* RTEMS or RAW */ +) +{ + i960_isr_entry *intr_tbl, *cached_intr_tbl; + i960_isr_entry saved_intr; + unsigned int vector, group, nibble; + unsigned int *imap; + + if ( xint > 7 ) + exit( 0x80 ); + + cached_intr_tbl = (i960_isr_entry *) 0; + intr_tbl = (i960_isr_entry *) Prcb->intr_tbl; + group = Xint_2_Group_Map[xint]; /* remap XINT to group */ + vector = (group << 4) + 2; /* direct vector num */ + + if ( type ) + rtems_interrupt_catch( func, vector, (rtems_isr_entry *) &saved_intr ); + else { + saved_intr = (i960_isr_entry) intr_tbl[ vector ]; + /* return old vector */ + intr_tbl[ vector + 1 ] = /* normal vector table */ + cached_intr_tbl[ group ] = (i960_isr_entry) func; /* cached vector */ + } + + if ( xint <= 3 ) imap = &Ctl_tbl->imap0; /* updating IMAP0 */ + else imap = &Ctl_tbl->imap1; /* updating IMAP1 */ + nibble = (xint % 4) * 4; + *imap &= ~(0xf << nibble); + *imap |= group << nibble; + + Ctl_tbl->icon &= ~0x00000400; /* enable global interrupts */ + Ctl_tbl->icon |= 0x00004000; /* fast sampling mode */ + switch ( xint ) { + case 0: Ctl_tbl->icon |= 0x00000004; break; + case 1: Ctl_tbl->icon |= 0x00000008; break; + case 2: Ctl_tbl->icon &= ~0x00000010; break; + case 4: Ctl_tbl->icon &= ~0x00000040; break; + case 5: Ctl_tbl->icon |= 0x00000080; break; + case 6: Ctl_tbl->icon &= ~0x00000100; break; + default: exit( 0x81 ); break; /* unsupported */ + } + +#if defined (i960ca) + if ( xint == 4 ) { /* reprogram MCON for SQSIO4 */ + Ctl_tbl->mcon12 = 0x00002012; /* MCON12 - 0xCxxxxxxx */ + Ctl_tbl->mcon13 = 0x00000000; /* MCON13 - 0xDxxxxxxx */ + i960_reload_ctl_group( 5 ); /* update MCON12-MCON15 */ + } +#endif; + + i960_unmask_intr( xint ); /* update IMSK */ + i960_reload_ctl_group( 1 ); /* update IMAP?/ICON */ + return( saved_intr ); /* return old vector */ +} + +/* note: this needs a little fix up work for XINTs */ +i960_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry func, /* isr routine */ + unsigned int vector, /* vector number */ + unsigned int type /* RTEMS or RAW */ +) +{ + i960_isr_entry *intr_tbl, *cached_intr_tbl; + i960_isr_entry saved_intr; + unsigned int vect_idx, group, nibble; + unsigned int *imap; + unsigned int imask; + unsigned int vec_idx; + volatile unsigned int *ipnd = (unsigned int *) IPND_ADDR; + volatile unsigned int *imsk = (unsigned int *) IMSK_ADDR; + + + cached_intr_tbl = (i960_isr_entry *) 0; + intr_tbl = (i960_isr_entry *) Prcb->intr_tbl; + + vec_idx = vector >> 4; + if ( type ) + { + rtems_interrupt_catch( func, vector, (rtems_isr_entry *) &saved_intr ); + return (saved_intr); + } + else { + saved_intr = (i960_isr_entry) intr_tbl[ vect_idx ]; + /* return old vector */ + intr_tbl[ vector ] = /* normal vector table */ + cached_intr_tbl[ vec_idx ] = (i960_isr_entry) func; /* cached vector */ + } + + if( vec_idx > 8) + imask = 0x1000 << (vec_idx - 9); + else + imask = 0x1 << (vec_idx - 1); + *ipnd &= ~(imask); + *imsk |= (imask); + + return( saved_intr ); /* return old vector */ +} + +i960_isr_entry set_tmr_vector( /* returns old vector */ + rtems_isr_entry func, /* isr routine */ + unsigned int vector, /* vector number */ + unsigned int tmrno /* which timer? */ +) +{ +#if defined(i960ca) + saved_intr = NULL; +#else + volatile i960_isr_entry *intr_tbl; + volatile i960_isr_entry saved_intr; + volatile unsigned int *imap2 = (unsigned int *) IMAP2_ADDR; + volatile unsigned int *isr = (unsigned int *) (4*(vector >> 4)); + + intr_tbl = (i960_isr_entry *) Prcb->intr_tbl; + saved_intr = (i960_isr_entry) intr_tbl[ vector ]; + intr_tbl[vector] = (((int) func) | 0x2); /* set IN_CACHE_IH flag */ + *isr = (unsigned int) func | 0x2; + + if (tmrno) /* timer 1 */ + { + *imap2 = (*imap2 & 0xff0fffff) | (((vector >> 4) & 0xf) << 20); + } + else /* timer 0 */ + { + *imap2 = (*imap2 & 0xfff0ffff) | (((vector >> 4) & 0xf) << 16); + } + +#endif + return( saved_intr ); /* return old vector */ +} + +void print_prcb() +{ + printf( "fault_table =0x%p\n", Prcb->fault_tbl ); + printf( "control_tbl =0x%p\n", Prcb->control_tbl ); + printf( "AC mask ov =0x%x\n", Prcb->initial_ac ); + printf( "fltconfig =0x%x\n", Prcb->fault_config ); + printf( "intr tbl =0x%p\n", Prcb->intr_tbl ); + printf( "systable =0x%p\n", Prcb->sys_proc_tbl ); + printf( "reserved =0x%x\n", Prcb->reserved ); + printf( "isr stk =0x%p\n", Prcb->intr_stack ); + printf( "ins cache =0x%x\n", Prcb->ins_cache_cfg ); + printf( "reg cache =0x%x\n", Prcb->reg_cache_cfg ); +} + +void print_intr_info() +{ + printf( "prcb =0x%p\n", Prcb ); + printf( "ctl_tbl =0x%p\n", Ctl_tbl ); + printf( "intr_tbl=0x%p\n", Prcb->intr_tbl ); + printf( "IMAP0 = 0x%x\n", Ctl_tbl->imap0 ); + printf( "IMAP1 = 0x%x\n", Ctl_tbl->imap1 ); + print_ipnd_imsk(); +} + +void print_ipnd_imsk() +{ + printf(" IPEND = 0x%x\n", i960_pend_intrs() ); + printf(" IMASK = 0x%x\n", i960_mask_intrs() ); +} diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/systbl.c b/c/src/lib/libbsp/i960/rxgen960/startup/systbl.c new file mode 100644 index 0000000000..05031ab2e0 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/systbl.c @@ -0,0 +1,97 @@ +/*-------------------------------------*/ +/* systbl.c */ +/* Last change : 21. 3.95 */ +/*-------------------------------------*/ +#include "prcb.h" +/*#include "uart_access.h" */ +#include "fault.h" +#include "faultret.h" +#include "memchnl.h" +#include "main.h" +/*#include "string_impl.h"*/ +#include "stdio.h" +/* #include "stdio_impl.h" */ +#include "systbl.h" +#include "time.h" +/*-------------------------------------*/ + +struct PRCB *sys_get_prcb() +{ + register struct PRCB *prcb = &ram_prcb; + + return(prcb); + /*asm volatile("lda _ram_prcb, g0" : : ); */ +} + + /* System Procedures Table. + */ +SystemTbl systemTbl = { + {0, 0, 0}, /* Reserved */ + svrStackPtr, /* Supervisor Stack Pointer Base */ + {0, 0, 0, 0, 0, 0, 0, 0}, /* Preserved */ + {0, 0, 0, 0, 0, + SP(sys_get_prcb + SUPERVISOR_SP), + 0, 0, /* 6 - 7 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 8 - 15 */ + 0, 0, /* 16 - 17 */ + 0, /* 18 */ + 0, /* 19 */ + 0, /* 20 */ + 0, /* 21 */ + 0, 0, /* 22 - 23 */ + 0, /* 24 */ + 0, /* 25 */ + 0, /* 26 */ + 0, /* 27 */ + 0, /* 28 */ + 0, /* 29 */ + 0, /* 30 */ + 0, /* 31 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 32 - 39 */ + 0, /* 40 */ + 0, /* 41 */ + 0, /* 42 */ + 0, /* 43 */ + 0, /* 44 */ + 0, /* 45 */ + 0, /* 46 */ + 0, /* 47 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* 48 - 55 */ + 0, /* 56 */ + 0, /* 57 */ + 0, /* 58 */ + 0, 0, 0, 0, 0, /* 59 - 63 */ + 0, /* 64 */ + 0, /* 65 */ + 0, 0, 0, 0, 0, 0, /* 66 - 71 */ + 0, /* 72 */ + 0, /* 73 */ + 0, /* 74 */ + 0, /* 75 */ + 0, /* 76 */ + 0, /* 77 */ + 0, 0, /* 78 - 79 */ + 0, /* 80 */ + 0, /* 81 */ + 0, 0, 0, 0, 0, 0, /* 82 - 87 */ + 0, /* 88 */ + 0, 0, 0, 0, 0, 0, 0, /* 89 - 95 */ + 0, /* 96 */ + 0, /* 97 */ + 0, 0, 0, 0, 0, 0, /* 98 - 103 */ + 0, /* 104 */ + 0, /* 105 */ + 0, /* 106 */ + 0, /* 107 */ + 0, /* 108 */ + 0, /* 109 */ + 0, 0, /* 110 - 111 */ + 0, /* 112 */ + 0, /* 113 */ + 0} /* 114 */ +}; + +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/systbl.h b/c/src/lib/libbsp/i960/rxgen960/startup/systbl.h new file mode 100644 index 0000000000..a69865a86b --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/systbl.h @@ -0,0 +1,34 @@ +/*-------------------------------------*/ +/* systbl.h */ +/* Last change : 14.10.94 */ +/*-------------------------------------*/ +#ifndef _SYSTBL_H_ +#define _SYSTBL_H_ + + /* System Procedure. + */ +typedef void (* SysProc)(void); + /* System Procedures Table. + */ +typedef struct { + unsigned int reserved[3]; /* Reserved */ + unsigned int * svrStackPtr; /* Supervisor Stack Pointer Base */ + unsigned int preserved[8]; /* Preserved */ + SysProc sysProc[259]; /* System Procedures Entry Points */ +} SystemTbl; + /* Type of System Procedure. + */ +#define LOCAL_SP 0x0 +#define SUPERVISOR_SP 0x2 + /* Cinvert to System Procedure Type. + */ +#define SP(addr) ((SysProc) (addr)) + /* System Procedures Table Itself. + */ +extern SystemTbl systemTbl; + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/systbl.s b/c/src/lib/libbsp/i960/rxgen960/startup/systbl.s new file mode 100644 index 0000000000..afa52bc350 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/systbl.s @@ -0,0 +1,289 @@ + .file "systbl.c" +gcc2_compiled.: +___gnu_compiled_c: +.text + .def _.0fake; .scl 10; .type 0x8; .size 8; .endef + .def _hndl; .val 0; .scl 8; .type 0x121; .endef + .def _type; .val 4; .scl 8; .type 0xe; .endef + .def .eos; .val 8; .scl 102; .tag _.0fake; .size 8; .endef + .def _FaultTblEntry; .scl 13; .tag _.0fake; .size 8; .tag _.0fake; .size 8; .type 0x8; .endef + .def _ControlTblEntry; .scl 13; .type 0xe; .endef + .def _IntrHndl; .scl 13; .type 0x121; .endef + .def _.1fake; .scl 10; .type 0x8; .size 1028; .endef + .def _pendPrty; .val 0; .scl 8; .type 0xe; .endef + .def _pendIntr; .val 4; .scl 8; .dim 8; .size 32; .dim 8; .size 32; .type 0x6e; .endef + .def _intrHndl; .val 36; .scl 8; .dim 248; .size 992; .dim 248; .size 992; .type 0x4e1; .endef + .def .eos; .val 1028; .scl 102; .tag _.1fake; .size 1028; .endef + .def _InterruptTbl; .scl 13; .tag _.1fake; .size 1028; .tag _.1fake; .size 1028; .type 0x8; .endef + .def _SysProc; .scl 13; .type 0x121; .endef + .def _.2fake; .scl 10; .type 0x8; .size 1084; .endef + .def _reserved; .val 0; .scl 8; .dim 3; .size 12; .dim 3; .size 12; .type 0x6e; .endef + .def _svrStackPtr; .val 12; .scl 8; .type 0x2e; .endef + .def _preserved; .val 16; .scl 8; .dim 8; .size 32; .dim 8; .size 32; .type 0x6e; .endef + .def _sysProc; .val 48; .scl 8; .dim 259; .size 1036; .dim 259; .size 1036; .type 0x4e1; .endef + .def .eos; .val 1084; .scl 102; .tag _.2fake; .size 1084; .endef + .def _SystemTbl; .scl 13; .tag _.2fake; .size 1084; .tag _.2fake; .size 1084; .type 0x8; .endef + .def _PRCB; .scl 10; .type 0x8; .size 40; .endef + .def _faultTbl; .val 0; .scl 8; .tag _.0fake; .size 8; .tag _.0fake; .size 8; .type 0x28; .endef + .def _controlTbl; .val 4; .scl 8; .type 0x2e; .endef + .def _arithConfig; .val 8; .scl 8; .type 0xe; .endef + .def _faultConfig; .val 12; .scl 8; .type 0xe; .endef + .def _interruptTbl; .val 16; .scl 8; .tag _.1fake; .size 1028; .tag _.1fake; .size 1028; .type 0x28; .endef + .def _systemTbl; .val 20; .scl 8; .tag _.2fake; .size 1084; .tag _.2fake; .size 1084; .type 0x28; .endef + .def _reserved; .val 24; .scl 8; .type 0xe; .endef + .def _intStackPtr; .val 28; .scl 8; .type 0x2e; .endef + .def _instCacheConfig; .val 32; .scl 8; .type 0xe; .endef + .def _regCacheConfig; .val 36; .scl 8; .type 0xe; .endef + .def .eos; .val 40; .scl 102; .tag _PRCB; .size 40; .endef + .def _UserFaultHandler; .scl 13; .type 0x121; .endef + .def _memMsg; .scl 10; .type 0x8; .size 4; .endef + .def _foo; .val 0; .scl 8; .type 0x24; .endef + .def .eos; .val 4; .scl 102; .tag _memMsg; .size 4; .endef + .def _IOTrCBlk; .scl 13; .tag _memMsg; .size 4; .tag _memMsg; .size 4; .type 0x8; .endef + .def _iotrcb_ptr_t; .scl 13; .tag _memMsg; .size 4; .tag _memMsg; .size 4; .type 0x28; .endef + .def _iotrcb_sgm_t; .scl 13; .type 0x21; .endef + .def _IotHandler; .scl 13; .type 0x121; .endef + .def _.3fake; .scl 10; .type 0x8; .size 16; .endef + .def _ptr_len; .val 0; .scl 8; .type 0x4; .endef + .def _ptr_loc; .val 4; .scl 8; .tag _memMsg; .size 4; .tag _memMsg; .size 4; .type 0x28; .endef + .def _ptr_crnt; .val 8; .scl 8; .tag _memMsg; .size 4; .tag _memMsg; .size 4; .type 0xa8; .endef + .def _sgm_crnt; .val 12; .scl 8; .type 0xa1; .endef + .def .eos; .val 16; .scl 102; .tag _.3fake; .size 16; .endef + .def _BufLookupHndl; .scl 13; .tag _.3fake; .size 16; .tag _.3fake; .size 16; .type 0x8; .endef + .def ___int32_t; .scl 13; .type 0x4; .endef + .def ___uint32_t; .scl 13; .type 0xe; .endef + .def _size_t; .scl 13; .type 0xf; .endef + .def ___gnuc_va_list; .scl 13; .dim 2; .size 8; .dim 2; .size 8; .type 0x6e; .endef + .def __glue; .scl 10; .type 0x8; .size 12; .endef + .def __next; .val 0; .scl 8; .tag __glue; .size 12; .tag __glue; .size 12; .type 0x28; .endef + .def __niobs; .val 4; .scl 8; .type 0x4; .endef + .def __iobs; .val 8; .scl 8; .type 0x28; .endef + .def .eos; .val 12; .scl 102; .tag __glue; .size 12; .endef + .def __Bigint; .scl 10; .type 0x8; .size 24; .endef + .def __next; .val 0; .scl 8; .tag __Bigint; .size 24; .tag __Bigint; .size 24; .type 0x28; .endef + .def __k; .val 4; .scl 8; .type 0x4; .endef + .def __maxwds; .val 8; .scl 8; .type 0x4; .endef + .def __sign; .val 12; .scl 8; .type 0x4; .endef + .def __wds; .val 16; .scl 8; .type 0x4; .endef + .def __x; .val 20; .scl 8; .dim 1; .size 4; .dim 1; .size 4; .type 0x6f; .endef + .def .eos; .val 24; .scl 102; .tag __Bigint; .size 24; .endef + .def __atexit; .scl 10; .type 0x8; .size 136; .endef + .def __next; .val 0; .scl 8; .tag __atexit; .size 136; .tag __atexit; .size 136; .type 0x28; .endef + .def __ind; .val 4; .scl 8; .type 0x4; .endef + .def __fns; .val 8; .scl 8; .dim 32; .size 128; .dim 32; .size 128; .type 0x4e1; .endef + .def .eos; .val 136; .scl 102; .tag __atexit; .size 136; .endef + .def ___sbuf; .scl 10; .type 0x8; .size 8; .endef + .def __base; .val 0; .scl 8; .type 0x2c; .endef + .def __size; .val 4; .scl 8; .type 0x4; .endef + .def .eos; .val 8; .scl 102; .tag ___sbuf; .size 8; .endef + .def __fpos_t; .scl 13; .type 0x5; .endef + .def ___sFILE; .scl 10; .type 0x8; .size 92; .endef + .def __p; .val 0; .scl 8; .type 0x2c; .endef + .def __r; .val 4; .scl 8; .type 0x4; .endef + .def __w; .val 8; .scl 8; .type 0x4; .endef + .def __flags; .val 12; .scl 8; .type 0x3; .endef + .def __file; .val 14; .scl 8; .type 0x3; .endef + .def __bf; .val 16; .scl 8; .tag ___sbuf; .size 8; .tag ___sbuf; .size 8; .type 0x8; .endef + .def __lbfsize; .val 24; .scl 8; .type 0x4; .endef + .def __cookie; .val 28; .scl 8; .type 0x21; .endef + .def __read; .val 32; .scl 8; .type 0x124; .endef + .def __write; .val 36; .scl 8; .type 0x124; .endef + .def __seek; .val 40; .scl 8; .type 0x125; .endef + .def __close; .val 44; .scl 8; .type 0x124; .endef + .def __ub; .val 48; .scl 8; .tag ___sbuf; .size 8; .tag ___sbuf; .size 8; .type 0x8; .endef + .def __up; .val 56; .scl 8; .type 0x2c; .endef + .def __ur; .val 60; .scl 8; .type 0x4; .endef + .def __ubuf; .val 64; .scl 8; .dim 3; .size 3; .dim 3; .size 3; .type 0x6c; .endef + .def __nbuf; .val 67; .scl 8; .dim 1; .size 1; .dim 1; .size 1; .type 0x6c; .endef + .def __lb; .val 72; .scl 8; .tag ___sbuf; .size 8; .tag ___sbuf; .size 8; .type 0x8; .endef + .def __blksize; .val 80; .scl 8; .type 0x4; .endef + .def __offset; .val 84; .scl 8; .type 0x4; .endef + .def __data; .val 88; .scl 8; .type 0x28; .endef + .def .eos; .val 92; .scl 102; .tag ___sFILE; .size 92; .endef + .def __reent; .scl 10; .type 0x8; .size 820; .endef + .def __errno; .val 0; .scl 8; .type 0x4; .endef + .def __stdin; .val 4; .scl 8; .tag ___sFILE; .size 92; .tag ___sFILE; .size 92; .type 0x28; .endef + .def __stdout; .val 8; .scl 8; .tag ___sFILE; .size 92; .tag ___sFILE; .size 92; .type 0x28; .endef + .def __stderr; .val 12; .scl 8; .tag ___sFILE; .size 92; .tag ___sFILE; .size 92; .type 0x28; .endef + .def __scanpoint; .val 16; .scl 8; .type 0x2c; .endef + .def __asctime; .val 20; .scl 8; .dim 26; .size 26; .dim 26; .size 26; .type 0x6c; .endef + .def __next; .val 48; .scl 8; .type 0x5; .endef + .def __inc; .val 52; .scl 8; .type 0x4; .endef + .def __emergency; .val 56; .scl 8; .dim 25; .size 25; .dim 25; .size 25; .type 0x6c; .endef + .def __current_category; .val 84; .scl 8; .type 0x4; .endef + .def __current_locale; .val 88; .scl 8; .type 0x2c; .endef + .def ___sdidinit; .val 92; .scl 8; .type 0x4; .endef + .def ___cleanup; .val 96; .scl 8; .type 0x121; .endef + .def __result; .val 100; .scl 8; .tag __Bigint; .size 24; .tag __Bigint; .size 24; .type 0x28; .endef + .def __result_k; .val 104; .scl 8; .type 0x4; .endef + .def __p5s; .val 108; .scl 8; .tag __Bigint; .size 24; .tag __Bigint; .size 24; .type 0x28; .endef + .def __freelist; .val 112; .scl 8; .tag __Bigint; .size 24; .tag __Bigint; .size 24; .type 0xa8; .endef + .def __signgam; .val 116; .scl 8; .type 0x4; .endef + .def __cvtlen; .val 120; .scl 8; .type 0x4; .endef + .def __cvtbuf; .val 124; .scl 8; .type 0x2c; .endef + .def __nextf; .val 128; .scl 8; .dim 30; .size 120; .dim 30; .size 120; .type 0xec; .endef + .def __nmalloc; .val 248; .scl 8; .dim 30; .size 120; .dim 30; .size 120; .type 0x6e; .endef + .def __atexit; .val 368; .scl 8; .tag __atexit; .size 136; .tag __atexit; .size 136; .type 0x28; .endef + .def __atexit0; .val 384; .scl 8; .tag __atexit; .size 136; .tag __atexit; .size 136; .type 0x8; .endef + .def __sig_func; .val 520; .scl 8; .type 0x4a1; .endef + .def ___sglue; .val 528; .scl 8; .tag __glue; .size 12; .tag __glue; .size 12; .type 0x8; .endef + .def ___sf; .val 544; .scl 8; .tag ___sFILE; .dim 3; .size 276; .tag ___sFILE; .dim 3; .size 276; .type 0x68; .endef + .def .eos; .val 820; .scl 102; .tag __reent; .size 820; .endef + .def _fpos_t; .scl 13; .type 0x5; .endef + .def _FILE; .scl 13; .tag ___sFILE; .size 92; .tag ___sFILE; .size 92; .type 0x8; .endef + .align 4 + .def _sys_get_prcb; .val _sys_get_prcb; .scl 2; .tag _PRCB; .size 40; .tag _PRCB; .size 40; .type 0xc8; .endef + .globl _sys_get_prcb + # Function 'sys_get_prcb' + # Registers used: g0 g1 + .globl sys_get_prcb.lf + .leafproc _sys_get_prcb,sys_get_prcb.lf +_sys_get_prcb: + lda LR1,g14 +sys_get_prcb.lf: + mov g14,g1 + lda 0,g14 + .def .bf; .val .; .scl 101; .line 19; .endef + .ln 2 + .ln 4 + ldconst _ram_prcb,g0 + bx (g1) + .align 3 + .ln 6 + .def .ef; .val .; .scl 101; .line 6; .endef +LR1: ret + .def _sys_get_prcb; .val .; .scl -1; .endef + .globl _systemTbl +.data + .align 4 +_systemTbl: + .word 0 + .word 0 + .word 0 + .word _svrStackPtr + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word _sys_get_prcb+2 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .space 576 +.text + .def _systemTbl; .val _systemTbl; .scl 2; .tag _.2fake; .size 1084; .tag _.2fake; .size 1084; .type 0x8; .endef diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/time.h b/c/src/lib/libbsp/i960/rxgen960/startup/time.h new file mode 100644 index 0000000000..406dbf90f5 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/time.h @@ -0,0 +1,2 @@ + extern void gettime_impl(void); + extern void gettime_us_impl(void); diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/types.h b/c/src/lib/libbsp/i960/rxgen960/startup/types.h new file mode 100644 index 0000000000..190bb027c1 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/types.h @@ -0,0 +1,34 @@ +/* Type definitions for our use */ +#ifndef __TYPES_H +#define __TYPES_H +typedef unsigned char u8; +typedef unsigned int u32; +typedef unsigned short u16; +typedef unsigned char uchar; +typedef unsigned int Int32; +typedef unsigned short Int16; +typedef unsigned char Int8; +typedef unsigned int u_int; +typedef unsigned int u_long; +typedef unsigned short u_short; +typedef unsigned char u_char; +#ifndef NULL +#define NULL 0 +#endif +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif +/* + * Definitions of unsigned amounts + */ +#define ub Int8 +#define uw Int16 +#define ul Int64 +#define sl long +#define ui Int32 + + +#endif |