diff options
Diffstat (limited to 'c/src/lib/libbsp/i386/i386ex/start/start.S')
| -rw-r--r-- | c/src/lib/libbsp/i386/i386ex/start/start.S | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/c/src/lib/libbsp/i386/i386ex/start/start.S b/c/src/lib/libbsp/i386/i386ex/start/start.S index 999c161b9b..6f515243de 100644 --- a/c/src/lib/libbsp/i386/i386ex/start/start.S +++ b/c/src/lib/libbsp/i386/i386ex/start/start.S @@ -28,19 +28,16 @@ * * $Id$ - changes: SetExRegByte(ICW3S , 0x02 ) # MUST be 0x02 according to intel SetExRegByte(ICW3M , 0x04 ) # IR2 is cascaded internally: was 0x02 => IR1 is cascaded */ - #include <rtems/asm.h> #include "macros.inc" #include "80386ex.inc" - /* * NEW_GAS Needed for binutils 2.9.1.0.7 and higher */ @@ -76,7 +73,6 @@ SYM(GDT_END): END_DATA - /* This section is the section that is used by the interrupt descriptor table. It is used to provide the IDT with the correct vector offsets. It is for symbol definition only. @@ -131,7 +127,6 @@ SYM(A20): orb $0x02 , al # Bit 1 Fast A20 = 0 (always 0) else enabled. outb al , dx - SYM(Watchdog): movw $WDTSTATUS , dx # address the WDT status port inb dx , al # get the WDT status @@ -284,7 +279,6 @@ SYM(InitTimer): SetExRegByte(TMR0 , 0x00 ) # sfa SetExRegByte(TMR0 , 0x00 ) # sfa - SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc SetExRegByte(TMR1 , 0x00 ) # sfa SetExRegByte(TMR1 , 0x00 ) # sfa @@ -342,7 +336,6 @@ SYM(InitInt): # for IR0 and IR2 use 0xfa SetExRegByte(INTCFG , 0x00 ) - SYM(SetCS4): SetExRegWord(CS4ADL , 0x702) #Configure chip select 4 SetExRegWord(CS4ADH , 0x00) @@ -383,7 +376,6 @@ SYM(SetUCS1): lgdt SYM(GDTR) # location of GDT #endif - SYM(SetUCS): SetExRegWord(UCSADL, 0x0702) # now 512K starting at 0x3f80000. SetExRegWord(UCSADH, 0x03f8) @@ -472,7 +464,6 @@ SYM (zero_bss): repne # while ecx != 0 stosl # clear a long in the bss - /* * Transfer control to User's Board Support Package */ |