1 files changed, 144 insertions, 6 deletions

diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c b/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c
index 2d27e8c2fb..6a062c9309 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/start-config-emc-dynamic.c
@@ -25,9 +25,9 @@
 #include <bsp/start-config.h>
 #include <bsp/lpc24xx.h>
 
-const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_config
+BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
   lpc24xx_start_config_emc_dynamic [] = {
-#if defined(LPC24XX_EMC_MICRON)
+#if defined(LPC24XX_EMC_MT48LC4M16A2)
   /* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
   {
     /* Auto-refresh command every 15.6 us */
@@ -69,6 +69,48 @@ const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_config
     /* Load mode register to active or refresh command period 2 tCK */
     .tmrd = 1
   }
+#elif defined(LPC24XX_EMC_W9825G2JB75I)
+  /* Dynamic Memory 0: Winbond W9825G2JB75I at 51612800Hz (tCK = 19.4ns) */
+  {
+    /* (n * 16) clock cycles -> 15.5us <= 15.6 us */
+    .refresh = 50,
+
+    /* Use command delayed strategy */
+    .readconfig = 1,
+
+    /* (n + 1) clock cycles -> 38.8ns >= 20ns */
+    .trp = 1,
+
+    /* (n + 1) clock cycles -> 58.1ns >= 45ns */
+    .tras = 2,
+
+    /* (n + 1) clock cycles -> 77.5ns >= 75ns (tXSR) */
+    .tsrex = 3,
+
+    /* (n + 1) clock cycles -> 38.8ns >= 20ns (tRCD) */
+    .tapr = 1,
+
+    /* n clock cycles -> 77.5ns >= tWR + tRP -> 2 * tCK + 20ns */
+    .tdal = 4,
+
+    /* (n + 1) clock cycles == 2 * tCK */
+    .twr = 1,
+
+    /* (n + 1) clock cycles = 77.5ns >= 65ns */
+    .trc = 3,
+
+    /* (n + 1) clock cycles = 77.5ns >= 65ns (tRC) */
+    .trfc = 3,
+
+    /* (n + 1) clock cycles = 77.5ns >= 75ns */
+    .txsr = 3,
+
+    /* (n + 1) clock cycles == 2 * tCK */
+    .trrd = 1,
+
+    /* (n + 1) clock cycles == 2 * tCK (tRSC)*/
+    .tmrd = 1
+  }
 #elif defined(LPC24XX_EMC_K4S561632E)
   {
     .refresh = 35,
@@ -85,24 +127,103 @@ const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_config
     .trrd = 3,
     .tmrd = 2
   }
+#elif defined(LPC24XX_EMC_IS42S32800B)
+  #if LPC24XX_EMCCLK == 72000000U
+    {
+      /* tCK = 13.888ns at 72MHz */
+
+      /* (n * 16) clock cycles -> 15.556us <= 15.6us */
+      .refresh = 70,
+
+      .readconfig = 1,
+
+      /* (n + 1) clock cycles -> 27.8ns >= 20ns */
+      .trp = 1,
+
+      /* (n + 1) clock cycles -> 55.5ns >= 45ns */
+      .tras = 3,
+
+      /* (n + 1) clock cycles -> 69.4ns >= 70ns (tRC) */
+      .tsrex = 5,
+
+      /* (n + 1) clock cycles -> 41.7ns >= FIXME */
+      .tapr = 2,
+
+      /* n clock cycles -> 55.5ns >= tWR + tRP = 47.8ns */
+      .tdal = 4,
+
+      /* (n + 1) clock cycles == 2 * tCK */
+      .twr = 1,
+
+      /* (n + 1) clock cycles -> 83.3ns >= 70ns */
+      .trc = 5,
+
+      /* (n + 1) clock cycles -> 83.3ns >= 70ns */
+      .trfc = 5,
+
+      /* (n + 1) clock cycles -> 69.4ns >= 70ns (tRC) */
+      .txsr = 5,
+
+      /* (n + 1) clock cycles -> 27.8ns >= 14ns */
+      .trrd = 1,
+
+      /* (n + 1) clock cycles == 2 * tCK */
+      .tmrd = 1,
+
+      /* FIXME */
+      .emcdlyctl = 0x1112
+    }
+  #elif LPC24XX_EMCCLK == 60000000U
+    {
+      .refresh = 0x3a,
+      .readconfig = 1,
+      .trp = 1,
+      .tras = 3,
+      .tsrex = 5,
+      .tapr = 2,
+      .tdal = 3,
+      .twr = 1,
+      .trc = 4,
+      .trfc = 4,
+      .txsr = 5,
+      .trrd = 1,
+      .tmrd = 1,
+      .emcdlyctl = 0x1112
+    }
+  #else
+    #error "unexpected EMCCLK"
+  #endif
 #endif
 };
 
-const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_chip_config
+BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
   lpc24xx_start_config_emc_dynamic_chip [] = {
-#if defined(LPC24XX_EMC_MICRON)
+#if defined(LPC24XX_EMC_MT48LC4M16A2)
   {
     .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
 
     /*
      * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected
-     * writes.
+     * writes.  4 banks, 12 row lines, 8 column lines.
      */
     .config = 0x280,
 
     .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
     .mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
   }
+#elif defined(LPC24XX_EMC_W9825G2JB75I)
+  {
+    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
+
+    /* 32-bit data bus, 4 banks, 12 row lines, 9 column lines, RBC */
+    .config = 0x4280,
+
+    /* RAS based on tRCD = 20ns */
+    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
+
+    /* CAS 2, burst length 8, */
+    .mode = 0xa0000000 | (0x23 << (2 + 2 + 9))
+  }
 #elif defined(LPC24XX_EMC_K4S561632E)
   {
     .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
@@ -110,10 +231,27 @@ const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_chip_config
     .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
     .mode = 0xa0000000 | (0x33 << 12)
   }
+#elif defined(LPC24XX_EMC_IS42S32800B)
+  {
+    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
+
+    /* 256MBit, 8Mx32, 4 banks, row = 12, column = 9, RBC */
+    .config = 0x4480,
+
+    #if LPC24XX_EMCCLK == 72000000U
+      .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
+      .mode = 0xa0000000 | (0x32 << (2 + 2 + 9))
+    #elif LPC24XX_EMCCLK == 60000000U
+      .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
+      .mode = 0xa0000000 | (0x22 << (2 + 2 + 9))
+    #else
+      #error "unexpected EMCCLK"
+    #endif
+  }
 #endif
 };
 
-const BSP_START_DATA_SECTION size_t
+BSP_START_DATA_SECTION const size_t
   lpc24xx_start_config_emc_dynamic_chip_count =
     sizeof(lpc24xx_start_config_emc_dynamic_chip)
       / sizeof(lpc24xx_start_config_emc_dynamic_chip [0]);