diff options
Diffstat (limited to 'c/src/lib/include/zilog')
| -rw-r--r-- | c/src/lib/include/zilog/z8036.h | 109 | ||||
| -rw-r--r-- | c/src/lib/include/zilog/z8530.h | 99 | ||||
| -rw-r--r-- | c/src/lib/include/zilog/z8536.h | 112 |
3 files changed, 320 insertions, 0 deletions
diff --git a/c/src/lib/include/zilog/z8036.h b/c/src/lib/include/zilog/z8036.h new file mode 100644 index 0000000000..b2b2c073cb --- /dev/null +++ b/c/src/lib/include/zilog/z8036.h @@ -0,0 +1,109 @@ +/* z8036.h + * + * This include file defines information related to a Zilog Z8036 + * Counter/Timer/IO Chip. It is a memory mapped part. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * NOTE: This file shares as much as possible with the include + * file for the Z8536 via z8x36.h. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __Z8036_h +#define __Z8036_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* macros */ + +#define Z8036( ptr ) ((volatile struct z8036_map *)(ptr)) + +#define Z8x36_STATE0 ( z8036 ) \ + { /*char *garbage = *(Z8036(z8036))->???; */ } + + +#define Z8x36_WRITE( z8036, reg, data ) \ + (Z8036(z8036))->reg = (data) + + +#define Z8x36_READ( z8036, reg, data ) \ + (Z8036(z8036))->reg = (data) + +/* structures */ + +struct z8036_map { +/* MAIN CONTROL REGISTERS (0x00-0x07) */ + rtems_unsigned8 MASTER_INTR; /* Master Interrupt Ctl Reg */ + rtems_unsigned8 MASTER_CFG; /* Master Configuration Ctl Reg */ + rtems_unsigned8 PORTA_VECTOR; /* Port A - Interrupt Vector */ + rtems_unsigned8 PORTB_VECTOR; /* Port B - Interrupt Vector */ + rtems_unsigned8 CNT_TMR_VECTOR; /* Counter/Timer Interrupt Vector */ + rtems_unsigned8 PORTC_DATA_POLARITY; /* Port C - Data Path Polarity */ + rtems_unsigned8 PORTC_DIRECTION; /* Port C - Data Direction */ + rtems_unsigned8 PORTC_SPECIAL_IO_CTL; /* Port C - Special IO Control */ +/* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */ + rtems_unsigned8 PORTA_CMD_STATUS; /* Port A - Command Status Reg */ + rtems_unsigned8 PORTB_CMD_STATUS; /* Port B - Command Status Reg */ + rtems_unsigned8 CT1_CMD_STATUS; /* Ctr/Timer 1 - Command Status Reg */ + rtems_unsigned8 CT2_CMD_STATUS; /* Ctr/Timer 2 - Command Status Reg */ + rtems_unsigned8 CT3_CMD_STATUS; /* Ctr/Timer 3 - Command Status Reg */ + rtems_unsigned8 PORTA_DATA; /* Port A - Data */ + rtems_unsigned8 PORTB_DATA; /* Port B - Data */ + rtems_unsigned8 PORTC_DATA; /* Port C - Data */ +/* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */ + rtems_unsigned8 CT1_CUR_CNT_MSB; /* Ctr/Timer 1 - Current Count (MSB) */ + rtems_unsigned8 CT1_CUR_CNT_LSB; /* Ctr/Timer 1 - Current Count (LSB) */ + rtems_unsigned8 CT2_CUR_CNT_MSB; /* Ctr/Timer 2 - Current Count (MSB) */ + rtems_unsigned8 CT2_CUR_CNT_LSB; /* Ctr/Timer 2 - Current Count (LSB) */ + rtems_unsigned8 CT3_CUR_CNT_MSB; /* Ctr/Timer 3 - Current Count (MSB) */ + rtems_unsigned8 CT3_CUR_CNT_LSB; /* Ctr/Timer 3 - Current Count (LSB) */ + rtems_unsigned8 CT1_TIME_CONST_MSB; /* Ctr/Timer 1 - Time Constant (MSB) */ + rtems_unsigned8 CT1_TIME_CONST_LSB; /* Ctr/Timer 1 - Time Constant (LSB) */ + rtems_unsigned8 CT2_TIME_CONST_MSB; /* Ctr/Timer 2 - Time Constant (MSB) */ + rtems_unsigned8 CT2_TIME_CONST_LSB; /* Ctr/Timer 2 - Time Constant (LSB) */ + rtems_unsigned8 CT3_TIME_CONST_MSB; /* Ctr/Timer 3 - Time Constant (MSB) */ + rtems_unsigned8 CT3_TIME_CONST_LSB; /* Ctr/Timer 3 - Time Constant (LSB) */ + rtems_unsigned8 CT1_MODE_SPEC; /* Ctr/Timer 1 - Mode Specification */ + rtems_unsigned8 CT2_MODE_SPEC; /* Ctr/Timer 2 - Mode Specification */ + rtems_unsigned8 CT3_MODE_SPEC; /* Ctr/Timer 3 - Mode Specification */ + rtems_unsigned8 CURRENT_VECTOR; /* Current Vector */ +/* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */ + rtems_unsigned8 PORTA_MODE; /* Port A - Mode Specification */ + rtems_unsigned8 PORTA_HANDSHAKE; /* Port A - Handshake Specification */ + rtems_unsigned8 PORTA_DATA_POLARITY; /* Port A - Data Path Polarity */ + rtems_unsigned8 PORTA_DIRECTION; /* Port A - Data Direction */ + rtems_unsigned8 PORTA_SPECIAL_IO_CTL; /* Port A - Special IO Control */ + rtems_unsigned8 PORTA_PATT_POLARITY; /* Port A - Pattern Polarity */ + rtems_unsigned8 PORTA_PATT_TRANS; /* Port A - Pattern Transition */ + rtems_unsigned8 PORTA_PATT_MASK; /* Port A - Pattern Mask */ +/* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */ + rtems_unsigned8 PORTB_MODE; /* Port B - Mode Specification */ + rtems_unsigned8 PORTB_HANDSHAKE; /* Port B - Handshake Specification */ + rtems_unsigned8 PORTB_DATA_POLARITY; /* Port B - Data Path Polarity */ + rtems_unsigned8 PORTB_DIRECTION; /* Port B - Data Direction */ + rtems_unsigned8 PORTB_SPECIAL_IO_CTL; /* Port B - Special IO Control */ + rtems_unsigned8 PORTB_PATT_POLARITY; /* Port B - Pattern Polarity */ + rtems_unsigned8 PORTB_PATT_TRANS; /* Port B - Pattern Transition */ + rtems_unsigned8 PORTB_PATT_MASK; /* Port B - Pattern Mask */ +}; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/c/src/lib/include/zilog/z8530.h b/c/src/lib/include/zilog/z8530.h new file mode 100644 index 0000000000..cd6399844f --- /dev/null +++ b/c/src/lib/include/zilog/z8530.h @@ -0,0 +1,99 @@ +/* z8530.h + * + * This include file defines information related to a Zilog Z8530 + * SCC Chip. It is a IO mapped part. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __Z8530_h +#define __Z8530_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* macros */ + +#define VOL8( ptr ) ((volatile rtems_unsigned8 *)(ptr)) + +#define Z8x30_STATE0 ( z8530 ) \ + { char *garbage; \ + (garbage) = *(VOL8(z8530)) \ + } + +#define Z8x30_WRITE_CONTROL( z8530, reg, data ) \ + *(VOL8(z8530)) = (reg); \ + *(VOL8(z8530)) = (data) + +#define Z8x30_READ_CONTROL( z8530, reg, data ) \ + *(VOL8(z8530)) = (reg); \ + (data) = *(VOL8(z8530)) + +#define Z8x30_WRITE_DATA( z8530, data ) \ + *(VOL8(z8530)) = (data); + +#define Z8x30_READ_DATA( z8530, data ) \ + (data) = *(VOL8(z8530)); + + +/* RR_0 Bit Definitions */ + +#define RR_0_TX_BUFFER_EMPTY 0x04 +#define RR_0_RX_DATA_AVAILABLE 0x01 + +/* read registers */ + +#define RR_0 0x00 +#define RR_1 0x01 +#define RR_2 0x02 +#define RR_3 0x03 +#define RR_4 0x04 +#define RR_5 0x05 +#define RR_6 0x06 +#define RR_7 0x07 +#define RR_8 0x08 +#define RR_9 0x09 +#define RR_10 0x0A +#define RR_11 0x0B +#define RR_12 0x0C +#define RR_13 0x0D +#define RR_14 0x0E +#define RR_15 0x0F + +/* write registers */ + +#define WR_0 0x00 +#define WR_1 0x01 +#define WR_2 0x02 +#define WR_3 0x03 +#define WR_4 0x04 +#define WR_5 0x05 +#define WR_6 0x06 +#define WR_7 0x07 +#define WR_8 0x08 +#define WR_9 0x09 +#define WR_10 0x0A +#define WR_11 0x0B +#define WR_12 0x0C +#define WR_13 0x0D +#define WR_14 0x0E +#define WR_15 0x0F + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/lib/include/zilog/z8536.h b/c/src/lib/include/zilog/z8536.h new file mode 100644 index 0000000000..8d72f2c8af --- /dev/null +++ b/c/src/lib/include/zilog/z8536.h @@ -0,0 +1,112 @@ +/* z8536.h + * + * This include file defines information related to a Zilog Z8536 + * Counter/Timer/IO Chip. It is a IO mapped part. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * NOTE: This file shares as much as possible with the include + * file for the Z8036 via z8x36.h. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __Z8536_h +#define __Z8536_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* macros */ + +#define VOL8( ptr ) ((volatile rtems_unsigned8 *)(ptr)) + +#define Z8x36_STATE0 ( z8536 ) \ + { char *garbage; \ + (garbage) = *(VOL8(z8536+0xC)) \ + } + +#define Z8x36_WRITE( z8536, reg, data ) \ + *(VOL8(z8536+0xC)) = (reg); \ + *(VOL8(z8536+0xC)) = (data) + +#define Z8x36_READ( z8536, reg, data ) \ + *(VOL8(z8536+0xC)) = (reg); \ + (data) = *(VOL8(z8536+0xC)) + +/* structures */ + +/* MAIN CONTROL REGISTERS (0x00-0x07) */ +#define MASTER_INTR 0x00 /* Master Interrupt Ctl Reg */ +#define MASTER_CFG 0x01 /* Master Configuration Ctl Reg */ +#define PORTA_VECTOR 0x02 /* Port A - Interrupt Vector */ +#define PORTB_VECTOR 0x03 /* Port B - Interrupt Vector */ +#define CNT_TMR_VECTOR 0x04 /* Counter/Timer Interrupt Vector */ +#define PORTC_DATA_POLARITY 0x05 /* Port C - Data Path Polarity */ +#define PORTC_DIRECTION 0x06 /* Port C - Data Direction */ +#define PORTC_SPECIAL_IO_CTL 0x07 /* Port C - Special IO Control */ + +/* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */ +#define PORTA_CMD_STATUS 0x08 /* Port A - Command Status Reg */ +#define PORTB_CMD_STATUS 0x09 /* Port B - Command Status Reg */ +#define CT1_CMD_STATUS 0x0a /* Ctr/Timer 1 - Command Status Reg */ +#define CT2_CMD_STATUS 0x0b /* Ctr/Timer 2 - Command Status Reg */ +#define CT3_CMD_STATUS 0x0c /* Ctr/Timer 3 - Command Status Reg */ +#define PORTA_DATA 0x0d /* Port A - Data */ +#define PORTB_DATA 0x0e /* Port B - Data */ +#define PORTC_DATA 0x0f /* Port C - Data */ + +/* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */ +#define CT1_CUR_CNT_MSB 0x10 /* Ctr/Timer 1 - Current Count (MSB) */ +#define CT1_CUR_CNT_LSB 0x11 /* Ctr/Timer 1 - Current Count (LSB) */ +#define CT2_CUR_CNT_MSB 0x12 /* Ctr/Timer 2 - Current Count (MSB) */ +#define CT2_CUR_CNT_LSB 0x13 /* Ctr/Timer 2 - Current Count (LSB) */ +#define CT3_CUR_CNT_MSB 0x14 /* Ctr/Timer 3 - Current Count (MSB) */ +#define CT3_CUR_CNT_LSB 0x15 /* Ctr/Timer 3 - Current Count (LSB) */ +#define CT1_TIME_CONST_MSB 0x16 /* Ctr/Timer 1 - Time Constant (MSB) */ +#define CT1_TIME_CONST_LSB 0x17 /* Ctr/Timer 1 - Time Constant (LSB) */ +#define CT2_TIME_CONST_MSB 0x18 /* Ctr/Timer 2 - Time Constant (MSB) */ +#define CT2_TIME_CONST_LSB 0x19 /* Ctr/Timer 2 - Time Constant (LSB) */ +#define CT3_TIME_CONST_MSB 0x1a /* Ctr/Timer 3 - Time Constant (MSB) */ +#define CT3_TIME_CONST_LSB 0x1b /* Ctr/Timer 3 - Time Constant (LSB) */ +#define CT1_MODE_SPEC 0x1c /* Ctr/Timer 1 - Mode Specification */ +#define CT2_MODE_SPEC 0x1d /* Ctr/Timer 2 - Mode Specification */ +#define CT3_MODE_SPEC 0x1e /* Ctr/Timer 3 - Mode Specification */ +#define CURRENT_VECTOR 0x1f /* Current Vector */ + +/* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */ +#define PORTA_MODE 0x20 /* Port A - Mode Specification */ +#define PORTA_HANDSHAKE 0x21 /* Port A - Handshake Specification */ +#define PORTA_DATA_POLARITY 0x22 /* Port A - Data Path Polarity */ +#define PORTA_DIRECTION 0x23 /* Port A - Data Direction */ +#define PORTA_SPECIAL_IO_CTL 0x24 /* Port A - Special IO Control */ +#define PORTA_PATT_POLARITY 0x25 /* Port A - Pattern Polarity */ +#define PORTA_PATT_TRANS 0x26 /* Port A - Pattern Transition */ +#define PORTA_PATT_MASK 0x27 /* Port A - Pattern Mask */ + +/* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */ +#define PORTB_MODE 0x28 /* Port B - Mode Specification */ +#define PORTB_HANDSHAKE 0x29 /* Port B - Handshake Specification */ +#define PORTB_DATA_POLARITY 0x2a /* Port B - Data Path Polarity */ +#define PORTB_DIRECTION 0x2b /* Port B - Data Direction */ +#define PORTB_SPECIAL_IO_CTL 0x2c /* Port B - Special IO Control */ +#define PORTB_PATT_POLARITY 0x2d /* Port B - Pattern Polarity */ +#define PORTB_PATT_TRANS 0x2e /* Port B - Pattern Transition */ +#define PORTB_PATT_MASK 0x2f /* Port B - Pattern Mask */ + +#ifdef __cplusplus +} +#endif + +#endif |