diff options
Diffstat (limited to 'c/src/exec/score/cpu')
24 files changed, 0 insertions, 7667 deletions
diff --git a/c/src/exec/score/cpu/hppa1.1/cpu.c b/c/src/exec/score/cpu/hppa1.1/cpu.c deleted file mode 100644 index d72dda4941..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/cpu.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * HP PA-RISC Dependent Source - * - * COPYRIGHT (c) 1994 by Division Incorporated - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Division Incorporated not be - * used in advertising or publicity pertaining to distribution - * of the software without specific, written prior permission. - * Division Incorporated makes no representations about the - * suitability of this software for any purpose. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -void hppa_cpu_halt(unsigned32 the_error); - - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is unsupported. For HPPA this function is handled by BSP - */ - - _CPU_Fatal_halt( 0xdeaddead ); -} - - - -/* - * This is the default handler which is called if - * _CPU_ISR_install_vector() has not been called for the - * specified vector. It simply forwards onto the spurious - * handler defined in the cpu-table. - */ - -static ISR_Handler -hppa_interrupt_report_spurious(ISR_Vector_number vector, - void* rtems_isr_frame) /* HPPA extension */ -{ - - /* - * If the CPU table defines a spurious_handler, then - * call it. If the handler returns halt. - */ - if ( _CPU_Table.spurious_handler ) - _CPU_Table.spurious_handler(vector, rtems_isr_frame); - - hppa_cpu_halt(vector); -} - - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level(void) -{ - int level; - HPPA_ASM_SSM(0, level); /* change no bits; just get copy */ - if (level & HPPA_PSW_I) - return 0; - return 1; -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. The handler is a C callable routine. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[vector]; - - _ISR_Vector_table[vector] = new_handler; -} - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - * - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - register unsigned8 *fp_context; - int i; - proc_ptr old_handler; - - /* - * This is the default fp context for all tasks - * Set it up so that denormalized results go to zero. - */ - - fp_context = (unsigned8*) &_CPU_Null_fp_context; - for (i=0 ; i<sizeof(Context_Control_fp); i++) - *fp_context++ = 0; - *((unsigned32 *) &_CPU_Null_fp_context) = HPPA_FPSTATUS_D; - - /* - * Save r27 into _CPU_Default_gr27 so it will hopefully be the correct - * global data pointer for the entire system. - */ - - asm volatile( "stw %%r27,%0" : "=m" (_CPU_Default_gr27): ); - - /* - * Init the 2nd level interrupt handlers - */ - - for (i=0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++) - _CPU_ISR_install_vector(i, - hppa_interrupt_report_spurious, - &old_handler); - - _CPU_Table = *cpu_table; - -} - - -/* - * Halt the system. - * Called by the _CPU_Fatal_halt macro - * - * XXX - * Later on, this will allow us to return to the prom. - * For now, we just ignore 'type_of_halt' - * - * XXX - * NOTE: for gcc, this function must be at the bottom - * of the file, that is because if it is at the top - * of the file, gcc will inline it's calls. Since - * the function uses the HPPA_ASM_LABEL() macro, when - * gcc inlines it, you get two definitions of the same - * label name, which is an assembly error. - */ - - -void -hppa_cpu_halt(unsigned32 the_error) -{ - unsigned32 isrlevel; - - _CPU_ISR_Disable(isrlevel); - - /* - * XXXXX NOTE: This label is only needed that that when - * the simulator stops, it shows the label name specified - */ - HPPA_ASM_LABEL("_hppa_cpu_halt"); - HPPA_ASM_BREAK(0, 0); -} - diff --git a/c/src/exec/score/cpu/hppa1.1/cpu.h b/c/src/exec/score/cpu/hppa1.1/cpu.h deleted file mode 100644 index 2d35735ad4..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/cpu.h +++ /dev/null @@ -1,607 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the HP - * PA-RISC processor (Level 1.1). - * - * COPYRIGHT (c) 1994 by Division Incorporated - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Division Incorporated not be - * used in advertising or publicity pertaining to distribution - * of the software without specific, written prior permission. - * Division Incorporated makes no representations about the - * suitability of this software for any purpose. - * - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/hppa.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/hppatypes.h> -#endif - -/* conditional compilation parameters */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * RTEMS manages an interrupt stack in software for the HPPA. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * HPPA has hardware FP, it is assumed to exist by GCC so all tasks - * may implicitly use it (especially for integer multiplies). Because - * the FP context is technically part of the basic integer context - * on this CPU, we cannot use the deferred FP context switch algorithm. - */ - -#define CPU_HARDWARE_FP TRUE -#define CPU_ALL_TASKS_ARE_FP TRUE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE -#define CPU_STACK_GROWS_UP TRUE -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((__aligned__ (32))) - -/* constants */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * PSW contstants - */ - -#define CPU_PSW_BASE (HPPA_PSW_C | HPPA_PSW_Q | HPPA_PSW_P | HPPA_PSW_D) -#define CPU_PSW_INTERRUPTS_ON (CPU_PSW_BASE | HPPA_PSW_I) -#define CPU_PSW_INTERRUPTS_OFF (CPU_PSW_BASE) - -#define CPU_PSW_DEFAULT CPU_PSW_BASE - - -#ifndef ASM - -/* - * Contexts - * - * This means we have the following context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * - * The PA-RISC is very fast so the expense of saving an extra register - * or two is not of great concern at the present. So we are not making - * a distinction between what is saved during a task switch and what is - * saved at each interrupt. Plus saving the entire context should make - * it easier to make gdb aware of RTEMS tasks. - */ - -typedef struct { - unsigned32 flags; /* whatever */ - unsigned32 gr1; /* scratch -- caller saves */ - unsigned32 gr2; /* RP -- return pointer */ - unsigned32 gr3; /* scratch -- callee saves */ - unsigned32 gr4; /* scratch -- callee saves */ - unsigned32 gr5; /* scratch -- callee saves */ - unsigned32 gr6; /* scratch -- callee saves */ - unsigned32 gr7; /* scratch -- callee saves */ - unsigned32 gr8; /* scratch -- callee saves */ - unsigned32 gr9; /* scratch -- callee saves */ - unsigned32 gr10; /* scratch -- callee saves */ - unsigned32 gr11; /* scratch -- callee saves */ - unsigned32 gr12; /* scratch -- callee saves */ - unsigned32 gr13; /* scratch -- callee saves */ - unsigned32 gr14; /* scratch -- callee saves */ - unsigned32 gr15; /* scratch -- callee saves */ - unsigned32 gr16; /* scratch -- callee saves */ - unsigned32 gr17; /* scratch -- callee saves */ - unsigned32 gr18; /* scratch -- callee saves */ - unsigned32 gr19; /* scratch -- caller saves */ - unsigned32 gr20; /* scratch -- caller saves */ - unsigned32 gr21; /* scratch -- caller saves */ - unsigned32 gr22; /* scratch -- caller saves */ - unsigned32 gr23; /* argument 3 */ - unsigned32 gr24; /* argument 2 */ - unsigned32 gr25; /* argument 1 */ - unsigned32 gr26; /* argument 0 */ - unsigned32 gr27; /* DP -- global data pointer */ - unsigned32 gr28; /* return values -- caller saves */ - unsigned32 gr29; /* return values -- caller saves */ - unsigned32 sp; /* gr30 */ - unsigned32 gr31; - - /* Various control registers */ - - unsigned32 sar; /* cr11 */ - unsigned32 ipsw; /* cr22; full 32 bits of psw */ - unsigned32 iir; /* cr19; interrupt instruction register */ - unsigned32 ior; /* cr21; interrupt offset register */ - unsigned32 isr; /* cr20; interrupt space register (not used) */ - unsigned32 pcoqfront; /* cr18; front que offset */ - unsigned32 pcoqback; /* cr18; back que offset */ - unsigned32 pcsqfront; /* cr17; front que space (not used) */ - unsigned32 pcsqback; /* cr17; back que space (not used) */ - unsigned32 itimer; /* cr16; itimer value */ - -} Context_Control; - - -/* Must be double word aligned. - * This will be ok since our allocator returns 8 byte aligned chunks - */ - -typedef struct { - double fr0; /* status */ - double fr1; /* exception information */ - double fr2; /* exception information */ - double fr3; /* exception information */ - double fr4; /* argument */ - double fr5; /* argument */ - double fr6; /* argument */ - double fr7; /* argument */ - double fr8; /* scratch -- caller saves */ - double fr9; /* scratch -- caller saves */ - double fr10; /* scratch -- caller saves */ - double fr11; /* scratch -- caller saves */ - double fr12; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr13; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr14; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr15; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr16; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr17; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr18; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr19; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr20; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr21; /* callee saves -- (PA-RISC 1.1 CPUs) */ - double fr22; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr23; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr24; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr25; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr26; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr27; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr28; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr29; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr30; /* caller saves -- (PA-RISC 1.1 CPUs) */ - double fr31; /* caller saves -- (PA-RISC 1.1 CPUs) */ -} Context_Control_fp; - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of each interrupt. - */ - -typedef struct { - Context_Control Integer; - Context_Control_fp Floating_Point; -} CPU_Interrupt_frame; - -/* - * Our interrupt handlers take a 2nd argument: - * a pointer to a CPU_Interrupt_frame - * So we use our own prototype instead of rtems_isr_entry - */ - -typedef void ( *hppa_rtems_isr_entry )( - unsigned32, - CPU_Interrupt_frame * - ); - -/* - * The following table contains the information required to configure - * the HPPA specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void * ); - /* end of fields required on all CPUs */ - - hppa_rtems_isr_entry spurious_handler; - - unsigned32 itimer_clicks_per_microsecond; /* for use by Clock driver */ -} rtems_cpu_table; - -/* variables */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -SCORE_EXTERN unsigned32 _CPU_Default_gr27; -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -#endif /* ! ASM */ - -/* - * context sizes - */ - -#ifndef ASM -#define CPU_CONTEXT_SIZE sizeof( Context_Control ) -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) -#endif - -/* - * size of a frame on the stack - */ - -#define CPU_FRAME_SIZE (16 * 4) - -/* - * (Optional) # of bytes for libmisc/stackchk to check - * If not specifed, then it defaults to something reasonable - * for most architectures. - */ - -#define CPU_STACK_CHECK_SIZE (CPU_FRAME_SIZE * 2) - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * HPPA has 32 traps, then 32 external interrupts - * Rtems (_ISR_Vector_Table) is aware ONLY of the first 32 - * The BSP is aware of the external interrupts and possibly more. - * - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS (HPPA_INTERNAL_TRAPS) -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * Don't be chintzy here; we don't want to debug these problems - * Some of the tests eat almost 4k. - * Plus, the HPPA always allocates chunks of 64 bytes for stack - * growth. - */ - -#define CPU_STACK_MINIMUM_SIZE (8 * 1024) - -/* - * HPPA double's must be on 8 byte boundary - */ - -#define CPU_ALIGNMENT 8 - -/* - * just follow the basic HPPA alignment for the heap and partition - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * HPPA stack is best when 64 byte aligned. - */ - -#define CPU_STACK_ALIGNMENT 64 - -#ifndef ASM - -/* macros */ - -/* - * ISR handler macros - * - * These macros perform the following functions: - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -/* Disable interrupts; returning previous psw bits in _isr_level */ -#define _CPU_ISR_Disable( _isr_level ) \ - do { \ - HPPA_ASM_RSM(HPPA_PSW_I, _isr_level); \ - if (_isr_level & HPPA_PSW_I) _isr_level = 0; \ - else _isr_level = 1; \ - } while(0) - -/* Enable interrupts to previous level from _CPU_ISR_Disable - * does not change 'level' */ -#define _CPU_ISR_Enable( _isr_level ) \ - { \ - register int _ignore; \ - if (_isr_level == 0) HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \ - else HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \ - } - -/* restore, then disable interrupts; does not change level */ -#define _CPU_ISR_Flash( _isr_level ) \ - { \ - if (_isr_level == 0) \ - { \ - register int _ignore; \ - HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \ - HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \ - } \ - } - -/* - * Interrupt task levels - * - * Future scheme proposal - * level will be an index into a array. - * Each entry of array will be the interrupt bits - * enabled for that level. There will be 32 bits of external - * interrupts (to be placed in EIEM) and some (optional) bsp - * specific bits - * - * For pixel flow this *may* mean something like: - * level 0: all interrupts enabled (external + rhino) - * level 1: rhino disabled - * level 2: all io interrupts disabled (timer still enabled) - * level 7: *ALL* disabled (timer disabled) - */ - -/* set interrupts on or off; does not return new level */ -#define _CPU_ISR_Set_level( new_level ) \ - { \ - volatile int ignore; \ - if ( new_level ) HPPA_ASM_RSM(HPPA_PSW_I, ignore); \ - else HPPA_ASM_SSM(HPPA_PSW_I, ignore); \ - } - -/* return current level */ -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - * - * HPPA port adds two macros which hide the "indirectness" of the - * pointer passed the save/restore FP context assembly routines. - */ - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _new_level, _entry_point, _is_fp ) \ - do { \ - unsigned32 _stack; \ - \ - (_the_context)->flags = 0xfeedf00d; \ - (_the_context)->pcoqfront = (unsigned32)(_entry_point); \ - (_the_context)->pcoqback = (unsigned32)(_entry_point) + 4; \ - (_the_context)->pcsqfront = 0; \ - (_the_context)->pcsqback = 0; \ - if ( (_new_level) ) \ - (_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \ - else \ - (_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \ - \ - _stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \ - _stack &= ~(CPU_STACK_ALIGNMENT - 1); \ - if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \ - _stack += CPU_FRAME_SIZE; \ - \ - (_the_context)->sp = (_stack); \ - (_the_context)->gr27 = _CPU_Default_gr27; \ - } while (0) - -#define _CPU_Context_Restart_self( _the_context ) \ - do { \ - _CPU_Context_restore( (_the_context) ); \ - } while (0) - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\ - } while(0) - -#define _CPU_Context_save_fp( _fp_context ) \ - _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context) ) - -#define _CPU_Context_restore_fp( _fp_context ) \ - _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context) ) - -/* end of Context handler macros */ - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -void hppa_cpu_halt(unsigned32 the_error); -#define _CPU_Fatal_halt( _error ) \ - hppa_cpu_halt(_error) - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - * - * NOTE: - * - * The HPPA does not have a scan instruction. This functionality - * is implemented in software. - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -int hppa_rtems_ffs(unsigned int value); -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - _output = hppa_rtems_ffs(_value) - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - * - * Note: 255 is the lowest priority - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner and avoid stack conflicts. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Save_float_context - * - * This routine saves the floating point context passed to it. - * - * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA - * which dereferences the pointer before calling this. - */ - -void _CPU_Save_float_context( - Context_Control_fp *fp_context -); - -/* - * _CPU_Restore_float_context - * - * This routine restores the floating point context passed to it. - * - * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA - * which dereferences the pointer before calling this. - */ - -void _CPU_Restore_float_context( - Context_Control_fp *fp_context -); - - -/* - * The raw interrupt handler for external interrupts - */ - -extern void _Generic_ISR_Handler( - void -); - - -/* The following routine swaps the endian format of an unsigned int. - * It must be static so it can be referenced indirectly. - */ - -static inline unsigned int -CPU_swap_u32(unsigned32 value) -{ - unsigned32 swapped; - - HPPA_ASM_SWAPBYTES(value, swapped); - - return( swapped ); -} - -#endif /* ! ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* ! __CPU_h */ diff --git a/c/src/exec/score/cpu/hppa1.1/cpu_asm.h b/c/src/exec/score/cpu/hppa1.1/cpu_asm.h deleted file mode 100644 index 951f80dcf0..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/cpu_asm.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 1990,1991 The University of Utah and - * the Center for Software Science (CSS). All rights reserved. - * - * Permission to use, copy, modify and distribute this software is hereby - * granted provided that (1) source code retains these copyright, permission, - * and disclaimer notices, and (2) redistributions including binaries - * reproduce the notices in supporting documentation, and (3) all advertising - * materials mentioning features or use of this software display the following - * acknowledgement: ``This product includes software developed by the Center - * for Software Science at the University of Utah.'' - * - * THE UNIVERSITY OF UTAH AND CSS ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS - * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSS DISCLAIM ANY LIABILITY OF - * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * - * CSS requests users of this software to return to css-dist@cs.utah.edu any - * improvements that they make and grant CSS redistribution rights. - * - * Utah $Hdr: asm.h 1.6 91/12/03$ - * - * $Id$ - */ - -/* - * Hardware Space Registers - */ -sr0 .reg %sr0 -sr1 .reg %sr1 -sr2 .reg %sr2 -sr3 .reg %sr3 -sr4 .reg %sr4 -sr5 .reg %sr5 -sr6 .reg %sr6 -sr7 .reg %sr7 - -/* - * Control register aliases - */ - -rctr .reg %cr0 -pidr1 .reg %cr8 -pidr2 .reg %cr9 -ccr .reg %cr10 -sar .reg %cr11 -pidr3 .reg %cr12 -pidr4 .reg %cr13 -iva .reg %cr14 -eiem .reg %cr15 -itmr .reg %cr16 -pcsq .reg %cr17 -pcoq .reg %cr18 -iir .reg %cr19 -isr .reg %cr20 -ior .reg %cr21 -ipsw .reg %cr22 -eirr .reg %cr23 - -/* - * Calling Convention - */ -rp .reg %r2 -arg3 .reg %r23 -arg2 .reg %r24 -arg1 .reg %r25 -arg0 .reg %r26 -dp .reg %r27 -ret0 .reg %r28 -ret1 .reg %r29 -sl .reg %r29 -sp .reg %r30 - - diff --git a/c/src/exec/score/cpu/hppa1.1/cpu_asm.s b/c/src/exec/score/cpu/hppa1.1/cpu_asm.s deleted file mode 100644 index bf0d4b0bee..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/cpu_asm.s +++ /dev/null @@ -1,705 +0,0 @@ -# -# TODO: -# Context_switch needs to only save callee save registers -# I think this means can skip: r1, r2, r19-29, r31 -# Ref: p 3-2 of Procedure Calling Conventions Manual -# This should be #ifndef DEBUG so that debugger has -# accurate visibility into all registers -# -# This file contains the assembly code for the HPPA implementation -# of RTEMS. -# -# COPYRIGHT (c) 1994,95 by Division Incorporated -# -# To anyone who acknowledges that this file is provided "AS IS" -# without any express or implied warranty: -# permission to use, copy, modify, and distribute this file -# for any purpose is hereby granted without fee, provided that -# the above copyright notice and this notice appears in all -# copies, and that the name of Division Incorporated not be -# used in advertising or publicity pertaining to distribution -# of the software without specific, written prior permission. -# Division Incorporated makes no representations about the -# suitability of this software for any purpose. -# -# $Id$ -# - -#include <rtems/score/hppa.h> -#include <rtems/score/cpu_asm.h> -#include <rtems/score/cpu.h> -#include <rtems/score/offsets.h> - - .SPACE $PRIVATE$ - .SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31 - .SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82 - .SPACE $TEXT$ - .SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44 - .SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY - .SPACE $TEXT$ - .SUBSPA $CODE$ - -# -# Special register usage for context switch and interrupts -# Stay away from %cr28 which is used for TLB misses on 72000 -# - -isr_arg0 .reg %cr24 -isr_r9 .reg %cr25 -isr_r8 .reg %cr26 - -# -# Interrupt stack frame looks like this -# -# offset item -# ----------------------------------------------------------------- -# INTEGER_CONTEXT_OFFSET Context_Control -# FP_CONTEXT_OFFSET Context_Control_fp -# -# It is padded out to a multiple of 64 -# - - -# PAGE^L -# void _Generic_ISR_Handler() -# -# This routine provides the RTEMS interrupt management. -# -# We jump here from the interrupt vector. -# The HPPA hardware has done some stuff for us: -# PSW saved in IPSW -# PSW set to 0 -# PSW[E] set to default (0) -# PSW[M] set to 1 iff this is HPMC -# -# IIA queue is frozen (since PSW[Q] is now 0) -# privilege level promoted to 0 -# IIR, ISR, IOR potentially updated if PSW[Q] was 1 at trap -# registers GR 1,8,9,16,17,24,25 copied to shadow regs -# SHR 0 1 2 3 4 5 6 -# -# Our vector stub (in the BSP) MUST have done the following: -# -# a) Saved the original %r9 into %isr_r9 (%cr25) -# b) Placed the vector number in %r9 -# c) Was allowed to also destroy $isr_r8 (%cr26), -# but the stub was NOT allowed to destroy any other registers. -# -# The typical stub sequence (in the BSP) should look like this: -# -# a) mtctl %r9,isr_r9 ; (save r9 in cr25) -# b) ldi vector,%r9 ; (load constant vector number in r9) -# c) mtctl %r8,isr_r8 ; (save r8 in cr26) -# d) ldil L%MY_BSP_first_level_interrupt_handler,%r8 -# e) ldo R%MY_BSP_first_level_interrupt_handler(%r8),%r8 -# ; (point to BSP raw handler table) -# f) ldwx,s %r9(%r8),%r8 ; (load value from raw handler table) -# g) bv 0(%r8) ; (call raw handler: _Generic_ISR_Handler) -# h) mfctl isr_r8,%r8 ; (restore r8 from cr26 in delay slot) -# -# Optionally, steps (c) thru (h) _could_ be replaced with a single -# bl,n _Generic_ISR_Handler,%r0 -# -# -# - .EXPORT _Generic_ISR_Handler,ENTRY,PRIV_LEV=0 -_Generic_ISR_Handler: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - - mtctl arg0, isr_arg0 - -# save interrupt state - mfctl ipsw, arg0 - stw arg0, IPSW_OFFSET(sp) - - mfctl iir, arg0 - stw arg0, IIR_OFFSET(sp) - - mfctl ior, arg0 - stw arg0, IOR_OFFSET(sp) - - mfctl pcoq, arg0 - stw arg0, PCOQFRONT_OFFSET(sp) - - mtctl %r0, pcoq - mfctl pcoq, arg0 - stw arg0, PCOQBACK_OFFSET(sp) - - mfctl %sar, arg0 - stw arg0, SAR_OFFSET(sp) - -# -# Build an interrupt frame to hold the contexts we will need. -# We have already saved the interrupt items on the stack - -# At this point the following registers are damaged wrt the interrupt -# reg current value saved value -# ------------------------------------------------ -# arg0 scratch isr_arg0 (cr24) -# r9 vector number isr_r9 (cr25) -# -# Point to beginning of integer context and -# save the integer context - stw %r1,R1_OFFSET(sp) - stw %r2,R2_OFFSET(sp) - stw %r3,R3_OFFSET(sp) - stw %r4,R4_OFFSET(sp) - stw %r5,R5_OFFSET(sp) - stw %r6,R6_OFFSET(sp) - stw %r7,R7_OFFSET(sp) - stw %r8,R8_OFFSET(sp) -# skip r9 - stw %r10,R10_OFFSET(sp) - stw %r11,R11_OFFSET(sp) - stw %r12,R12_OFFSET(sp) - stw %r13,R13_OFFSET(sp) - stw %r14,R14_OFFSET(sp) - stw %r15,R15_OFFSET(sp) - stw %r16,R16_OFFSET(sp) - stw %r17,R17_OFFSET(sp) - stw %r18,R18_OFFSET(sp) - stw %r19,R19_OFFSET(sp) - stw %r20,R20_OFFSET(sp) - stw %r21,R21_OFFSET(sp) - stw %r22,R22_OFFSET(sp) - stw %r23,R23_OFFSET(sp) - stw %r24,R24_OFFSET(sp) - stw %r25,R25_OFFSET(sp) -# skip arg0 - stw %r27,R27_OFFSET(sp) - stw %r28,R28_OFFSET(sp) - stw %r29,R29_OFFSET(sp) - stw %r30,R30_OFFSET(sp) - stw %r31,R31_OFFSET(sp) - -# Now most registers are available since they have been saved -# -# The following items are currently wrong in the integer context -# reg current value saved value -# ------------------------------------------------ -# arg0 scratch isr_arg0 (cr24) -# r9 vector number isr_r9 (cr25) -# -# Fix them - - mfctl isr_arg0,%r3 - stw %r3,ARG0_OFFSET(sp) - - mfctl isr_r9,%r3 - stw %r3,R9_OFFSET(sp) - -# -# At this point we are done with isr_arg0, and isr_r9 control registers -# -# Prepare to re-enter virtual mode -# We need Q in case the interrupt handler enables interrupts -# - - ldil L%CPU_PSW_DEFAULT, arg0 - ldo R%CPU_PSW_DEFAULT(arg0), arg0 - mtctl arg0, ipsw - -# Now jump to "rest_of_isr_handler" with the rfi -# We are assuming the space queues are all correct already - - ldil L%rest_of_isr_handler, arg0 - ldo R%rest_of_isr_handler(arg0), arg0 - mtctl arg0, pcoq - ldo 4(arg0), arg0 - mtctl arg0, pcoq - - rfi - nop - -# At this point we are back in virtual mode and all our -# normal addressing is once again ok. -# -# It is now ok to take an exception or trap -# - -rest_of_isr_handler: - -# Point to beginning of float context and -# save the floating point context -- doing whatever patches are necessary - .call ARGW0=GR - bl _CPU_Save_float_context,%r2 - ldo FP_CONTEXT_OFFSET(sp),arg0 - -# save the ptr to interrupt frame as an argument for the interrupt handler - copy sp, arg1 - -# Advance the frame to point beyond all interrupt contexts (integer & float) -# this also includes the pad to align to 64byte stack boundary - ldo CPU_INTERRUPT_FRAME_SIZE(sp), sp - -# r3 -- &_ISR_Nest_level -# r5 -- value _ISR_Nest_level -# r4 -- &_Thread_Dispatch_disable_level -# r6 -- value _Thread_Dispatch_disable_level -# r9 -- vector number - - .import _ISR_Nest_level,data - ldil L%_ISR_Nest_level,%r3 - ldo R%_ISR_Nest_level(%r3),%r3 - ldw 0(%r3),%r5 - - .import _Thread_Dispatch_disable_level,data - ldil L%_Thread_Dispatch_disable_level,%r4 - ldo R%_Thread_Dispatch_disable_level(%r4),%r4 - ldw 0(%r4),%r6 - -# increment interrupt nest level counter. If outermost interrupt -# switch the stack and squirrel away the previous sp. - addi 1,%r5,%r5 - stw %r5, 0(%r3) - -# compute and save new stack (with frame) -# just in case we are nested -- simpler this way - comibf,= 1,%r5,stack_done - ldo 128(sp),%r7 - -# -# Switch to interrupt stack allocated by the interrupt manager (intr.c) -# - .import _CPU_Interrupt_stack_low,data - ldil L%_CPU_Interrupt_stack_low,%r7 - ldw R%_CPU_Interrupt_stack_low(%r7),%r7 - ldo 128(%r7),%r7 - -stack_done: -# save our current stack pointer where the "old sp" is supposed to be - stw sp, -4(%r7) -# and switch stacks (or advance old stack in nested case) - copy %r7, sp - -# increment the dispatch disable level counter. - addi 1,%r6,%r6 - stw %r6, 0(%r4) - -# load address of user handler -# Note: No error checking is done, it is assumed that the -# vector table contains a valid address or a stub -# spurious handler. - .import _ISR_Vector_table,data - ldil L%_ISR_Vector_table,%r8 - ldo R%_ISR_Vector_table(%r8),%r8 - ldwx,s %r9(%r8),%r8 - -# invoke user interrupt handler -# Interrupts are currently disabled, as per RTEMS convention -# The handler has the option of re-enabling interrupts -# NOTE: can not use 'bl' since it uses "pc-relative" addressing -# and we are using a hard coded address from a table -# So... we fudge r2 ourselves (ala dynacall) -# arg0 = vector number, arg1 = ptr to rtems_interrupt_frame - copy %r9, %r26 - .call ARGW0=GR, ARGW1=GR - blr %r0, rp - bv,n 0(%r8) - -post_user_interrupt_handler: - -# Back from user handler(s) -# Disable external interrupts (since the interrupt handler could -# have turned them on) and return to the interrupted task stack (assuming -# (_ISR_Nest_level == 0) - - rsm HPPA_PSW_I + HPPA_PSW_R, %r0 - ldw -4(sp), sp - -# r3 -- (most of) &_ISR_Nest_level -# r5 -- value _ISR_Nest_level -# r4 -- (most of) &_Thread_Dispatch_disable_level -# r6 -- value _Thread_Dispatch_disable_level -# r7 -- (most of) &_ISR_Signals_to_thread_executing -# r8 -- value _ISR_Signals_to_thread_executing - - .import _ISR_Nest_level,data - ldil L%_ISR_Nest_level,%r3 - ldw R%_ISR_Nest_level(%r3),%r5 - - .import _Thread_Dispatch_disable_level,data - ldil L%_Thread_Dispatch_disable_level,%r4 - ldw R%_Thread_Dispatch_disable_level(%r4),%r6 - - .import _ISR_Signals_to_thread_executing,data - ldil L%_ISR_Signals_to_thread_executing,%r7 - -# decrement isr nest level - addi -1, %r5, %r5 - stw %r5, R%_ISR_Nest_level(%r3) - -# decrement dispatch disable level counter and, if not 0, go on - addi -1,%r6,%r6 - comibf,= 0,%r6,isr_restore - stw %r6, R%_Thread_Dispatch_disable_level(%r4) - -# check whether or not a context switch is necessary - .import _Context_Switch_necessary,data - ldil L%_Context_Switch_necessary,%r8 - ldw R%_Context_Switch_necessary(%r8),%r8 - comibf,=,n 0,%r8,ISR_dispatch - -# check whether or not a context switch is necessary because an ISR -# sent signals to the interrupted task - ldw R%_ISR_Signals_to_thread_executing(%r7),%r8 - comibt,=,n 0,%r8,isr_restore - - -# OK, something happened while in ISR and we need to switch to a task -# other than the one which was interrupted or the -# ISR_Signals_to_thread_executing case -# We also turn on interrupts, since the interrupted task had them -# on (obviously :-) and Thread_Dispatch is happy to leave ints on. -# - -ISR_dispatch: - stw %r0, R%_ISR_Signals_to_thread_executing(%r7) - - ssm HPPA_PSW_I, %r0 - - .import _Thread_Dispatch,code - .call - bl _Thread_Dispatch,%r2 - ldo 128(sp),sp - - ldo -128(sp),sp - -isr_restore: - -# enable interrupts during most of restore - ssm HPPA_PSW_I, %r0 - -# Get a pointer to beginning of our stack frame - ldo -CPU_INTERRUPT_FRAME_SIZE(sp), %arg1 - -# restore float - .call ARGW0=GR - bl _CPU_Restore_float_context,%r2 - ldo FP_CONTEXT_OFFSET(%arg1), arg0 - - copy %arg1, %arg0 - -# ********** FALL THRU ********** - -# Jump here from bottom of Context_Switch -# Also called directly by _CPU_Context_Restart_self via _Thread_Restart_self -# restore interrupt state -# - - .EXPORT _CPU_Context_restore -_CPU_Context_restore: - -# -# restore integer state -# - ldw R1_OFFSET(arg0),%r1 - ldw R2_OFFSET(arg0),%r2 - ldw R3_OFFSET(arg0),%r3 - ldw R4_OFFSET(arg0),%r4 - ldw R5_OFFSET(arg0),%r5 - ldw R6_OFFSET(arg0),%r6 - ldw R7_OFFSET(arg0),%r7 - ldw R8_OFFSET(arg0),%r8 - ldw R9_OFFSET(arg0),%r9 - ldw R10_OFFSET(arg0),%r10 - ldw R11_OFFSET(arg0),%r11 - ldw R12_OFFSET(arg0),%r12 - ldw R13_OFFSET(arg0),%r13 - ldw R14_OFFSET(arg0),%r14 - ldw R15_OFFSET(arg0),%r15 - ldw R16_OFFSET(arg0),%r16 - ldw R17_OFFSET(arg0),%r17 - ldw R18_OFFSET(arg0),%r18 - ldw R19_OFFSET(arg0),%r19 - ldw R20_OFFSET(arg0),%r20 - ldw R21_OFFSET(arg0),%r21 - ldw R22_OFFSET(arg0),%r22 - ldw R23_OFFSET(arg0),%r23 - ldw R24_OFFSET(arg0),%r24 -# skipping r25; used as scratch register below -# skipping r26 (arg0) until we are done with it - ldw R27_OFFSET(arg0),%r27 - ldw R28_OFFSET(arg0),%r28 - ldw R29_OFFSET(arg0),%r29 -# skipping r30 (sp) until we turn off interrupts - ldw R31_OFFSET(arg0),%r31 - -# Turn off Q & R & I so we can write r30 and interrupt control registers - rsm HPPA_PSW_Q + HPPA_PSW_R + HPPA_PSW_I, %r0 - -# now safe to restore r30 - ldw R30_OFFSET(arg0),%r30 - - ldw IPSW_OFFSET(arg0), %r25 - mtctl %r25, ipsw - - ldw SAR_OFFSET(arg0), %r25 - mtctl %r25, sar - - ldw PCOQFRONT_OFFSET(arg0), %r25 - mtctl %r25, pcoq - - ldw PCOQBACK_OFFSET(arg0), %r25 - mtctl %r25, pcoq - -# Load r25 with interrupts off - ldw R25_OFFSET(arg0),%r25 -# Must load r26 (arg0) last - ldw R26_OFFSET(arg0),%r26 - -isr_exit: - rfi - .EXIT - .PROCEND - -# -# This section is used to context switch floating point registers. -# Ref: 6-35 of Architecture 1.1 -# -# NOTE: since integer multiply uses the floating point unit, -# we have to save/restore fp on every trap. We cannot -# just try to keep track of fp usage. - - .align 32 - .EXPORT _CPU_Save_float_context,ENTRY,PRIV_LEV=0 -_CPU_Save_float_context: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - fstds,ma %fr0,8(%arg0) - fstds,ma %fr1,8(%arg0) - fstds,ma %fr2,8(%arg0) - fstds,ma %fr3,8(%arg0) - fstds,ma %fr4,8(%arg0) - fstds,ma %fr5,8(%arg0) - fstds,ma %fr6,8(%arg0) - fstds,ma %fr7,8(%arg0) - fstds,ma %fr8,8(%arg0) - fstds,ma %fr9,8(%arg0) - fstds,ma %fr10,8(%arg0) - fstds,ma %fr11,8(%arg0) - fstds,ma %fr12,8(%arg0) - fstds,ma %fr13,8(%arg0) - fstds,ma %fr14,8(%arg0) - fstds,ma %fr15,8(%arg0) - fstds,ma %fr16,8(%arg0) - fstds,ma %fr17,8(%arg0) - fstds,ma %fr18,8(%arg0) - fstds,ma %fr19,8(%arg0) - fstds,ma %fr20,8(%arg0) - fstds,ma %fr21,8(%arg0) - fstds,ma %fr22,8(%arg0) - fstds,ma %fr23,8(%arg0) - fstds,ma %fr24,8(%arg0) - fstds,ma %fr25,8(%arg0) - fstds,ma %fr26,8(%arg0) - fstds,ma %fr27,8(%arg0) - fstds,ma %fr28,8(%arg0) - fstds,ma %fr29,8(%arg0) - fstds,ma %fr30,8(%arg0) - fstds %fr31,0(%arg0) - bv 0(%r2) - addi -(31*8), %arg0, %arg0 ; restore arg0 just for fun - .EXIT - .PROCEND - - .align 32 - .EXPORT _CPU_Restore_float_context,ENTRY,PRIV_LEV=0 -_CPU_Restore_float_context: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - addi (31*8), %arg0, %arg0 ; point at last double - fldds 0(%arg0),%fr31 - fldds,mb -8(%arg0),%fr30 - fldds,mb -8(%arg0),%fr29 - fldds,mb -8(%arg0),%fr28 - fldds,mb -8(%arg0),%fr27 - fldds,mb -8(%arg0),%fr26 - fldds,mb -8(%arg0),%fr25 - fldds,mb -8(%arg0),%fr24 - fldds,mb -8(%arg0),%fr23 - fldds,mb -8(%arg0),%fr22 - fldds,mb -8(%arg0),%fr21 - fldds,mb -8(%arg0),%fr20 - fldds,mb -8(%arg0),%fr19 - fldds,mb -8(%arg0),%fr18 - fldds,mb -8(%arg0),%fr17 - fldds,mb -8(%arg0),%fr16 - fldds,mb -8(%arg0),%fr15 - fldds,mb -8(%arg0),%fr14 - fldds,mb -8(%arg0),%fr13 - fldds,mb -8(%arg0),%fr12 - fldds,mb -8(%arg0),%fr11 - fldds,mb -8(%arg0),%fr10 - fldds,mb -8(%arg0),%fr9 - fldds,mb -8(%arg0),%fr8 - fldds,mb -8(%arg0),%fr7 - fldds,mb -8(%arg0),%fr6 - fldds,mb -8(%arg0),%fr5 - fldds,mb -8(%arg0),%fr4 - fldds,mb -8(%arg0),%fr3 - fldds,mb -8(%arg0),%fr2 - fldds,mb -8(%arg0),%fr1 - bv 0(%r2) - fldds,mb -8(%arg0),%fr0 - .EXIT - .PROCEND - -# -# These 2 small routines are unused right now. -# Normally we just go thru _CPU_Save_float_context (and Restore) -# -# Here we just deref the ptr and jump up, letting _CPU_Save_float_context -# do the return for us. -# - .EXPORT _CPU_Context_save_fp,ENTRY,PRIV_LEV=0 -_CPU_Context_save_fp: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - bl _CPU_Save_float_context, %r0 - ldw 0(%arg0), %arg0 - .EXIT - .PROCEND - - .EXPORT _CPU_Context_restore_fp,ENTRY,PRIV_LEV=0 -_CPU_Context_restore_fp: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - bl _CPU_Restore_float_context, %r0 - ldw 0(%arg0), %arg0 - .EXIT - .PROCEND - - -# void _CPU_Context_switch( run_context, heir_context ) -# -# This routine performs a normal non-FP context switch. -# - - .align 32 - .EXPORT _CPU_Context_switch,ENTRY,PRIV_LEV=0,ARGW0=GR,ARGW1=GR -_CPU_Context_switch: - .PROC - .CALLINFO FRAME=64 - .ENTRY - -# Save the integer context - stw %r1,R1_OFFSET(arg0) - stw %r2,R2_OFFSET(arg0) - stw %r3,R3_OFFSET(arg0) - stw %r4,R4_OFFSET(arg0) - stw %r5,R5_OFFSET(arg0) - stw %r6,R6_OFFSET(arg0) - stw %r7,R7_OFFSET(arg0) - stw %r8,R8_OFFSET(arg0) - stw %r9,R9_OFFSET(arg0) - stw %r10,R10_OFFSET(arg0) - stw %r11,R11_OFFSET(arg0) - stw %r12,R12_OFFSET(arg0) - stw %r13,R13_OFFSET(arg0) - stw %r14,R14_OFFSET(arg0) - stw %r15,R15_OFFSET(arg0) - stw %r16,R16_OFFSET(arg0) - stw %r17,R17_OFFSET(arg0) - stw %r18,R18_OFFSET(arg0) - stw %r19,R19_OFFSET(arg0) - stw %r20,R20_OFFSET(arg0) - stw %r21,R21_OFFSET(arg0) - stw %r22,R22_OFFSET(arg0) - stw %r23,R23_OFFSET(arg0) - stw %r24,R24_OFFSET(arg0) - stw %r25,R25_OFFSET(arg0) - stw %r26,R26_OFFSET(arg0) - stw %r27,R27_OFFSET(arg0) - stw %r28,R28_OFFSET(arg0) - stw %r29,R29_OFFSET(arg0) - stw %r30,R30_OFFSET(arg0) - stw %r31,R31_OFFSET(arg0) - -# fill in interrupt context section - stw %r2, PCOQFRONT_OFFSET(%arg0) - ldo 4(%r2), %r2 - stw %r2, PCOQBACK_OFFSET(%arg0) - -# Generate a suitable IPSW by using the system default psw -# with the current low bits added in. - - ldil L%CPU_PSW_DEFAULT, %r2 - ldo R%CPU_PSW_DEFAULT(%r2), %r2 - ssm 0, %arg2 - dep %arg2, 31, 8, %r2 - stw %r2, IPSW_OFFSET(%arg0) - -# at this point, the running task context is completely saved -# Now jump to the bottom of the interrupt handler to load the -# heirs context - - b _CPU_Context_restore - copy %arg1, %arg0 - - .EXIT - .PROCEND - - -/* - * Find first bit - * NOTE: - * This is used (and written) only for the ready chain code and - * priority bit maps. - * Any other use constitutes fraud. - * Returns first bit from the least significant side. - * Eg: if input is 0x8001 - * output will indicate the '1' bit and return 0. - * This is counter to HPPA bit numbering which calls this - * bit 31. This way simplifies the macros _CPU_Priority_Mask - * and _CPU_Priority_Bits_index. - * - * NOTE: - * We just use 16 bit version - * does not handle zero case - * - * Based on the UTAH Mach libc version of ffs. - */ - - .align 32 - .EXPORT hppa_rtems_ffs,ENTRY,PRIV_LEV=0,ARGW0=GR -hppa_rtems_ffs: - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - -#ifdef RETURN_ERROR_ON_ZERO - comb,= %arg0,%r0,ffsdone ; If arg0 is 0 - ldi -1,%ret0 ; return -1 -#endif - -#if BITFIELD_SIZE == 32 - ldi 31,%ret0 ; Set return to high bit - extru,= %arg0,31,16,%r0 ; If low 16 bits are non-zero - addi,tr -16,%ret0,%ret0 ; subtract 16 from bitpos - shd %r0,%arg0,16,%arg0 ; else shift right 16 bits -#else - ldi 15,%ret0 ; Set return to high bit -#endif - extru,= %arg0,31,8,%r0 ; If low 8 bits are non-zero - addi,tr -8,%ret0,%ret0 ; subtract 8 from bitpos - shd %r0,%arg0,8,%arg0 ; else shift right 8 bits - extru,= %arg0,31,4,%r0 ; If low 4 bits are non-zero - addi,tr -4,%ret0,%ret0 ; subtract 4 from bitpos - shd %r0,%arg0,4,%arg0 ; else shift right 4 bits - extru,= %arg0,31,2,%r0 ; If low 2 bits are non-zero - addi,tr -2,%ret0,%ret0 ; subtract 2 from bitpos - shd %r0,%arg0,2,%arg0 ; else shift right 2 bits - extru,= %arg0,31,1,%r0 ; If low bit is non-zero - addi -1,%ret0,%ret0 ; subtract 1 from bitpos -ffsdone: - bv,n 0(%r2) - nop - .EXIT - .PROCEND diff --git a/c/src/exec/score/cpu/hppa1.1/hppa.h b/c/src/exec/score/cpu/hppa1.1/hppa.h deleted file mode 100644 index 87ba027aab..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/hppa.h +++ /dev/null @@ -1,745 +0,0 @@ -/* - * Description: - * - * Definitions for HP PA Risc - * ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual - * - * COPYRIGHT (c) 1994 by Division Incorporated - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Division Incorporated not be - * used in advertising or publicity pertaining to distribution - * of the software without specific, written prior permission. - * Division Incorporated makes no representations about the - * suitability of this software for any purpose. - * - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - * - * $Id$ - */ - -#ifndef _INCLUDE_HPPA_H -#define _INCLUDE_HPPA_H - -#if defined(__cplusplus) -extern "C" { -#endif - -/* - * The following define the CPU Family and Model within the family - * - * NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced - * with the name of the appropriate macro for this target CPU. - */ - -#ifdef hppa1_1 -#undef hppa1_1 -#endif -#define hppa1_1 - -#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL -#undef REPLACE_THIS_WITH_THE_CPU_MODEL -#endif -#define REPLACE_THIS_WITH_THE_CPU_MODEL - -#ifdef REPLACE_THIS_WITH_THE_BSP -#undef REPLACE_THIS_WITH_THE_BSP -#endif -#define REPLACE_THIS_WITH_THE_BSP - -/* - * This section contains the information required to build - * RTEMS for a particular member of the Hewlett Packard - * PA-RISC family. It does this by setting variables to - * indicate which implementation dependent features are - * present in a particular member of the family. - */ - -#if !defined(CPU_MODEL_NAME) - -#if defined(hppa7100) - -#define CPU_MODEL_NAME "hppa 7100" - -#elif defined(hppa7200) - -#define CPU_MODEL_NAME "hppa 7200" - -#else - -#define CPU_MODEL_NAME Unsupported CPU Model /* cause an error on usage */ - -#endif - -#endif /* !defined(CPU_MODEL_NAME) */ - -/* - * Define the name of the CPU family. - */ - -#if !defined(CPU_NAME) -#define CPU_NAME "HP PA-RISC 1.1" -#endif - -/* - * Processor Status Word (PSW) Masks - */ - -#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */ -#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */ -#define HPPA_PSW_r2 0x20000000 /* reserved */ -#define HPPA_PSW_r3 0x10000000 /* reserved */ -#define HPPA_PSW_r4 0x08000000 /* reserved */ -#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */ -#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */ -#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */ -#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/ -#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */ -#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */ -#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */ -#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */ -#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */ -#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */ -#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */ -#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */ -#define HPPA_PSW_r24 0x00000080 /* reserved */ -#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */ -#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */ -#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */ -#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */ -#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */ -#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */ -#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */ - /* Low-Priority Machine Check */ - /* Interruption Enable */ - -/* - * HPPA traps and interrupts - * basic layout. Note numbers do not denote priority - * - * 0-31 basic traps and interrupts defined by HPPA architecture - * 0-31 32 external interrupts - * 32-... bsp defined - */ - -#define HPPA_TRAP_NON_EXISTENT 0 -/* group 1 */ -#define HPPA_TRAP_HIGH_PRIORITY_MACHINE_CHECK 1 -/* group 2 */ -#define HPPA_TRAP_POWER_FAIL 2 -#define HPPA_TRAP_RECOVERY_COUNTER 3 -#define HPPA_TRAP_EXTERNAL_INTERRUPT 4 -#define HPPA_TRAP_LOW_PRIORITY_MACHINE_CHECK 5 -#define HPPA_TRAP_PERFORMANCE_MONITOR 29 -/* group 3 */ -#define HPPA_TRAP_INSTRUCTION_TLB_MISS 6 -#define HPPA_TRAP_INSTRUCTION_MEMORY_PROTECTION 7 -#define HPPA_TRAP_INSTRUCTION_DEBUG 30 -#define HPPA_TRAP_ILLEGAL_INSTRUCTION 8 -#define HPPA_TRAP_BREAK_INSTRUCTION 9 -#define HPPA_TRAP_PRIVILEGED_OPERATION 10 -#define HPPA_TRAP_PRIVILEGED_REGISTER 11 -#define HPPA_TRAP_OVERFLOW 12 -#define HPPA_TRAP_CONDITIONAL 13 -#define HPPA_TRAP_ASSIST_EXCEPTION 14 -#define HPPA_TRAP_DATA_TLB_MISS 15 -#define HPPA_TRAP_NON_ACCESS_INSTRUCTION_TLB_MISS 16 -#define HPPA_TRAP_NON_ACCESS_DATA_TLB_MISS 17 -#define HPPA_TRAP_DATA_MEMORY_ACCESS_RIGHTS 26 -#define HPPA_TRAP_DATA_MEMORY_PROTECTION_ID 27 -#define HPPA_TRAP_UNALIGNED_DATA_REFERENCE 28 -#define HPPA_TRAP_DATA_MEMORY_PROTECTION 18 -#define HPPA_TRAP_DATA_MEMORY_BREAK 19 -#define HPPA_TRAP_TLB_DIRTY_BIT 20 -#define HPPA_TRAP_PAGE_REFERENCE 21 -#define HPPA_TRAP_DATA_DEBUG 31 -#define HPPA_TRAP_ASSIST_EMULATION 22 -/* group 4 */ -#define HPPA_TRAP_HIGHER_PRIVILEGE_TRANSFER 23 -#define HPPA_TRAP_LOWER_PRIVILEGE_TRANSFER 24 -#define HPPA_TRAP_TAKEN_BRANCH 25 - -#define HPPA_INTERNAL_TRAPS 32 - -/* External Interrupts via interrupt 4 */ - -#define HPPA_INTERRUPT_EXTERNAL_0 0 -#define HPPA_INTERRUPT_EXTERNAL_1 1 -#define HPPA_INTERRUPT_EXTERNAL_2 2 -#define HPPA_INTERRUPT_EXTERNAL_3 3 -#define HPPA_INTERRUPT_EXTERNAL_4 4 -#define HPPA_INTERRUPT_EXTERNAL_5 5 -#define HPPA_INTERRUPT_EXTERNAL_6 6 -#define HPPA_INTERRUPT_EXTERNAL_7 7 -#define HPPA_INTERRUPT_EXTERNAL_8 8 -#define HPPA_INTERRUPT_EXTERNAL_9 9 -#define HPPA_INTERRUPT_EXTERNAL_10 10 -#define HPPA_INTERRUPT_EXTERNAL_11 11 -#define HPPA_INTERRUPT_EXTERNAL_12 12 -#define HPPA_INTERRUPT_EXTERNAL_13 13 -#define HPPA_INTERRUPT_EXTERNAL_14 14 -#define HPPA_INTERRUPT_EXTERNAL_15 15 -#define HPPA_INTERRUPT_EXTERNAL_16 16 -#define HPPA_INTERRUPT_EXTERNAL_17 17 -#define HPPA_INTERRUPT_EXTERNAL_18 18 -#define HPPA_INTERRUPT_EXTERNAL_19 19 -#define HPPA_INTERRUPT_EXTERNAL_20 20 -#define HPPA_INTERRUPT_EXTERNAL_21 21 -#define HPPA_INTERRUPT_EXTERNAL_22 22 -#define HPPA_INTERRUPT_EXTERNAL_23 23 -#define HPPA_INTERRUPT_EXTERNAL_24 24 -#define HPPA_INTERRUPT_EXTERNAL_25 25 -#define HPPA_INTERRUPT_EXTERNAL_26 26 -#define HPPA_INTERRUPT_EXTERNAL_27 27 -#define HPPA_INTERRUPT_EXTERNAL_28 28 -#define HPPA_INTERRUPT_EXTERNAL_29 29 -#define HPPA_INTERRUPT_EXTERNAL_30 30 -#define HPPA_INTERRUPT_EXTERNAL_31 31 - -#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0 -#define HPPA_EXTERNAL_INTERRUPTS 32 - -/* BSP defined interrupts begin here */ - -#define HPPA_INTERRUPT_MAX 32 - -/* - * Cache characteristics - */ - -#define HPPA_CACHELINE_SIZE 32 -#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1) - -/* - * page size characteristics - */ - -#define HPPA_PAGE_SIZE 4096 -#define HPPA_PAGE_MASK (0xfffff000) - - -/* - * TLB characteristics - * - * Flags and Access Control layout for using TLB protection insertion - * - * 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 - * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |?|?|T|D|B|type |PL1|Pl2|U| access id |?| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * - */ - -/* - * Access rights (type + PL1 + PL2) - */ -#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */ -#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */ -#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */ -#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */ -#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */ -#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */ -#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */ -#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */ - -/* - * Floating point status register definitions - */ - -#define HPPA_FPSTATUS_ENABLE_I 0x00000001 /* inexact operation */ -#define HPPA_FPSTATUS_ENABLE_U 0x00000002 /* underflow */ -#define HPPA_FPSTATUS_ENABLE_O 0x00000004 /* overflow */ -#define HPPA_FPSTATUS_ENABLE_Z 0x00000008 /* division by zero */ -#define HPPA_FPSTATUS_ENABLE_V 0x00000010 /* invalid operation */ -#define HPPA_FPSTATUS_D 0x00000020 /* denormalize as zero */ -#define HPPA_FPSTATUS_T 0x00000040 /* delayed trap */ -#define HPPA_FPSTATUS_RM_MASK 0x00000600 /* rounding mode */ -#define HPPA_FPSTATUS_RM_SHIFT 9 -#define HPPA_FPSTATUS_CQ_MASK 0x001FFC00 /* compare queue */ -#define HPPA_FPSTATUS_CQ_SHIFT 13 -#define HPPA_FPSTATUS_C 0x04000000 /* most recent ompare bit */ -#define HPPA_FPSTATUS_FLAG_I 0x08000000 /* inexact */ -#define HPPA_FPSTATUS_FLAG_U 0x10000000 /* underflow */ -#define HPPA_FPSTATUS_FLAG_O 0x20000000 /* overflow */ -#define HPPA_FPSTATUS_FLAG_Z 0x40000000 /* division by zero */ -#define HPPA_FPSTATUS_FLAG_V 0x80000000 /* invalid operation */ - - -/* - * Inline macros for misc. interesting opcodes - */ - -/* generate a global label */ -#define HPPA_ASM_LABEL(label) \ - asm(".export " label ", ! .label " label); - -/* Return From Interrupt RFI */ -#define HPPA_ASM_RFI() asm volatile ("rfi") - -/* Set System Mask SSM i,t */ -#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \ - : "=r" (gr) \ - : "i" (i)) -/* Reset System Mask RSM i,t */ -#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \ - : "=r" (gr) \ - : "i" (i)) -/* Move To System Mask MTSM r */ -#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \ - : : "r" (gr)) - -/* Load Space Identifier LDSID (s,b),t */ -#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (grb)) - -/* - * Gcc extended asm doesn't really allow for treatment of space registers - * as "registers", so we have to use "i" format. - * Unfortunately this means that the "=" constraint is not available. - */ - -/* Move To Space Register MTSP r,sr */ -#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \ - : : "i" (sr), \ - "r" (gr)) - -/* Move From Space Register MFSP sr,t */ -#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \ - : "=r" (gr) \ - : "i" (sr)) - -/* Move To Control register MTCTL r,t */ -#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \ - : : "i" (cr), \ - "r" (gr)) - -/* Move From Control register MFCTL r,t */ -#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \ - : "=r" (gr) \ - : "i" (cr)) - -/* Synchronize caches SYNC */ -#define HPPA_ASM_SYNC() asm volatile ("sync") - -/* Probe Read Access PROBER (s,b),r,t */ -#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \ - asm volatile ("prober (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "r" (gracc)) - -/* Probe Read Access Immediate PROBERI (s,b),i,t*/ -#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \ - asm volatile ("proberi (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "i" (iacc)) - -/* Probe Write Access PROBEW (s,b),r,t */ -#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \ - asm volatile ("probew (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "r" (gracc)) - -/* Probe Write Access Immediate PROBEWI (s,b),i,t */ -#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \ - asm volatile ("probewi (%1,%2),%3,%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (groff), \ - "i" (iacc)) - -/* Load Physical Address LPA x(s,b),t */ -#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \ - : "=r" (grt) \ - : "i" (sr), \ - "r" (grb)) - -/* Load Coherence Index LCI x(s,b),t */ -/* AKA: Load Hash Address LHA x(s,b),t */ -#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \ - : "=r" (grt) \ - : "r" (grx),\ - "i" (sr), \ - "r" (grb)) -#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt) - -/* Purge Data Tlb PDTLB x(s,b) */ -#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Instruction Tlb PITLB x(s,b) */ -#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Data Tlb Entry PDTLBE x(s,b) */ -#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Instruction Tlb Entry PITLBE x(s,b) */ -#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - - -/* Insert Data TLB Address IDTLBA r,(s,b) */ -#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Insert Instruction TLB Address IITLBA r,(s,b) */ -#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Insert Data TLB Protection IDTLBP r,(s,b) */ -#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Insert Instruction TLB Protection IITLBP r,(s,b) */ -#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \ - : : "r" (gr), \ - "i" (sr), \ - "r" (grb)) - -/* Purge Data Cache PDC x(s,b) */ -#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Data Cache FDC x(s,b) */ -#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Instruction Cache FDC x(s,b) */ -#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Data Cache Entry FDCE x(s,b) */ -#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Flush Instruction Cache Entry FICE x(s,b) */ -#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \ - : : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Break BREAK i5,i13 */ -#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \ - : : "i" (i5), \ - "i" (i13)) - -/* Load and Clear Word Short LDCWS d(s,b),t */ -#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \ - : "=r" (grt) \ - : "i" (i), \ - "i" (sr), \ - "r" (grb)) - -/* Load and Clear Word Indexed LDCWX x(s,b),t */ -#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \ - : "=r" (grt) \ - : "r" (grx), \ - "i" (sr), \ - "r" (grb)) - -/* Load Word Absolute Short LDWAS d(b),t */ -/* NOTE: "short" here means "short displacement" */ -#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \ - : "=r" (gr) \ - : "i" (disp), \ - "r" (grbase)) - -/* Store Word Absolute Short STWAS r,d(b) */ -/* NOTE: "short" here means "short displacement" */ -#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \ - : : "r" (gr), \ - "i" (disp), \ - "r" (grbase)) - -/* - * Swap bytes - * REFERENCE: PA72000 TRM -- Appendix C - */ -#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \ - " shd %1,%1,16,%0 \n\ - dep %0,15,8,%0 \n\ - shd %1,%0,8,%0" \ - : "=r" (swapped) \ - : "r" (value) \ - ) - - -/* 72000 Diagnose instructions follow - * These macros assume gas knows about these instructions. - * gas2.2.u1 did not. - * I added them to my copy and installed it locally. - * - * There are *very* special requirements for these guys - * ref: TRM 6.1.3 Programming Constraints - * - * The macros below handle the following rules - * - * Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled. - * Must never be nullified (hence the leading nop) - * NOP must preced every RDD,RDT,WDD,WDT,RDTLB - * Instruction preceeding GR_SHDW must not set any of the GR's saved - * - * The macros do *NOT* deal with the following problems - * doubled DIAGNOSE instructions must not straddle a page boundary - * if code translation enabled. (since 2nd could trap on ITLB) - * If you care about DHIT and DPE bits of DR0, then - * No store instruction in the 2 insn window before RDD - */ - - -/* Move To CPU/DIAG register MTCPU r,t */ -#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \ - " mtcpu %1,%0 \n" \ - " mtcpu %1,%0" \ - : : "i" (dr), \ - "r" (gr)) - -/* Move From CPU/DIAG register MFCPU r,t */ -#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \ - " mfcpu %1,%0\n" \ - " mfcpu %1,%0" \ - : "=r" (gr) \ - : "i" (dr)) - -/* Transfer of Control Enable TOC_EN */ -#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \ - " tocen") - -/* Transfer of Control Disable TOC_DIS */ -#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \ - " tocdis") - -/* Shadow Registers to General Register SHDW_GR */ -#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \ - " shdwgr" \ - ::: "r1" "r8" "r9" "r16" \ - "r17" "r24" "r25") - -/* General Registers to Shadow Register GR_SHDW */ -#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \ - " grshdw \n" \ - " grshdw") - -/* - * Definitions of special registers for use by the above macros. - */ - -/* Hardware Space Registers */ -#define HPPA_SR0 0 -#define HPPA_SR1 1 -#define HPPA_SR2 2 -#define HPPA_SR3 3 -#define HPPA_SR4 4 -#define HPPA_SR5 5 -#define HPPA_SR6 6 -#define HPPA_SR7 7 - -/* Hardware Control Registers */ -#define HPPA_CR0 0 -#define HPPA_RCTR 0 /* Recovery Counter Register */ - -#define HPPA_CR8 8 /* Protection ID 1 */ -#define HPPA_PIDR1 8 - -#define HPPA_CR9 9 /* Protection ID 2 */ -#define HPPA_PIDR2 9 - -#define HPPA_CR10 10 -#define HPPA_CCR 10 /* Coprocessor Confiquration Register */ - -#define HPPA_CR11 11 -#define HPPA_SAR 11 /* Shift Amount Register */ - -#define HPPA_CR12 12 -#define HPPA_PIDR3 12 /* Protection ID 3 */ - -#define HPPA_CR13 13 -#define HPPA_PIDR4 13 /* Protection ID 4 */ - -#define HPPA_CR14 14 -#define HPPA_IVA 14 /* Interrupt Vector Address */ - -#define HPPA_CR15 15 -#define HPPA_EIEM 15 /* External Interrupt Enable Mask */ - -#define HPPA_CR16 16 -#define HPPA_ITMR 16 /* Interval Timer */ - -#define HPPA_CR17 17 -#define HPPA_PCSQ 17 /* Program Counter Space queue */ - -#define HPPA_CR18 18 -#define HPPA_PCOQ 18 /* Program Counter Offset queue */ - -#define HPPA_CR19 19 -#define HPPA_IIR 19 /* Interruption Instruction Register */ - -#define HPPA_CR20 20 -#define HPPA_ISR 20 /* Interruption Space Register */ - -#define HPPA_CR21 21 -#define HPPA_IOR 21 /* Interruption Offset Register */ - -#define HPPA_CR22 22 -#define HPPA_IPSW 22 /* Interrpution Processor Status Word */ - -#define HPPA_CR23 23 -#define HPPA_EIRR 23 /* External Interrupt Request */ - -#define HPPA_CR24 24 -#define HPPA_PPDA 24 /* Physcial Page Directory Address */ -#define HPPA_TR0 24 /* Temporary register 0 */ - -#define HPPA_CR25 25 -#define HPPA_HTA 25 /* Hash Table Address */ -#define HPPA_TR1 25 /* Temporary register 1 */ - -#define HPPA_CR26 26 -#define HPPA_TR2 26 /* Temporary register 2 */ - -#define HPPA_CR27 27 -#define HPPA_TR3 27 /* Temporary register 3 */ - -#define HPPA_CR28 28 -#define HPPA_TR4 28 /* Temporary register 4 */ - -#define HPPA_CR29 29 -#define HPPA_TR5 29 /* Temporary register 5 */ - -#define HPPA_CR30 30 -#define HPPA_TR6 30 /* Temporary register 6 */ - -#define HPPA_CR31 31 -#define HPPA_CPUID 31 /* MP identifier */ - -/* - * Diagnose registers - */ - -#define HPPA_DR0 0 -#define HPPA_DR1 1 -#define HPPA_DR8 8 -#define HPPA_DR24 24 -#define HPPA_DR25 25 - -/* - * Tear apart a break instruction to find its type. - */ -#define HPPA_BREAK5(x) ((x) & 0x1F) -#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF) - -/* assemble a break instruction */ -#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) | (((i13) & 0x1FFF) << 13)) - - -/* - * this won't work in ASM or non-GNU compilers - */ - -#if !defined(ASM) && defined(__GNUC__) - -/* - * static inline utility functions to get at control registers - */ - -#define EMIT_GET_CONTROL(name, reg) \ -static __inline__ unsigned int \ -get_ ## name (void) \ -{ \ - unsigned int value; \ - HPPA_ASM_MFCTL(reg, value); \ - return value; \ -} - -#define EMIT_SET_CONTROL(name, reg) \ -static __inline__ void \ -set_ ## name (unsigned int new_value) \ -{ \ - HPPA_ASM_MTCTL(new_value, reg); \ -} - -#define EMIT_CONTROLS(name, reg) \ - EMIT_GET_CONTROL(name, reg) \ - EMIT_SET_CONTROL(name, reg) - -EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */ -EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */ -EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */ -EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */ -EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */ -EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */ -EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */ -EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */ -EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */ -EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */ -EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */ -EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */ -EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */ -EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */ -EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */ -EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */ -EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */ -EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */ -EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */ -EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */ -EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */ -EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */ -EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */ -EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */ -EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */ -EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */ - -#endif /* ASM and GNU */ - -/* - * If and How to invoke the debugger (a ROM debugger generally) - */ -#define CPU_INVOKE_DEBUGGER \ - do { \ - HPPA_ASM_BREAK(1,1); \ - } while (0) - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_HPPA_H */ - diff --git a/c/src/exec/score/cpu/hppa1.1/hppatypes.h b/c/src/exec/score/cpu/hppa1.1/hppatypes.h deleted file mode 100644 index 512323819b..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/hppatypes.h +++ /dev/null @@ -1,46 +0,0 @@ -/* hppatypes.h - * - * This include file contains type definitions pertaining to the Hewlett - * Packard PA-RISC processor family. - * - * $Id$ - */ - -#ifndef _INCLUDE_HPPATYPES_H -#define _INCLUDE_HPPATYPES_H - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* 8-bit unsigned integer */ -typedef unsigned short unsigned16; /* 16-bit unsigned integer */ -typedef unsigned int unsigned32; /* 32-bit unsigned integer */ -typedef unsigned long long unsigned64; /* 64-bit unsigned integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif /* _INCLUDE_HPPATYPES_H */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/hppa1.1/rtems.s b/c/src/exec/score/cpu/hppa1.1/rtems.s deleted file mode 100644 index 06de39dddf..0000000000 --- a/c/src/exec/score/cpu/hppa1.1/rtems.s +++ /dev/null @@ -1,53 +0,0 @@ -/* rtems.S - * - * This file contains the single entry point code for - * the HPPA implementation of RTEMS. - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * All rights assigned to U.S. Government, 1994. - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - */ - -#include <rtems/score/hppa.h> -#include <rtems/score/cpu_asm.h> - - .SPACE $PRIVATE$ - .SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31 - .SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82 - .SPACE $TEXT$ - .SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44 - .SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY - .SPACE $TEXT$ - .SUBSPA $CODE$ - - .align 32 - .EXPORT cpu_jump_to_directive,ENTRY,PRIV_LEV=0 -cpu_jump_to_directive - .PROC - .CALLINFO FRAME=0,NO_CALLS - .ENTRY - -# invoke user interrupt handler - -# XXX: look at register usage and code -# XXX: this is not necessarily right!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -# r9 = directive number - - .import _Entry_points,data - ldil L%_Entry_points,%r8 - ldo R%_Entry_points(%r8),%r8 - ldwx,s %r9(%r8),%r8 - - .call ARGW0=GR - bv,n 0(%r8) - nop - - .EXIT - .PROCEND - diff --git a/c/src/exec/score/cpu/mips/asm.h b/c/src/exec/score/cpu/mips/asm.h deleted file mode 100644 index d45405b669..0000000000 --- a/c/src/exec/score/cpu/mips/asm.h +++ /dev/null @@ -1,99 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ -/* @(#)asm.h 03/15/96 1.1 */ - -#ifndef __NO_CPU_ASM_h -#define __NO_CPU_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#define ASM -#include <rtems/score/no_cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/mips/cpu.c b/c/src/exec/score/cpu/mips/cpu.c deleted file mode 100644 index 5088c2ad84..0000000000 --- a/c/src/exec/score/cpu/mips/cpu.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Mips CPU Dependent Source - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/score/cpu/no_cpu/cpu.c: - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * All rights assigned to U.S. Government, 1994. - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - */ - -#ifndef lint -static char _sccsid[] = "@(#)cpu.c 08/20/96 1.5\n"; -#endif - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> - - -ISR_Handler_entry _ISR_Vector_table[ ISR_NUMBER_OF_VECTORS ]; - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void null_handler( void ) -{ -} - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - unsigned int i = ISR_NUMBER_OF_VECTORS; - - while ( i-- ) - { - _ISR_Vector_table[i] = (ISR_Handler_entry)null_handler; - } - - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - - _CPU_Table = *cpu_table; - -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -#if 0 /* located in cpu_asm.S */ -unsigned32 _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ -} -#endif - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ - -#if 0 /* not necessary */ -/* use IDT/Sim to set interrupt vector. Needed to co-exist with debugger. */ - add_ext_int_func( vector, new_handler ); -#endif -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler ); - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -/* we don't support this yet */ -} - -/*PAGE - * - * _CPU_Internal_threads_Idle_thread_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -#if 0 /* located in cpu_asm.S */ -void _CPU_Thread_Idle_body( void ) -{ - - for( ; ; ) - /* insert your "halt" instruction here */ ; -} -#endif - -extern void mips_break( int error ); - -#include <stdio.h> - -void mips_fatal_error( int error ) -{ - printf("fatal error 0x%x %d\n",error,error); - mips_break( error ); -} diff --git a/c/src/exec/score/cpu/mips/cpu_asm.S b/c/src/exec/score/cpu/mips/cpu_asm.S deleted file mode 100644 index 9f95229b8f..0000000000 --- a/c/src/exec/score/cpu/mips/cpu_asm.S +++ /dev/null @@ -1,972 +0,0 @@ -/* cpu_asm.S - * - * This file contains the basic algorithms for all assembly code used - * in an specific CPU port of RTEMS. These algorithms must be implemented - * in assembly language - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s: - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * All rights assigned to U.S. Government, 1994. - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - */ -/* @(#)cpu_asm.S 08/20/96 1.15 */ - -#include "cpu_asm.h" - -#include "iregdef.h" -#include "idtcpu.h" - -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl name; \ - .ent name; \ -name:; \ - .frame frm_reg,offset,ret_reg -#define ENDFRAME(name) \ - .end name - - -#define EXCP_STACK_SIZE (NREGS*R_SZ) - -#if __ghs__ -#define sd sw -#define ld lw -#define dmtc0 mtc0 -#define dsll sll -#define dmfc0 mfc0 -#endif - -#if 1 /* 32 bit unsigned32 types */ -#define sint sw -#define lint lw -#define stackadd addiu -#define intadd addu -#define SZ_INT 4 -#define SZ_INT_POW2 2 -#else /* 64 bit unsigned32 types */ -#define sint dw -#define lint dw -#define stackadd daddiu -#define intadd daddu -#define SZ_INT 8 -#define SZ_INT_POW2 3 -#endif - -#ifdef __GNUC__ -#define EXTERN(x,size) .extern x,size -#else -#define EXTERN(x,size) -#endif - -/* NOTE: these constants must match the Context_Control structure in cpu.h */ -#define S0_OFFSET 0 -#define S1_OFFSET 1 -#define S2_OFFSET 2 -#define S3_OFFSET 3 -#define S4_OFFSET 4 -#define S5_OFFSET 5 -#define S6_OFFSET 6 -#define S7_OFFSET 7 -#define SP_OFFSET 8 -#define FP_OFFSET 9 -#define RA_OFFSET 10 -#define C0_SR_OFFSET 11 -#define C0_EPC_OFFSET 12 - -/* NOTE: these constants must match the Context_Control_fp structure in cpu.h */ -#define FP0_OFFSET 0 -#define FP1_OFFSET 1 -#define FP2_OFFSET 2 -#define FP3_OFFSET 3 -#define FP4_OFFSET 4 -#define FP5_OFFSET 5 -#define FP6_OFFSET 6 -#define FP7_OFFSET 7 -#define FP8_OFFSET 8 -#define FP9_OFFSET 9 -#define FP10_OFFSET 10 -#define FP11_OFFSET 11 -#define FP12_OFFSET 12 -#define FP13_OFFSET 13 -#define FP14_OFFSET 14 -#define FP15_OFFSET 15 -#define FP16_OFFSET 16 -#define FP17_OFFSET 17 -#define FP18_OFFSET 18 -#define FP19_OFFSET 19 -#define FP20_OFFSET 20 -#define FP21_OFFSET 21 -#define FP22_OFFSET 22 -#define FP23_OFFSET 23 -#define FP24_OFFSET 24 -#define FP25_OFFSET 25 -#define FP26_OFFSET 26 -#define FP27_OFFSET 27 -#define FP28_OFFSET 28 -#define FP29_OFFSET 29 -#define FP30_OFFSET 30 -#define FP31_OFFSET 31 - - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -#if 0 -unsigned32 _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ -} -#endif -/* return the current exception level for the 4650 */ -FRAME(_CPU_ISR_Get_level,sp,0,ra) - mfc0 v0,C0_SR - nop - andi v0,SR_EXL - srl v0,1 - j ra -ENDFRAME(_CPU_ISR_Get_level) - -FRAME(_CPU_ISR_Set_level,sp,0,ra) - nop - mfc0 a0,C0_SR - nop - andi a0,SR_EXL - beqz a0,_CPU_ISR_Set_1 /* normalize a0 */ - nop - li a0,1 -_CPU_ISR_Set_1: - beq v0,a0,_CPU_ISR_Set_exit /* if (current_level != new_level ) */ - nop - bnez a0,_CPU_ISR_Set_2 - nop - nop - mfc0 t0,C0_SR - nop - li t1,~SR_EXL - and t0,t1 - nop - mtc0 t0,C0_SR /* disable exception level */ - nop - j ra - nop -_CPU_ISR_Set_2: - nop - mfc0 t0,C0_SR - nop - li t1,~SR_IE - and t0,t1 - nop - mtc0 t0,C0_SR /* first disable ie bit (recommended) */ - nop - ori t0,SR_EXL|SR_IE /* enable exception level */ - nop - mtc0 t0,C0_SR - nop -_CPU_ISR_Set_exit: - j ra - nop -ENDFRAME(_CPU_ISR_Set_level) - -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -/* void _CPU_Context_save_fp( - * void **fp_context_ptr - * ) - * { - * } - */ - -FRAME(_CPU_Context_save_fp,sp,0,ra) - .set noat - ld a1,(a0) - swc1 $f0,FP0_OFFSET*4(a1) - swc1 $f1,FP1_OFFSET*4(a1) - swc1 $f2,FP2_OFFSET*4(a1) - swc1 $f3,FP3_OFFSET*4(a1) - swc1 $f4,FP4_OFFSET*4(a1) - swc1 $f5,FP5_OFFSET*4(a1) - swc1 $f6,FP6_OFFSET*4(a1) - swc1 $f7,FP7_OFFSET*4(a1) - swc1 $f8,FP8_OFFSET*4(a1) - swc1 $f9,FP9_OFFSET*4(a1) - swc1 $f10,FP10_OFFSET*4(a1) - swc1 $f11,FP11_OFFSET*4(a1) - swc1 $f12,FP12_OFFSET*4(a1) - swc1 $f13,FP13_OFFSET*4(a1) - swc1 $f14,FP14_OFFSET*4(a1) - swc1 $f15,FP15_OFFSET*4(a1) - swc1 $f16,FP16_OFFSET*4(a1) - swc1 $f17,FP17_OFFSET*4(a1) - swc1 $f18,FP18_OFFSET*4(a1) - swc1 $f19,FP19_OFFSET*4(a1) - swc1 $f20,FP20_OFFSET*4(a1) - swc1 $f21,FP21_OFFSET*4(a1) - swc1 $f22,FP22_OFFSET*4(a1) - swc1 $f23,FP23_OFFSET*4(a1) - swc1 $f24,FP24_OFFSET*4(a1) - swc1 $f25,FP25_OFFSET*4(a1) - swc1 $f26,FP26_OFFSET*4(a1) - swc1 $f27,FP27_OFFSET*4(a1) - swc1 $f28,FP28_OFFSET*4(a1) - swc1 $f29,FP29_OFFSET*4(a1) - swc1 $f30,FP30_OFFSET*4(a1) - swc1 $f31,FP31_OFFSET*4(a1) - j ra - nop - .set at -ENDFRAME(_CPU_Context_save_fp) - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - -/* void _CPU_Context_restore_fp( - * void **fp_context_ptr - * ) - * { - * } - */ - -FRAME(_CPU_Context_restore_fp,sp,0,ra) - .set noat - ld a1,(a0) - lwc1 $f0,FP0_OFFSET*4(a1) - lwc1 $f1,FP1_OFFSET*4(a1) - lwc1 $f2,FP2_OFFSET*4(a1) - lwc1 $f3,FP3_OFFSET*4(a1) - lwc1 $f4,FP4_OFFSET*4(a1) - lwc1 $f5,FP5_OFFSET*4(a1) - lwc1 $f6,FP6_OFFSET*4(a1) - lwc1 $f7,FP7_OFFSET*4(a1) - lwc1 $f8,FP8_OFFSET*4(a1) - lwc1 $f9,FP9_OFFSET*4(a1) - lwc1 $f10,FP10_OFFSET*4(a1) - lwc1 $f11,FP11_OFFSET*4(a1) - lwc1 $f12,FP12_OFFSET*4(a1) - lwc1 $f13,FP13_OFFSET*4(a1) - lwc1 $f14,FP14_OFFSET*4(a1) - lwc1 $f15,FP15_OFFSET*4(a1) - lwc1 $f16,FP16_OFFSET*4(a1) - lwc1 $f17,FP17_OFFSET*4(a1) - lwc1 $f18,FP18_OFFSET*4(a1) - lwc1 $f19,FP19_OFFSET*4(a1) - lwc1 $f20,FP20_OFFSET*4(a1) - lwc1 $f21,FP21_OFFSET*4(a1) - lwc1 $f22,FP22_OFFSET*4(a1) - lwc1 $f23,FP23_OFFSET*4(a1) - lwc1 $f24,FP24_OFFSET*4(a1) - lwc1 $f25,FP25_OFFSET*4(a1) - lwc1 $f26,FP26_OFFSET*4(a1) - lwc1 $f27,FP27_OFFSET*4(a1) - lwc1 $f28,FP28_OFFSET*4(a1) - lwc1 $f29,FP29_OFFSET*4(a1) - lwc1 $f30,FP30_OFFSET*4(a1) - lwc1 $f31,FP31_OFFSET*4(a1) - j ra - nop - .set at -ENDFRAME(_CPU_Context_restore_fp) - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - */ - -/* void _CPU_Context_switch( - * Context_Control *run, - * Context_Control *heir - * ) - * { - * } - */ - -FRAME(_CPU_Context_switch,sp,0,ra) - - mfc0 t0,C0_SR - li t1,~SR_IE - sd t0,C0_SR_OFFSET*8(a0) /* save status register */ - and t0,t1 - mtc0 t0,C0_SR /* first disable ie bit (recommended) */ - ori t0,SR_EXL|SR_IE /* enable exception level to disable interrupts */ - mtc0 t0,C0_SR - - sd ra,RA_OFFSET*8(a0) /* save current context */ - sd sp,SP_OFFSET*8(a0) - sd fp,FP_OFFSET*8(a0) - sd s0,S0_OFFSET*8(a0) - sd s1,S1_OFFSET*8(a0) - sd s2,S2_OFFSET*8(a0) - sd s3,S3_OFFSET*8(a0) - sd s4,S4_OFFSET*8(a0) - sd s5,S5_OFFSET*8(a0) - sd s6,S6_OFFSET*8(a0) - sd s7,S7_OFFSET*8(a0) - dmfc0 t0,C0_EPC - sd t0,C0_EPC_OFFSET*8(a0) - -_CPU_Context_switch_restore: - ld s0,S0_OFFSET*8(a1) /* restore context */ - ld s1,S1_OFFSET*8(a1) - ld s2,S2_OFFSET*8(a1) - ld s3,S3_OFFSET*8(a1) - ld s4,S4_OFFSET*8(a1) - ld s5,S5_OFFSET*8(a1) - ld s6,S6_OFFSET*8(a1) - ld s7,S7_OFFSET*8(a1) - ld fp,FP_OFFSET*8(a1) - ld sp,SP_OFFSET*8(a1) - ld ra,RA_OFFSET*8(a1) - ld t0,C0_EPC_OFFSET*8(a1) - dmtc0 t0,C0_EPC - ld t0,C0_SR_OFFSET*8(a1) - andi t0,SR_EXL - bnez t0,_CPU_Context_1 /* set exception level from restore context */ - li t0,~SR_EXL - mfc0 t1,C0_SR - nop - and t1,t0 - mtc0 t1,C0_SR -_CPU_Context_1: - j ra - nop -ENDFRAME(_CPU_Context_switch) - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -#if 0 -void _CPU_Context_restore( - Context_Control *new_context -) -{ -} -#endif - -FRAME(_CPU_Context_restore,sp,0,ra) - dadd a1,a0,zero - j _CPU_Context_switch_restore - nop -ENDFRAME(_CPU_Context_restore) - -EXTERN(_ISR_Nest_level, SZ_INT) -EXTERN(_Thread_Dispatch_disable_level,SZ_INT) -EXTERN(_Context_Switch_necessary,SZ_INT) -EXTERN(_ISR_Signals_to_thread_executing,SZ_INT) -.extern _Thread_Dispatch -.extern _ISR_Vector_table - -/* void __ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * - */ - -#if 0 -void _ISR_Handler() -{ - /* - * This discussion ignores a lot of the ugly details in a real - * implementation such as saving enough registers/state to be - * able to do something real. Keep in mind that the goal is - * to invoke a user's ISR handler which is written in C and - * uses a certain set of registers. - * - * Also note that the exact order is to a large extent flexible. - * Hardware will dictate a sequence for a certain subset of - * _ISR_Handler while requirements for setting - */ - - /* - * At entry to "common" _ISR_Handler, the vector number must be - * available. On some CPUs the hardware puts either the vector - * number or the offset into the vector table for this ISR in a - * known place. If the hardware does not give us this information, - * then the assembly portion of RTEMS for this port will contain - * a set of distinct interrupt entry points which somehow place - * the vector number in a known place (which is safe if another - * interrupt nests this one) and branches to _ISR_Handler. - * - */ -#endif -FRAME(_ISR_Handler,sp,0,ra) -.set noreorder -#if USE_IDTKIT -/* IDT/Kit incorrectly adds 4 to EPC before returning. This compensates */ - lreg k0, R_EPC*R_SZ(sp) - daddiu k0,k0,-4 - sreg k0, R_EPC*R_SZ(sp) - lreg k0, R_CAUSE*R_SZ(sp) - li k1, ~CAUSE_BD - and k0, k1 - sreg k0, R_CAUSE*R_SZ(sp) -#endif - -/* save registers not already saved by IDT/sim */ - stackadd sp,sp,-EXCP_STACK_SIZE /* store ra on the stack */ - - sreg ra, R_RA*R_SZ(sp) - sreg v0, R_V0*R_SZ(sp) - sreg v1, R_V1*R_SZ(sp) - sreg a0, R_A0*R_SZ(sp) - sreg a1, R_A1*R_SZ(sp) - sreg a2, R_A2*R_SZ(sp) - sreg a3, R_A3*R_SZ(sp) - sreg t0, R_T0*R_SZ(sp) - sreg t1, R_T1*R_SZ(sp) - sreg t2, R_T2*R_SZ(sp) - sreg t3, R_T3*R_SZ(sp) - sreg t4, R_T4*R_SZ(sp) - sreg t5, R_T5*R_SZ(sp) - sreg t6, R_T6*R_SZ(sp) - sreg t7, R_T7*R_SZ(sp) - mflo k0 - sreg t8, R_T8*R_SZ(sp) - sreg k0, R_MDLO*R_SZ(sp) - sreg t9, R_T9*R_SZ(sp) - mfhi k0 - sreg gp, R_GP*R_SZ(sp) - sreg fp, R_FP*R_SZ(sp) - sreg k0, R_MDHI*R_SZ(sp) - .set noat - sreg AT, R_AT*R_SZ(sp) - .set at - - stackadd sp,sp,-40 /* store ra on the stack */ - sd ra,32(sp) - -/* determine if an interrupt generated this exception */ - mfc0 k0,C0_CAUSE - and k1,k0,CAUSE_EXCMASK - bnez k1,_ISR_Handler_prom_exit /* not an external interrupt, pass exception to Monitor */ - mfc0 k1,C0_SR - and k0,k1 - and k0,CAUSE_IPMASK - beq k0,zero,_ISR_Handler_quick_exit /* external interrupt not enabled, ignore */ - nop - - /* - * save some or all context on stack - * may need to save some special interrupt information for exit - * - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * if ( _ISR_Nest_level == 0 ) - * switch to software interrupt stack - * #endif - */ -#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - lint t0,_ISR_Nest_level - beq t0, zero, _ISR_Handler_1 - nop - /* switch stacks */ -_ISR_Handler_1: -#else - lint t0,_ISR_Nest_level -#endif - /* - * _ISR_Nest_level++; - */ - addi t0,t0,1 - sint t0,_ISR_Nest_level - /* - * _Thread_Dispatch_disable_level++; - */ - lint t1,_Thread_Dispatch_disable_level - addi t1,t1,1 - sint t1,_Thread_Dispatch_disable_level -#if 0 - nop - j _ISR_Handler_4 - nop - /* - * while ( interrupts_pending(cause_reg) ) { - * vector = BITFIELD_TO_INDEX(cause_reg); - * (*_ISR_Vector_table[ vector ])( vector ); - * } - */ -_ISR_Handler_2: -/* software interrupt priorities can be applied here */ - li t1,-1 -/* convert bit field into interrupt index */ -_ISR_Handler_3: - andi t2,t0,1 - addi t1,1 - beql t2,zero,_ISR_Handler_3 - dsrl t0,1 - li t1,7 - dsll t1,3 /* convert index to byte offset (*8) */ - la t3,_ISR_Vector_table - intadd t1,t3 - lint t1,(t1) - jalr t1 - nop - j _ISR_Handler_5 - nop -_ISR_Handler_4: - mfc0 t0,C0_CAUSE - andi t0,CAUSE_IPMASK - bne t0,zero,_ISR_Handler_2 - dsrl t0,t0,8 -_ISR_Handler_5: -#else - nop - li t1,7 - dsll t1,t1,SZ_INT_POW2 - la t3,_ISR_Vector_table - intadd t1,t3 - lint t1,(t1) - jalr t1 - nop -#endif - /* - * --_ISR_Nest_level; - */ - lint t2,_ISR_Nest_level - addi t2,t2,-1 - sint t2,_ISR_Nest_level - /* - * --_Thread_Dispatch_disable_level; - */ - lint t1,_Thread_Dispatch_disable_level - addi t1,t1,-1 - sint t1,_Thread_Dispatch_disable_level - /* - * if ( _Thread_Dispatch_disable_level || _ISR_Nest_level ) - * goto the label "exit interrupt (simple case)" - */ - or t0,t2,t1 - bne t0,zero,_ISR_Handler_exit - nop - /* - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * restore stack - * #endif - * - * if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing ) - * goto the label "exit interrupt (simple case)" - */ - lint t0,_Context_Switch_necessary - lint t1,_ISR_Signals_to_thread_executing - or t0,t0,t1 - beq t0,zero,_ISR_Handler_exit - nop - - /* - * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch - */ - jal _Thread_Dispatch - nop - /* - * prepare to get out of interrupt - * return from interrupt (maybe to _ISR_Dispatch) - * - * LABEL "exit interrupt (simple case): - * prepare to get out of interrupt - * return from interrupt - */ -_ISR_Handler_exit: - ld ra,32(sp) - stackadd sp,sp,40 - -/* restore interrupt context from stack */ - lreg k0, R_MDLO*R_SZ(sp) - mtlo k0 - lreg k0, R_MDHI*R_SZ(sp) - lreg a2, R_A2*R_SZ(sp) - mthi k0 - lreg a3, R_A3*R_SZ(sp) - lreg t0, R_T0*R_SZ(sp) - lreg t1, R_T1*R_SZ(sp) - lreg t2, R_T2*R_SZ(sp) - lreg t3, R_T3*R_SZ(sp) - lreg t4, R_T4*R_SZ(sp) - lreg t5, R_T5*R_SZ(sp) - lreg t6, R_T6*R_SZ(sp) - lreg t7, R_T7*R_SZ(sp) - lreg t8, R_T8*R_SZ(sp) - lreg t9, R_T9*R_SZ(sp) - lreg gp, R_GP*R_SZ(sp) - lreg fp, R_FP*R_SZ(sp) - lreg ra, R_RA*R_SZ(sp) - lreg a0, R_A0*R_SZ(sp) - lreg a1, R_A1*R_SZ(sp) - lreg v1, R_V1*R_SZ(sp) - lreg v0, R_V0*R_SZ(sp) - .set noat - lreg AT, R_AT*R_SZ(sp) - .set at - - stackadd sp,sp,EXCP_STACK_SIZE /* store ra on the stack */ - -#if USE_IDTKIT -/* we handled exception, so return non-zero value */ - li v0,1 -#endif - -_ISR_Handler_quick_exit: -#ifdef USE_IDTKIT - j ra -#else - eret -#endif - nop - -_ISR_Handler_prom_exit: -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif - j k0 - nop - - .set reorder - -ENDFRAME(_ISR_Handler) - - -FRAME(mips_enable_interrupts,sp,0,ra) - mfc0 t0,C0_SR /* get status reg */ - nop - or t0,t0,a0 - mtc0 t0,C0_SR /* save updated status reg */ - j ra - nop -ENDFRAME(mips_enable_interrupts) - -FRAME(mips_disable_interrupts,sp,0,ra) - mfc0 v0,C0_SR /* get status reg */ - li t1,SR_IMASK /* t1 = load interrupt mask word */ - not t0,t1 /* t0 = ~t1 */ - and t0,v0 /* clear imask bits */ - mtc0 t0,C0_SR /* save status reg */ - and v0,t1 /* mask return value (only return imask bits) */ - jr ra - nop -ENDFRAME(mips_disable_interrupts) - -FRAME(mips_enable_global_interrupts,sp,0,ra) - mfc0 t0,C0_SR /* get status reg */ - nop - ori t0,SR_IE - mtc0 t0,C0_SR /* save updated status reg */ - j ra - nop -ENDFRAME(mips_enable_global_interrupts) - -FRAME(mips_disable_global_interrupts,sp,0,ra) - li t1,SR_IE - mfc0 t0,C0_SR /* get status reg */ - not t1 - and t0,t1 - mtc0 t0,C0_SR /* save updated status reg */ - j ra - nop -ENDFRAME(mips_disable_global_interrupts) - -/* return the value of the status register in v0. Used for debugging */ -FRAME(mips_get_sr,sp,0,ra) - mfc0 v0,C0_SR - j ra - nop -ENDFRAME(mips_get_sr) - -FRAME(mips_break,sp,0,ra) -#if 1 - break 0x0 - j mips_break -#else - j ra -#endif - nop -ENDFRAME(mips_break) - -/*PAGE - * - * _CPU_Internal_threads_Idle_thread_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -FRAME(_CPU_Thread_Idle_body,sp,0,ra) - wait /* enter low power mode */ - j _CPU_Thread_Idle_body - nop -ENDFRAME(_CPU_Thread_Idle_body) - -#define VEC_CODE_LENGTH 10*4 - -/************************************************************************** -** -** init_exc_vecs() - moves the exception code into the addresses -** reserved for exception vectors -** -** UTLB Miss exception vector at address 0x80000000 -** -** General exception vector at address 0x80000080 -** -** RESET exception vector is at address 0xbfc00000 -** -***************************************************************************/ - -#define INITEXCFRM ((2*4)+4) /* ra + 2 arguments */ -FRAME(init_exc_vecs,sp,0,ra) -/* This code yanked from SIM */ -#if defined(CPU_R3000) - .set noreorder - la t1,exc_utlb_code - la t2,exc_norm_code - li t3,UT_VEC - li t4,E_VEC - li t5,VEC_CODE_LENGTH -1: - lw t6,0(t1) - lw t7,0(t2) - sw t6,0(t3) - sw t7,0(t4) - addiu t1,4 - addiu t3,4 - addiu t4,4 - subu t5,4 - bne t5,zero,1b - addiu t2,4 - move t5,ra # assumes clear_cache doesnt use t5 - li a0,UT_VEC - jal clear_cache - li a1,VEC_CODE_LENGTH - nop - li a0,E_VEC - jal clear_cache - li a1,VEC_CODE_LENGTH - move ra,t5 # restore ra - j ra - nop - .set reorder -#endif -#if defined(CPU_R4000) - .set reorder - move t5,ra # assumes clear_cache doesnt use t5 - - /* TLB exception vector */ - la t1,exc_tlb_code - li t2,T_VEC |K1BASE - li t3,VEC_CODE_LENGTH -1: - lw t6,0(t1) - addiu t1,4 - subu t3,4 - sw t6,0(t2) - addiu t2,4 - bne t3,zero,1b - - li a0,T_VEC - li a1,VEC_CODE_LENGTH - jal clear_cache - - la t1,exc_xtlb_code - li t2,X_VEC |K1BASE - li t3,VEC_CODE_LENGTH -1: - lw t6,0(t1) - addiu t1,4 - subu t3,4 - sw t6,0(t2) - addiu t2,4 - bne t3,zero,1b - - /* extended TLB exception vector */ - li a0,X_VEC - li a1,VEC_CODE_LENGTH - jal clear_cache - - /* cache error exception vector */ - la t1,exc_cache_code - li t2,C_VEC |K1BASE - li t3,VEC_CODE_LENGTH -1: - lw t6,0(t1) - addiu t1,4 - subu t3,4 - sw t6,0(t2) - addiu t2,4 - bne t3,zero,1b - - li a0,C_VEC - li a1,VEC_CODE_LENGTH - jal clear_cache - - /* normal exception vector */ - la t1,exc_norm_code - li t2,E_VEC |K1BASE - li t3,VEC_CODE_LENGTH -1: - lw t6,0(t1) - addiu t1,4 - subu t3,4 - sw t6,0(t2) - addiu t2,4 - bne t3,zero,1b - - li a0,E_VEC - li a1,VEC_CODE_LENGTH - jal clear_cache - - move ra,t5 # restore ra - j ra -#endif -ENDFRAME(init_exc_vecs) - - -#if defined(CPU_R4000) -FRAME(exc_tlb_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif - j k0 - nop - -ENDFRAME(exc_tlb_code) - - -FRAME(exc_xtlb_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif - j k0 - nop - -ENDFRAME(exc_xtlb_code) - - -FRAME(exc_cache_code,sp,0,ra) -#ifdef CPU_R3000 - la k0, (R_VEC+((48)*8)) -#endif - -#ifdef CPU_R4000 - la k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */ -#endif - j k0 - nop - -ENDFRAME(exc_cache_code) - - -FRAME(exc_norm_code,sp,0,ra) - la k0, _ISR_Handler /* generic external int hndlr */ - j k0 - nop - subu sp, EXCP_STACK_SIZE /* set up local stack frame */ -ENDFRAME(exc_norm_code) -#endif - -/************************************************************************** -** -** enable_int(mask) - enables interrupts - mask is positioned so it only -** needs to be or'ed into the status reg. This -** also does some other things !!!! caution should -** be used if invoking this while in the middle -** of a debugging session where the client may have -** nested interrupts. -** -****************************************************************************/ -FRAME(enable_int,sp,0,ra) - .set noreorder - mfc0 t0,C0_SR - or a0,1 - or t0,a0 - mtc0 t0,C0_SR - j ra - nop - .set reorder -ENDFRAME(enable_int) - - -/*************************************************************************** -** -** disable_int(mask) - disable the interrupt - mask is the complement -** of the bits to be cleared - i.e. to clear ext int -** 5 the mask would be - 0xffff7fff -** -****************************************************************************/ -FRAME(disable_int,sp,0,ra) - .set noreorder - mfc0 t0,C0_SR - nop - and t0,a0 - mtc0 t0,C0_SR - j ra - nop -ENDFRAME(disable_int) - - diff --git a/c/src/exec/score/cpu/mips/cpu_asm.h b/c/src/exec/score/cpu/mips/cpu_asm.h deleted file mode 100644 index 8c104bfdb4..0000000000 --- a/c/src/exec/score/cpu/mips/cpu_asm.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * cpu_asm.h - * - * Author: Craig Lebakken <craigl@transition.com> - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.h: - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - * - */ -/* @(#)cpu_asm.h 08/20/96 1.2 */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - -/* pull in the generated offsets */ - -/* #include <rtems/score/offsets.h> */ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -#define R_FP0 0 -#define R_FP1 1 -#define R_FP2 2 -#define R_FP3 3 -#define R_FP4 4 -#define R_FP5 5 -#define R_FP6 6 -#define R_FP7 7 -#define R_FP8 8 -#define R_FP9 9 -#define R_FP10 10 -#define R_FP11 11 -#define R_FP12 12 -#define R_FP13 13 -#define R_FP14 14 -#define R_FP15 15 -#define R_FP16 16 -#define R_FP17 17 -#define R_FP18 18 -#define R_FP19 19 -#define R_FP20 20 -#define R_FP21 21 -#define R_FP22 22 -#define R_FP23 23 -#define R_FP24 24 -#define R_FP25 25 -#define R_FP26 26 -#define R_FP27 27 -#define R_FP28 28 -#define R_FP29 29 -#define R_FP30 30 -#define R_FP31 31 - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/c/src/exec/score/cpu/mips/idtcpu.h b/c/src/exec/score/cpu/mips/idtcpu.h deleted file mode 100644 index f921e85ef6..0000000000 --- a/c/src/exec/score/cpu/mips/idtcpu.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - - $Id$ -*/ - -/* -** idtcpu.h -- cpu related defines -*/ - -#ifndef _IDTCPU_H__ -#define _IDTCPU_H__ - -/* - * 950313: Ketan added Register definition for XContext reg. - * added define for WAIT instruction. - * 950421: Ketan added Register definition for Config reg (R3081) - */ - -/* -** memory configuration and mapping -*/ -#define K0BASE 0x80000000 -#define K0SIZE 0x20000000 -#define K1BASE 0xa0000000 -#define K1SIZE 0x20000000 -#define K2BASE 0xc0000000 -#define K2SIZE 0x20000000 -#if defined(CPU_R4000) -#define KSBASE 0xe0000000 -#define KSSIZE 0x20000000 -#endif - -#define KUBASE 0 -#define KUSIZE 0x80000000 - -/* -** Exception Vectors -*/ -#if defined(CPU_R3000) -#define UT_VEC K0BASE /* utlbmiss vector */ -#define E_VEC (K0BASE+0x80) /* exception vevtor */ -#endif -#if defined(CPU_R4000) -#define T_VEC (K0BASE+0x000) /* tlbmiss vector */ -#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ -#define C_VEC (K0BASE+0x100) /* cache error vector */ -#define E_VEC (K0BASE+0x180) /* exception vector */ -#endif -#define R_VEC (K1BASE+0x1fc00000) /* reset vector */ - -/* -** Address conversion macros -*/ -#ifdef CLANGUAGE -#define CAST(as) (as) -#else -#define CAST(as) -#endif -#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */ -#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */ -#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */ -#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */ -#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to kseg0 */ -#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to kseg1 */ - -/* -** Cache size constants -*/ -#define MINCACHE 0x200 /* 512 For 3041. */ -#define MAXCACHE 0x40000 /* 256*1024 256k */ - -#if defined(CPU_R4000) -/* R4000 configuration register definitions */ -#define CFG_CM 0x80000000 /* Master-Checker mode */ -#define CFG_ECMASK 0x70000000 /* System Clock Ratio */ -#define CFG_ECBY2 0x00000000 /* divide by 2 */ -#define CFG_ECBY3 0x10000000 /* divide by 3 */ -#define CFG_ECBY4 0x20000000 /* divide by 4 */ -#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */ -#define CFG_EPD 0x00000000 /* D */ -#define CFG_EPDDX 0x01000000 /* DDX */ -#define CFG_EPDDXX 0x02000000 /* DDXX */ -#define CFG_EPDXDX 0x03000000 /* DXDX */ -#define CFG_EPDDXXX 0x04000000 /* DDXXX */ -#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */ -#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */ -#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */ -#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */ -#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */ -#define CFG_SBSHIFT 22 -#define CFG_SB4 0x00000000 /* 4 words */ -#define CFG_SB8 0x00400000 /* 8 words */ -#define CFG_SB16 0x00800000 /* 16 words */ -#define CFG_SB32 0x00c00000 /* 32 words */ -#define CFG_SS 0x00200000 /* Split secondary cache */ -#define CFG_SW 0x00100000 /* Secondary cache port width */ -#define CFG_EWMASK 0x000c0000 /* System port width */ -#define CFG_EWSHIFT 18 -#define CFG_EW64 0x00000000 /* 64 bit */ -#define CFG_EW32 0x00010000 /* 32 bit */ -#define CFG_SC 0x00020000 /* Secondary cache absent */ -#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */ -#define CFG_BE 0x00008000 /* Big Endian */ -#define CFG_EM 0x00004000 /* ECC mode enable */ -#define CFG_EB 0x00002000 /* Block ordering */ -#define CFG_ICMASK 0x00000e00 /* Instruction cache size */ -#define CFG_ICSHIFT 9 -#define CFG_DCMASK 0x000001c0 /* Data cache size */ -#define CFG_DCSHIFT 6 -#define CFG_IB 0x00000020 /* Instruction cache block size */ -#define CFG_DB 0x00000010 /* Data cache block size */ -#define CFG_CU 0x00000008 /* Update on Store Conditional */ -#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ - -/* - * R4000 primary cache mode - */ -#define CFG_C_UNCACHED 2 -#define CFG_C_NONCOHERENT 3 -#define CFG_C_COHERENTXCL 4 -#define CFG_C_COHERENTXCLW 5 -#define CFG_C_COHERENTUPD 6 - -/* - * R4000 cache operations (should be in assembler...?) - */ -#define Index_Invalidate_I 0x0 /* 0 0 */ -#define Index_Writeback_Inv_D 0x1 /* 0 1 */ -#define Index_Invalidate_SI 0x2 /* 0 2 */ -#define Index_Writeback_Inv_SD 0x3 /* 0 3 */ -#define Index_Load_Tag_I 0x4 /* 1 0 */ -#define Index_Load_Tag_D 0x5 /* 1 1 */ -#define Index_Load_Tag_SI 0x6 /* 1 2 */ -#define Index_Load_Tag_SD 0x7 /* 1 3 */ -#define Index_Store_Tag_I 0x8 /* 2 0 */ -#define Index_Store_Tag_D 0x9 /* 2 1 */ -#define Index_Store_Tag_SI 0xA /* 2 2 */ -#define Index_Store_Tag_SD 0xB /* 2 3 */ -#define Create_Dirty_Exc_D 0xD /* 3 1 */ -#define Create_Dirty_Exc_SD 0xF /* 3 3 */ -#define Hit_Invalidate_I 0x10 /* 4 0 */ -#define Hit_Invalidate_D 0x11 /* 4 1 */ -#define Hit_Invalidate_SI 0x12 /* 4 2 */ -#define Hit_Invalidate_SD 0x13 /* 4 3 */ -#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ -#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */ -#define Fill_I 0x14 /* 5 0 */ -#define Hit_Writeback_D 0x19 /* 6 1 */ -#define Hit_Writeback_SD 0x1B /* 6 3 */ -#define Hit_Writeback_I 0x18 /* 6 0 */ -#define Hit_Set_Virtual_SI 0x1E /* 7 2 */ -#define Hit_Set_Virtual_SD 0x1F /* 7 3 */ - -#ifndef WAIT -#define WAIT .word 0x42000020 -#endif WAIT - -#ifndef wait -#define wait .word 0x42000020 -#endif wait - -#endif - -/* -** TLB resource defines -*/ -#if defined(CPU_R3000) -#define N_TLB_ENTRIES 64 -#define TLB_PGSIZE 0x1000 -#define RANDBASE 8 -#define TLBLO_PFNMASK 0xfffff000 -#define TLBLO_PFNSHIFT 12 -#define TLBLO_N 0x800 /* non-cacheable */ -#define TLBLO_D 0x400 /* writeable */ -#define TLBLO_V 0x200 /* valid bit */ -#define TLBLO_G 0x100 /* global access bit */ - -#define TLBHI_VPNMASK 0xfffff000 -#define TLBHI_VPNSHIFT 12 -#define TLBHI_PIDMASK 0xfc0 -#define TLBHI_PIDSHIFT 6 -#define TLBHI_NPID 64 - -#define TLBINX_PROBE 0x80000000 -#define TLBINX_INXMASK 0x00003f00 -#define TLBINX_INXSHIFT 8 - -#define TLBRAND_RANDMASK 0x00003f00 -#define TLBRAND_RANDSHIFT 8 - -#define TLBCTXT_BASEMASK 0xffe00000 -#define TLBCTXT_BASESHIFT 21 - -#define TLBCTXT_VPNMASK 0x001ffffc -#define TLBCTXT_VPNSHIFT 2 -#endif -#if defined(CPU_R4000) -#define N_TLB_ENTRIES 48 - -#define TLBHI_VPN2MASK 0xffffe000 -#define TLBHI_PIDMASK 0x000000ff -#define TLBHI_NPID 256 - -#define TLBLO_PFNMASK 0x3fffffc0 -#define TLBLO_PFNSHIFT 6 -#define TLBLO_D 0x00000004 /* writeable */ -#define TLBLO_V 0x00000002 /* valid bit */ -#define TLBLO_G 0x00000001 /* global access bit */ -#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */ -#define TLBLO_CSHIFT 3 - -#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT) -#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT) -#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT) -#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT) -#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT) - -#define TLBINX_PROBE 0x80000000 -#define TLBINX_INXMASK 0x0000003f - -#define TLBRAND_RANDMASK 0x0000003f - -#define TLBCTXT_BASEMASK 0xff800000 -#define TLBCTXT_BASESHIFT 23 - -#define TLBCTXT_VPN2MASK 0x007ffff0 -#define TLBCTXT_VPN2SHIFT 4 - -#define TLBPGMASK_MASK 0x01ffe000 -#endif - -#if defined(CPU_R3000) -#define SR_CUMASK 0xf0000000 /* coproc usable bits */ -#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ -#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ -#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ -#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ - -#define SR_BEV 0x00400000 /* use boot exception vectors */ - -/* Cache control bits */ -#define SR_TS 0x00200000 /* TLB shutdown */ -#define SR_PE 0x00100000 /* cache parity error */ -#define SR_CM 0x00080000 /* cache miss */ -#define SR_PZ 0x00040000 /* cache parity zero */ -#define SR_SWC 0x00020000 /* swap cache */ -#define SR_ISC 0x00010000 /* Isolate data cache */ - -/* -** status register interrupt masks and bits -*/ - -#define SR_IMASK 0x0000ff00 /* Interrupt mask */ -#define SR_IMASK8 0x00000000 /* mask level 8 */ -#define SR_IMASK7 0x00008000 /* mask level 7 */ -#define SR_IMASK6 0x0000c000 /* mask level 6 */ -#define SR_IMASK5 0x0000e000 /* mask level 5 */ -#define SR_IMASK4 0x0000f000 /* mask level 4 */ -#define SR_IMASK3 0x0000f800 /* mask level 3 */ -#define SR_IMASK2 0x0000fc00 /* mask level 2 */ -#define SR_IMASK1 0x0000fe00 /* mask level 1 */ -#define SR_IMASK0 0x0000ff00 /* mask level 0 */ - -#define SR_IMASKSHIFT 8 - -#define SR_IBIT8 0x00008000 /* bit level 8 */ -#define SR_IBIT7 0x00004000 /* bit level 7 */ -#define SR_IBIT6 0x00002000 /* bit level 6 */ -#define SR_IBIT5 0x00001000 /* bit level 5 */ -#define SR_IBIT4 0x00000800 /* bit level 4 */ -#define SR_IBIT3 0x00000400 /* bit level 3 */ -#define SR_IBIT2 0x00000200 /* bit level 2 */ -#define SR_IBIT1 0x00000100 /* bit level 1 */ - -#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */ -#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */ -#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */ -#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */ -#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */ -#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */ -#endif - -#if defined(CPU_R4000) -#define SR_CUMASK 0xf0000000 /* coproc usable bits */ -#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ -#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ -#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ -#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ - -#define SR_RP 0x08000000 /* Reduced power operation */ -#define SR_FR 0x04000000 /* Additional floating point registers */ -#define SR_RE 0x02000000 /* Reverse endian in user mode */ - -#define SR_BEV 0x00400000 /* Use boot exception vectors */ -#define SR_TS 0x00200000 /* TLB shutdown */ -#define SR_SR 0x00100000 /* Soft reset */ -#define SR_CH 0x00040000 /* Cache hit */ -#define SR_CE 0x00020000 /* Use cache ECC */ -#define SR_DE 0x00010000 /* Disable cache exceptions */ - -/* -** status register interrupt masks and bits -*/ - -#define SR_IMASK 0x0000ff00 /* Interrupt mask */ -#define SR_IMASK8 0x00000000 /* mask level 8 */ -#define SR_IMASK7 0x00008000 /* mask level 7 */ -#define SR_IMASK6 0x0000c000 /* mask level 6 */ -#define SR_IMASK5 0x0000e000 /* mask level 5 */ -#define SR_IMASK4 0x0000f000 /* mask level 4 */ -#define SR_IMASK3 0x0000f800 /* mask level 3 */ -#define SR_IMASK2 0x0000fc00 /* mask level 2 */ -#define SR_IMASK1 0x0000fe00 /* mask level 1 */ -#define SR_IMASK0 0x0000ff00 /* mask level 0 */ - -#define SR_IMASKSHIFT 8 - -#define SR_IBIT8 0x00008000 /* bit level 8 */ -#define SR_IBIT7 0x00004000 /* bit level 7 */ -#define SR_IBIT6 0x00002000 /* bit level 6 */ -#define SR_IBIT5 0x00001000 /* bit level 5 */ -#define SR_IBIT4 0x00000800 /* bit level 4 */ -#define SR_IBIT3 0x00000400 /* bit level 3 */ -#define SR_IBIT2 0x00000200 /* bit level 2 */ -#define SR_IBIT1 0x00000100 /* bit level 1 */ - -#define SR_KSMASK 0x00000018 /* Kernel mode mask */ -#define SR_KSUSER 0x00000010 /* User mode */ -#define SR_KSSUPER 0x00000008 /* Supervisor mode */ -#define SR_KSKERNEL 0x00000000 /* Kernel mode */ -#define SR_ERL 0x00000004 /* Error level */ -#define SR_EXL 0x00000002 /* Exception level */ -#define SR_IE 0x00000001 /* Interrupts enabled */ -#endif - - - -/* - * Cause Register - */ -#define CAUSE_BD 0x80000000 /* Branch delay slot */ -#define CAUSE_CEMASK 0x30000000 /* coprocessor error */ -#define CAUSE_CESHIFT 28 - - -#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */ -#define CAUSE_IPSHIFT 8 - -#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */ -#define CAUSE_EXCSHIFT 2 - -#ifndef XDS -/* -** Coprocessor 0 registers -*/ -#define C0_INX $0 /* tlb index */ -#define C0_RAND $1 /* tlb random */ -#if defined(CPU_R3000) -#define C0_TLBLO $2 /* tlb entry low */ -#endif -#if defined(CPU_R4000) -#define C0_TLBLO0 $2 /* tlb entry low 0 */ -#define C0_TLBLO1 $3 /* tlb entry low 1 */ -#endif - -#define C0_CTXT $4 /* tlb context */ - -#if defined(CPU_R4000) -#define C0_PAGEMASK $5 /* tlb page mask */ -#define C0_WIRED $6 /* number of wired tlb entries */ -#endif - -#define C0_BADVADDR $8 /* bad virtual address */ - -#if defined(CPU_R4000) -#define C0_COUNT $9 /* cycle count */ -#endif - -#define C0_TLBHI $10 /* tlb entry hi */ - -#if defined(CPU_R4000) -#define C0_COMPARE $11 /* cyccle count comparator */ -#endif - -#define C0_SR $12 /* status register */ -#define C0_CAUSE $13 /* exception cause */ -#define C0_EPC $14 /* exception pc */ -#define C0_PRID $15 /* revision identifier */ - -#if defined(CPU_R3000) -#define C0_CONFIG $3 /* configuration register R3081*/ -#endif - -#if defined(CPU_R4000) -#define C0_CONFIG $16 /* configuration register */ -#define C0_LLADDR $17 /* linked load address */ -#define C0_WATCHLO $18 /* watchpoint trap register */ -#define C0_WATCHHI $19 /* watchpoint trap register */ -#define C0_XCTXT $20 /* extended tlb context */ -#define C0_ECC $26 /* secondary cache ECC control */ -#define C0_CACHEERR $27 /* cache error status */ -#define C0_TAGLO $28 /* cache tag lo */ -#define C0_TAGHI $29 /* cache tag hi */ -#define C0_ERRPC $30 /* cache error pc */ -#endif - -#endif XDS - -#ifdef R4650 -#define IWATCH $18 -#define DWATCH $19 -#define IBASE $0 -#define IBOUND $1 -#define DBASE $2 -#define DBOUND $3 -#define CALG $17 -#endif - -#endif /* _IDTCPU_H__ */ - diff --git a/c/src/exec/score/cpu/mips/idtmon.h b/c/src/exec/score/cpu/mips/idtmon.h deleted file mode 100644 index b42211ed5c..0000000000 --- a/c/src/exec/score/cpu/mips/idtmon.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - - $Id$ -*/ - -/* -** idtmon.h - General header file for the IDT Prom Monitor -** -** Copyright 1989 Integrated Device Technology, Inc. -** All Rights Reserved. -** -** June 1989 - D.Cahoon -*/ -#ifndef __IDTMON_H__ -#define __IDTMON_H__ - -/* -** P_STACKSIZE is the size of the Prom Stack. -** the prom stack grows downward -*/ -#define P_STACKSIZE 0x2000 /* sets stack size to 8k */ - -/* -** M_BUSWIDTH -** Memory bus width (including bank interleaving) in bytes -** used when doing memory sizing to prevent bus capacitance -** reporting ghost memory locations -*/ -#if defined(CPU_R3000) -#define M_BUSWIDTH 8 /* 32bit memory bank interleaved */ -#endif -#if defined(CPU_R4000) -#define M_BUSWIDTH 16 /* 64 bit memory bank interleaved */ -#endif - -/* -** this is the default value for the number of bytes to add in calculating -** the checksums in the checksum command -*/ -#define CHK_SUM_CNT 0x20000 /* number of bytes to calc chksum for */ - -/* -** Monitor modes -*/ -#define MODE_MONITOR 5 /* IDT Prom Monitor is executing */ -#define MODE_USER 0xa /* USER is executing */ - -/* -** memory reference widths -*/ -#define SW_BYTE 1 -#define SW_HALFWORD 2 -#define SW_WORD 4 -#define SW_TRIBYTEL 12 -#define SW_TRIBYTER 20 - -#ifdef CPU_R4000 -/* -** definitions for select_cache call -*/ -#define DCACHE 0 -#define ICACHE 1 -#define SCACHE 2 - -#endif - -#if defined (CLANGUAGE) || defined(_LANGUAGE_C) -typedef struct { - unsigned int mem_size; - unsigned int icache_size; - unsigned int dcache_size; -#ifdef CPU_R4000 - unsigned int scache_size; -#endif - - } mem_config; - -#endif CLANGUAGE || defined(_LANGUAGE_C) - -/* -** general equates for diagnostics and boolean functions -*/ -#define PASS 0 -#define FAIL 1 - -#ifndef TRUE -#define TRUE 1 -#endif TRUE -#ifndef NULL -#define NULL 0 -#endif NULL - -#ifndef FALSE -#define FALSE 0 -#endif FALSE - - -/* -** portablility equates -*/ - -#ifndef BOOL -#define BOOL unsigned int -#endif BOOL - -#ifndef GLOBAL -#define GLOBAL /**/ -#endif GLOBAL - -#ifndef MLOCAL -#define MLOCAL static -#endif MLOCAL - - -#ifdef XDS -#define CONST const -#else -#define CONST -#endif XDS - -#define u_char unsigned char -#define u_short unsigned short -#define u_int unsigned int -/* -** assembly instructions for compatability between xds and mips -*/ -#ifndef XDS -#define sllv sll -#define srlv srl -#endif XDS -/* -** debugger macros for assembly language routines. Allows the -** programmer to set up the necessary stack frame info -** required by debuggers to do stack traces. -*/ - -#ifndef XDS -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl name; \ - .ent name; \ -name:; \ - .frame frm_reg,offset,ret_reg -#define ENDFRAME(name) \ - .end name -#else -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl _##name;\ -_##name: -#define ENDFRAME(name) -#endif XDS -#endif /* __IDTMON_H__ */ diff --git a/c/src/exec/score/cpu/mips/iregdef.h b/c/src/exec/score/cpu/mips/iregdef.h deleted file mode 100644 index f0953da852..0000000000 --- a/c/src/exec/score/cpu/mips/iregdef.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - -Based upon IDT provided code with the following release: - -This source code has been made available to you by IDT on an AS-IS -basis. Anyone receiving this source is licensed under IDT copyrights -to use it in any way he or she deems fit, including copying it, -modifying it, compiling it, and redistributing it either with or -without modifications. No license under IDT patents or patent -applications is to be implied by the copyright license. - -Any user of this software should understand that IDT cannot provide -technical support for this software and will not be responsible for -any consequences resulting from the use of this software. - -Any person who transfers this source code or any derivative work must -include the IDT copyright notice, this paragraph, and the preceeding -two paragraphs in the transferred software. - -COPYRIGHT IDT CORPORATION 1996 -LICENSED MATERIAL - PROGRAM PROPERTY OF IDT - - $Id$ -*/ - -/* -** iregdef.h - IDT R3000 register structure header file -** -** Copyright 1989 Integrated Device Technology, Inc -** All Rights Reserved -** -*/ -#ifndef __IREGDEF_H__ -#define __IREGDEF_H__ - -/* - * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves - * added Register definition for XContext reg. - * Look towards end of this file. - */ -/* -** register names -*/ -#define r0 $0 -#define r1 $1 -#define r2 $2 -#define r3 $3 -#define r4 $4 -#define r5 $5 -#define r6 $6 -#define r7 $7 -#define r8 $8 -#define r9 $9 -#define r10 $10 -#define r11 $11 -#define r12 $12 -#define r13 $13 - -#define r14 $14 -#define r15 $15 -#define r16 $16 -#define r17 $17 -#define r18 $18 -#define r19 $19 -#define r20 $20 -#define r21 $21 -#define r22 $22 -#define r23 $23 -#define r24 $24 -#define r25 $25 -#define r26 $26 -#define r27 $27 -#define r28 $28 -#define r29 $29 -#define r30 $30 -#define r31 $31 - -#define fp0 $f0 -#define fp1 $f1 -#define fp2 $f2 -#define fp3 $f3 -#define fp4 $f4 -#define fp5 $f5 -#define fp6 $f6 -#define fp7 $f7 -#define fp8 $f8 -#define fp9 $f9 -#define fp10 $f10 -#define fp11 $f11 -#define fp12 $f12 -#define fp13 $f13 -#define fp14 $f14 -#define fp15 $f15 -#define fp16 $f16 -#define fp17 $f17 -#define fp18 $f18 -#define fp19 $f19 -#define fp20 $f20 -#define fp21 $f21 -#define fp22 $f22 -#define fp23 $f23 -#define fp24 $f24 -#define fp25 $f25 -#define fp26 $f26 -#define fp27 $f27 -#define fp28 $f28 -#define fp29 $f29 -#define fp30 $f30 -#define fp31 $f31 - -#define fcr0 $0 -#define fcr30 $30 -#define fcr31 $31 - -#define zero $0 /* wired zero */ -#define AT $at /* assembler temp */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers a0-a3 */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved t0-t9 */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved s0-s8 */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 -#define t9 $25 -#define k0 $26 /* kernel usage */ -#define k1 $27 /* kernel usage */ -#define gp $28 /* sdata pointer */ -#define sp $29 /* stack pointer */ -#define s8 $30 /* yet another saved reg for the callee */ -#define fp $30 /* frame pointer - this is being phased out by MIPS */ -#define ra $31 /* return address */ - - -/* -** relative position of registers in save reg area -*/ -#define R_R0 0 -#define R_R1 1 -#define R_R2 2 -#define R_R3 3 -#define R_R4 4 -#define R_R5 5 -#define R_R6 6 -#define R_R7 7 -#define R_R8 8 -#define R_R9 9 -#define R_R10 10 -#define R_R11 11 -#define R_R12 12 -#define R_R13 13 -#define R_R14 14 -#define R_R15 15 -#define R_R16 16 -#define R_R17 17 -#define R_R18 18 -#define R_R19 19 -#define R_R20 20 -#define R_R21 21 -#define R_R22 22 -#define R_R23 23 -#define R_R24 24 -#define R_R25 25 -#define R_R26 26 -#define R_R27 27 -#define R_R28 28 -#define R_R29 29 -#define R_R30 30 -#define R_R31 31 -#define R_F0 32 -#define R_F1 33 -#define R_F2 34 -#define R_F3 35 -#define R_F4 36 -#define R_F5 37 -#define R_F6 38 -#define R_F7 39 -#define R_F8 40 -#define R_F9 41 -#define R_F10 42 -#define R_F11 43 -#define R_F12 44 -#define R_F13 45 -#define R_F14 46 -#define R_F15 47 -#define R_F16 48 -#define R_F17 49 -#define R_F18 50 -#define R_F19 51 -#define R_F20 52 -#define R_F21 53 -#define R_F22 54 -#define R_F23 55 -#define R_F24 56 -#define R_F25 57 -#define R_F26 58 -#define R_F27 59 -#define R_F28 60 -#define R_F29 61 -#define R_F30 62 -#define R_F31 63 -#define NCLIENTREGS 64 -#define R_EPC 64 -#define R_MDHI 65 -#define R_MDLO 66 -#define R_SR 67 -#define R_CAUSE 68 -#define R_TLBHI 69 -#if defined(CPU_R3000) -#define R_TLBLO 70 -#endif -#if defined(CPU_R4000) -#define R_TLBLO0 70 -#endif -#define R_BADVADDR 71 -#define R_INX 72 -#define R_RAND 73 -#define R_CTXT 74 -#define R_EXCTYPE 75 -#define R_MODE 76 -#define R_PRID 77 -#define R_FCSR 78 -#define R_FEIR 79 -#if defined(CPU_R3000) -#define NREGS 80 -#endif -#if defined(CPU_R4000) -#define R_TLBLO1 80 -#define R_PAGEMASK 81 -#define R_WIRED 82 -#define R_COUNT 83 -#define R_COMPARE 84 -#define R_CONFIG 85 -#define R_LLADDR 86 -#define R_WATCHLO 87 -#define R_WATCHHI 88 -#define R_ECC 89 -#define R_CACHEERR 90 -#define R_TAGLO 91 -#define R_TAGHI 92 -#define R_ERRPC 93 -#define R_XCTXT 94 /* Ketan added from SIM64bit */ - -#define NREGS 95 -#endif - -/* -** For those who like to think in terms of the compiler names for the regs -*/ -#define R_ZERO R_R0 -#define R_AT R_R1 -#define R_V0 R_R2 -#define R_V1 R_R3 -#define R_A0 R_R4 -#define R_A1 R_R5 -#define R_A2 R_R6 -#define R_A3 R_R7 -#define R_T0 R_R8 -#define R_T1 R_R9 -#define R_T2 R_R10 -#define R_T3 R_R11 -#define R_T4 R_R12 -#define R_T5 R_R13 -#define R_T6 R_R14 -#define R_T7 R_R15 -#define R_S0 R_R16 -#define R_S1 R_R17 -#define R_S2 R_R18 -#define R_S3 R_R19 -#define R_S4 R_R20 -#define R_S5 R_R21 -#define R_S6 R_R22 -#define R_S7 R_R23 -#define R_T8 R_R24 -#define R_T9 R_R25 -#define R_K0 R_R26 -#define R_K1 R_R27 -#define R_GP R_R28 -#define R_SP R_R29 -#define R_FP R_R30 -#define R_RA R_R31 - -/* Ketan added the following */ -#ifdef CPU_R3000 -#define sreg sw -#define lreg lw -#define rmfc0 mfc0 -#define rmtc0 mtc0 -#define R_SZ 4 -#endif CPU_R3000 - -#ifdef CPU_R4000 -#if __mips < 3 -#define sreg sw -#define lreg lw -#define rmfc0 mfc0 -#define rmtc0 mtc0 -#define R_SZ 4 -#else -#define sreg sd -#define lreg ld -#define rmfc0 dmfc0 -#define rmtc0 dmtc0 -#define R_SZ 8 -#endif -#endif CPU_R4000 -/* Ketan till here */ - -#endif /* __IREGDEF_H__ */ - diff --git a/c/src/exec/score/cpu/mips/rtems.c b/c/src/exec/score/cpu/mips/rtems.c deleted file mode 100644 index f7ef2c32ab..0000000000 --- a/c/src/exec/score/cpu/mips/rtems.c +++ /dev/null @@ -1,49 +0,0 @@ -/* rtems.c ===> rtems.S or rtems.s - * - * This file contains the single entry point code for - * the XXX implementation of RTEMS. - * - * NOTE: This is supposed to be a .S or .s file NOT a C file. - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * All rights assigned to U.S. Government, 1994. - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - */ - -#ifndef lint -static char _sccsid[] = "@(#)rtems.c 03/15/96 1.1\n"; -#endif - -/* - * This is supposed to be an assembly file. This means that system.h - * and cpu.h should not be included in a "real" rtems file. - */ - -#include <rtems/system.h> -#include <rtems/score/cpu.h> -/* #include "asm.h> */ - -/* - * RTEMS - * - * This routine jumps to the directive indicated in the - * CPU defined register. This routine is used when RTEMS is - * linked by itself and placed in ROM. This routine is the - * first address in the ROM space for RTEMS. The user "calls" - * this address with the directive arguments in the normal place. - * This routine then jumps indirectly to the correct directive - * preserving the arguments. The directive should not realize - * it has been "wrapped" in this way. The table "_Entry_points" - * is used to look up the directive. - */ - -void RTEMS() -{ -} - diff --git a/c/src/exec/score/cpu/powerpc/README b/c/src/exec/score/cpu/powerpc/README deleted file mode 100644 index fc0dd9c7d7..0000000000 --- a/c/src/exec/score/cpu/powerpc/README +++ /dev/null @@ -1,71 +0,0 @@ -# -# $Id$ -# - -There are various issues regarding this port: - - - -1) Legal - -This port is written by Andrew Bray <andy@i-cubed.co.uk>, and -is copyright 1995 i-cubed ltd. - - - -2) CPU support. - -This release fully supports the IBM PPC403GA and PPC403GB processors. - -It has only been tested on the PPC403GA (using software floating -point). - -With the gratefully acknowledged assistance of IBM and Blue Micro, -this release contains code to support the following processors - PPC601, PPC603, PPC603e, PPC604, and PPC602. - -The support for these processors is incomplete, especially that for -the PPC602 for which only sketchy data is currently available. - - - -3) Application Binary INterface - -In the context of RTEMS, the ABI is of interest for the following -aspects: - -a) Register usage. Which registers are used to provide static variable - linkage, stack pointer etc. - -b) Function calling convention. How parameters are passed, how function - variables should be invoked, how values are returned, etc. - -c) Stack frame layout. - -I am aware of a number of ABIs for the PowerPC: - -a) The PowerOpen ABI. This is the original Power ABI used on the RS/6000. - This is the only ABI supported by versions of GCC before 2.7.0. - -b) The SVR4 ABI. This is the ABI defined by SunSoft for the Solaris port - to the PowerPC. - -c) The Embedded ABI. This is an embedded ABI for PowerPC use, which has no - operating system interface defined. It is promoted by SunSoft, Motorola, - and Cygnus Support. Cygnus are porting the GNU toolchain to this ABI. - -d) GCC 2.7.0. This compiler is partway along the road to supporting the EABI, - but is currently halfway in between. - -This port was built and tested using the PowerOpen ABI, with the following -caveat: we used an ELF assembler and linker. So some attention may be required -on the assembler files to get them through a traditional (XCOFF) PowerOpen -assembler. - -This port contains support for the other ABIs, but this may prove to be incomplete -as it is untested. - -In the long term, the RTEMS PowerPC port should move to the EABI as its primary -or only port. This should wait on a true EABI version of GCC. - -Andrew Bray 4/December/1995 diff --git a/c/src/exec/score/cpu/powerpc/TODO b/c/src/exec/score/cpu/powerpc/TODO deleted file mode 100644 index 6e3e04e6ca..0000000000 --- a/c/src/exec/score/cpu/powerpc/TODO +++ /dev/null @@ -1,7 +0,0 @@ -# -# $Id$ -# - -Todo list: - -Maybe decode external interrupts like the HPPA does. diff --git a/c/src/exec/score/cpu/powerpc/cpu.c b/c/src/exec/score/cpu/powerpc/cpu.c deleted file mode 100644 index 77aacc2ed7..0000000000 --- a/c/src/exec/score/cpu/powerpc/cpu.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * PowerPC CPU Dependent Source - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/cpu.c: - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * All rights assigned to U.S. Government, 1994. - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> -#include <rtems/score/context.h> -#include <rtems/score/thread.h> - -/* - * These are for testing purposes. - */ -#undef Testing - -#ifdef Testing -static unsigned32 msr; -#ifdef ppc403 -static unsigned32 evpr; -static unsigned32 exier; -#endif -#endif - -/* - * ppc_interrupt_level_to_msr - * - * This routine converts a two bit interrupt level to an MSR bit map. - */ - -const unsigned32 _CPU_msrs[4] = - { PPC_MSR_0, PPC_MSR_1, PPC_MSR_2, PPC_MSR_3 }; - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - -static void ppc_spurious(int, CPU_Interrupt_frame *); - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - proc_ptr handler = (proc_ptr)ppc_spurious; - int i; -#if (PPC_ABI != PPC_ABI_POWEROPEN) - register unsigned32 r2; -#if (PPC_ABI != PPC_ABI_GCC27) - register unsigned32 r13; - - asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13))); - _CPU_IRQ_info.Default_r13 = r13; -#endif - - asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2))); - _CPU_IRQ_info.Default_r2 = r2; -#endif - - _CPU_IRQ_info.Nest_level = &_ISR_Nest_level; - _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level; - _CPU_IRQ_info.Vector_table = _ISR_Vector_table; -#if (PPC_ABI == PPC_ABI_POWEROPEN) - _CPU_IRQ_info.Dispatch_r2 = ((unsigned32 *)_Thread_Dispatch)[1]; -#endif - _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary; - _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing; - - i = (int)&_CPU_IRQ_info; - asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */ - - i = PPC_MSR_INITIAL & ~PPC_MSR_DISABLE_MASK; - asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */ - -#ifdef Testing - { - unsigned32 tmp; - - asm volatile ("mfmsr %0" : "=r" (tmp)); - msr = tmp; -#ifdef ppc403 - asm volatile ("mfspr %0, 0x3d6" : "=r" (tmp)); /* EVPR */ - evpr = tmp; - asm volatile ("mfdcr %0, 0x42" : "=r" (tmp)); /* EXIER */ - exier = tmp; - asm volatile ("mtspr 0x3d6, %0" :: "r" (0)); /* EVPR */ -#endif - } -#endif - - if ( cpu_table->spurious_handler ) - handler = (proc_ptr)cpu_table->spurious_handler; - - for (i = 0; i < PPC_INTERRUPT_MAX; i++) - _ISR_Vector_table[i] = handler; - - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * COMMENTS FROM Andrew Bray <andy@i-cubed.co.uk>: - * - * The PowerPC puts its interrupt enable status in the MSR register - * which also contains things like endianness control. To be more - * awkward, the layout varies from processor to processor. This - * is why I adopted a table approach in my interrupt handling. - * Thus the inverse process is slow, because it requires a table - * search. - * - * This could fail, and return 4 (an invalid level) if the MSR has been - * set to a value not in the table. This is also quite an expensive - * operation - I do hope its not too common. - * - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 level, msr; - - asm volatile("mfmsr %0" : "=r" ((msr))); - - msr &= PPC_MSR_DISABLE_MASK; - - for (level = 0; level < 4; level++) - if ((_CPU_msrs[level] & PPC_MSR_DISABLE_MASK) == msr) - break; - - return level; -} - -/* _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler : - _CPU_Table.spurious_handler ? - (ISR_Handler_entry)_CPU_Table.spurious_handler : - (ISR_Handler_entry)ppc_spurious; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) - _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56; -#else - _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8; -#endif -} - -/* Handle a spurious interrupt */ -static void ppc_spurious(int v, CPU_Interrupt_frame *i) -{ -#if 0 - printf("Spurious interrupt on vector %d from %08.8x\n", - v, i->pc); -#endif -#ifdef ppc403 - if (v == PPC_IRQ_EXTERNAL) - { - register int r = 0; - - asm volatile("mtdcr 0x42, %0" : "=r" ((r)) : "0" ((r))); /* EXIER */ - } - else if (v == PPC_IRQ_PIT) - { - register int r = 0x08000000; - - asm volatile("mtspr 0x3d8, %0" : "=r" ((r)) : "0" ((r))); /* TSR */ - } - else if (v == PPC_IRQ_FIT) - { - register int r = 0x04000000; - - asm volatile("mtspr 0x3d8, %0" : "=r" ((r)) : "0" ((r))); /* TSR */ - } -#endif -} - -void _CPU_Fatal_error(unsigned32 _error) -{ -#ifdef Testing - unsigned32 tmp; - - tmp = msr; - asm volatile ("mtmsr %0" :: "r" (tmp)); -#ifdef ppc403 - tmp = evpr; - asm volatile ("mtspr 0x3d6, %0" :: "r" (tmp)); /* EVPR */ - tmp = exier; - asm volatile ("mtdcr 0x42, %0" :: "r" (tmp)); /* EXIER */ -#endif -#endif - asm volatile ("mr 3, %0" : : "r" ((_error))); - asm volatile ("tweq 5,5"); - asm volatile ("li 0,0; mtmsr 0"); - while (1) ; -} diff --git a/c/src/exec/score/cpu/powerpc/cpu.h b/c/src/exec/score/cpu/powerpc/cpu.h deleted file mode 100644 index bb7b1fea49..0000000000 --- a/c/src/exec/score/cpu/powerpc/cpu.h +++ /dev/null @@ -1,1017 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the PowerPC - * processor. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/cpu.h: - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * All rights assigned to U.S. Government, 1994. - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/ppc.h> /* pick up machine definitions */ -#ifndef ASM -struct CPU_Interrupt_frame; - -#include <rtems/score/ppctypes.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -/* - * ACB: This is a lie, but it gets us a handle on a call to set up - * a variable derived from the top of the interrupt stack. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "PPC_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( PPC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ -/* - * ACB Note: This could make debugging tricky.. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (PPC_CACHE_ALIGNMENT))) - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ -/* - * ACB Note: Levels are: - * 0: All maskable interrupts enabled - * 1: Other critical exceptions enabled - * 2: Machine check enabled - * 3: All maskable IRQs disabled - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000003 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - unsigned32 gpr1; /* Stack pointer for all */ - unsigned32 gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */ - unsigned32 gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */ - unsigned32 gpr14; /* Non volatile for all */ - unsigned32 gpr15; /* Non volatile for all */ - unsigned32 gpr16; /* Non volatile for all */ - unsigned32 gpr17; /* Non volatile for all */ - unsigned32 gpr18; /* Non volatile for all */ - unsigned32 gpr19; /* Non volatile for all */ - unsigned32 gpr20; /* Non volatile for all */ - unsigned32 gpr21; /* Non volatile for all */ - unsigned32 gpr22; /* Non volatile for all */ - unsigned32 gpr23; /* Non volatile for all */ - unsigned32 gpr24; /* Non volatile for all */ - unsigned32 gpr25; /* Non volatile for all */ - unsigned32 gpr26; /* Non volatile for all */ - unsigned32 gpr27; /* Non volatile for all */ - unsigned32 gpr28; /* Non volatile for all */ - unsigned32 gpr29; /* Non volatile for all */ - unsigned32 gpr30; /* Non volatile for all */ - unsigned32 gpr31; /* Non volatile for all */ - unsigned32 cr; /* PART of the CR is non volatile for all */ - unsigned32 pc; /* Program counter/Link register */ - unsigned32 msr; /* Initial interrupt level */ -} Context_Control; - -typedef struct { - /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over - * procedure calls. However, this would mean that the interrupt - * frame had to hold f0-f13, and the fpscr. And as the majority - * of tasks will not have an FP context, we will save the whole - * context here. - */ -#if (PPC_HAS_DOUBLE == 1) - double f[32]; - double fpscr; -#else - float f[32]; - float fpscr; -#endif -} Context_Control_fp; - -typedef struct CPU_Interrupt_frame { - unsigned32 stacklink; /* Ensure this is a real frame (also reg1 save) */ -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) - unsigned32 dummy[13]; /* Used by callees: PowerOpen ABI */ -#else - unsigned32 dummy[1]; /* Used by callees: SVR4/EABI */ -#endif - /* This is what is left out of the primary contexts */ - unsigned32 gpr0; - unsigned32 gpr2; /* play safe */ - unsigned32 gpr3; - unsigned32 gpr4; - unsigned32 gpr5; - unsigned32 gpr6; - unsigned32 gpr7; - unsigned32 gpr8; - unsigned32 gpr9; - unsigned32 gpr10; - unsigned32 gpr11; - unsigned32 gpr12; - unsigned32 gpr13; /* Play safe */ - unsigned32 gpr28; /* For internal use by the IRQ handler */ - unsigned32 gpr29; /* For internal use by the IRQ handler */ - unsigned32 gpr30; /* For internal use by the IRQ handler */ - unsigned32 gpr31; /* For internal use by the IRQ handler */ - unsigned32 cr; /* Bits of this are volatile, so no-one may save */ - unsigned32 ctr; - unsigned32 xer; - unsigned32 lr; - unsigned32 pc; - unsigned32 msr; - unsigned32 pad[3]; -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the PowerPC processor specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - - unsigned32 clicks_per_usec; /* Timer clicks per microsecond */ - unsigned32 serial_per_sec; /* Serial clocks per second */ - boolean serial_external_clock; - boolean serial_xon_xoff; - boolean serial_cts_rts; - unsigned32 serial_rate; - unsigned32 timer_average_overhead; /* Average overhead of timer in ticks */ - unsigned32 timer_least_valid; /* Least valid number from timer */ - void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *); -} rtems_cpu_table; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -/* EXTERN Context_Control_fp _CPU_Null_fp_context; */ - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -/* EXTERN void (*_CPU_Thread_dispatch_pointer)(); */ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -SCORE_EXTERN struct { - unsigned32 *Nest_level; - unsigned32 *Disable_level; - void *Vector_table; - void *Stack; -#if (PPC_ABI == PPC_ABI_POWEROPEN) - unsigned32 Dispatch_r2; -#else - unsigned32 Default_r2; -#if (PPC_ABI != PPC_ABI_GCC27) - unsigned32 Default_r13; -#endif -#endif - boolean *Switch_necessary; - boolean *Signal; -} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * (Optional) # of bytes for libmisc/stackchk to check - * If not specifed, then it defaults to something reasonable - * for most architectures. - */ - -#define CPU_STACK_CHECK_SIZE (128) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS (PPC_INTERRUPT_MAX) -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*3) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) - -/* ISR handler macros */ - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define loc_string(a,b) a " (" #b ")\n" - -#define _CPU_ISR_Disable( _isr_cookie ) \ - { \ - asm volatile ( \ - "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \ - "=r" ((_isr_cookie)) : "r" ((PPC_MSR_DISABLE_MASK)) \ - ); \ - } - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - asm volatile ( "mtmsr %0" : \ - "=r" ((_isr_cookie)) : "0" ((_isr_cookie))); \ - } - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - { \ - asm volatile ( \ - "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \ - "=r" ((_isr_cookie)) : \ - "r" ((PPC_MSR_DISABLE_MASK)), "0" ((_isr_cookie)) \ - ); \ - } - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -#define _CPU_ISR_Set_level( new_level ) \ - { \ - register unsigned32 tmp; \ - asm volatile ( \ - "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" : \ - "=r" ((tmp)) : \ - "r" ((PPC_MSR_DISABLE_MASK)), "r" ((_CPU_msrs[new_level])), "0" ((tmp)) \ - ); \ - } - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - */ - -#if PPC_ABI == PPC_ABI_POWEROPEN -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - { \ - unsigned32 sp, *desc; \ - \ - sp = ((unsigned32)_stack_base) + (_size) - 56; \ - *((unsigned32 *)sp) = 0; \ - \ - desc = (unsigned32 *)_entry_point; \ - \ - (_the_context)->msr = PPC_MSR_INITIAL | \ - _CPU_msrs[ _isr ]; \ - (_the_context)->pc = desc[0]; \ - (_the_context)->gpr1 = sp; \ - (_the_context)->gpr2 = desc[1]; \ - } -#endif -#if PPC_ABI == PPC_ABI_SVR4 -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point ) \ - { \ - unsigned32 sp, r13; \ - \ - sp = ((unsigned32)_stack_base) + (_size) - 8; \ - *((unsigned32 *)sp) = 0; \ - \ - asm volatile ("mr %0, 13" : "=r" ((r13))); \ - \ - (_the_context->msr) = PPC_MSR_INITIAL | \ - _CPU_msrs[ _isr ]; \ - (_the_context->pc) = _entry_point; \ - (_the_context->gpr1) = sp; \ - (_the_context->gpr13) = r13; \ - } -#endif -#if PPC_ABI == PPC_ABI_EABI -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point ) \ - { \ - unsigned32 sp, r2, r13; \ - \ - sp = ((unsigned32)_stack_base) + (_size) - 8; \ - *((unsigned32 *)sp) = 0; \ - \ - asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); \ - \ - (_the_context)->msr = PPC_MSR_INITIAL | \ - _CPU_msrs[ _isr ]; \ - (_the_context->pc) = _entry_point; \ - (_the_context->gpr1) = sp; \ - (_the_context->gpr2) = r2; \ - (_the_context->gpr13) = r13; \ - } -#endif - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - _CPU_Fatal_error(_error) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_Bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ - "1" ((_value))); \ - } - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x80000000 >> (_bit_number) ) - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ - -/* variables */ - -extern const unsigned32 _CPU_msrs[4]; - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -void _CPU_Fatal_error( - unsigned32 _error -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 swapped; - - asm volatile("rlwimi %0,%1,8,24,31;" - "rlwimi %0,%1,24,16,23;" - "rlwimi %0,%1,8,8,15;" - "rlwimi %0,%1,24,0,7;" : - "=r" ((swapped)) : "r" ((value))); - - return( swapped ); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/powerpc/cpu_asm.s b/c/src/exec/score/cpu/powerpc/cpu_asm.s deleted file mode 100644 index cf95e25a5c..0000000000 --- a/c/src/exec/score/cpu/powerpc/cpu_asm.s +++ /dev/null @@ -1,749 +0,0 @@ - -/* cpu_asm.s 1.1 - 95/12/04 - * - * This file contains the assembly code for the PowerPC implementation - * of RTEMS. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/cpu_asm.c: - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * All rights assigned to U.S. Government, 1994. - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - */ - -#include "asm.h" - -/* - * Offsets for various Contexts - */ - .set GP_1, 0 - .set GP_2, (GP_1 + 4) - .set GP_13, (GP_2 + 4) - .set GP_14, (GP_13 + 4) - - .set GP_15, (GP_14 + 4) - .set GP_16, (GP_15 + 4) - .set GP_17, (GP_16 + 4) - .set GP_18, (GP_17 + 4) - - .set GP_19, (GP_18 + 4) - .set GP_20, (GP_19 + 4) - .set GP_21, (GP_20 + 4) - .set GP_22, (GP_21 + 4) - - .set GP_23, (GP_22 + 4) - .set GP_24, (GP_23 + 4) - .set GP_25, (GP_24 + 4) - .set GP_26, (GP_25 + 4) - - .set GP_27, (GP_26 + 4) - .set GP_28, (GP_27 + 4) - .set GP_29, (GP_28 + 4) - .set GP_30, (GP_29 + 4) - - .set GP_31, (GP_30 + 4) - .set GP_CR, (GP_31 + 4) - .set GP_PC, (GP_CR + 4) - .set GP_MSR, (GP_PC + 4) - -#if (PPC_HAS_DOUBLE == 1) - .set FP_0, 0 - .set FP_1, (FP_0 + 8) - .set FP_2, (FP_1 + 8) - .set FP_3, (FP_2 + 8) - .set FP_4, (FP_3 + 8) - .set FP_5, (FP_4 + 8) - .set FP_6, (FP_5 + 8) - .set FP_7, (FP_6 + 8) - .set FP_8, (FP_7 + 8) - .set FP_9, (FP_8 + 8) - .set FP_10, (FP_9 + 8) - .set FP_11, (FP_10 + 8) - .set FP_12, (FP_11 + 8) - .set FP_13, (FP_12 + 8) - .set FP_14, (FP_13 + 8) - .set FP_15, (FP_14 + 8) - .set FP_16, (FP_15 + 8) - .set FP_17, (FP_16 + 8) - .set FP_18, (FP_17 + 8) - .set FP_19, (FP_18 + 8) - .set FP_20, (FP_19 + 8) - .set FP_21, (FP_20 + 8) - .set FP_22, (FP_21 + 8) - .set FP_23, (FP_22 + 8) - .set FP_24, (FP_23 + 8) - .set FP_25, (FP_24 + 8) - .set FP_26, (FP_25 + 8) - .set FP_27, (FP_26 + 8) - .set FP_28, (FP_27 + 8) - .set FP_29, (FP_28 + 8) - .set FP_30, (FP_29 + 8) - .set FP_31, (FP_30 + 8) - .set FP_FPSCR, (FP_31 + 8) -#else - .set FP_0, 0 - .set FP_1, (FP_0 + 4) - .set FP_2, (FP_1 + 4) - .set FP_3, (FP_2 + 4) - .set FP_4, (FP_3 + 4) - .set FP_5, (FP_4 + 4) - .set FP_6, (FP_5 + 4) - .set FP_7, (FP_6 + 4) - .set FP_8, (FP_7 + 4) - .set FP_9, (FP_8 + 4) - .set FP_10, (FP_9 + 4) - .set FP_11, (FP_10 + 4) - .set FP_12, (FP_11 + 4) - .set FP_13, (FP_12 + 4) - .set FP_14, (FP_13 + 4) - .set FP_15, (FP_14 + 4) - .set FP_16, (FP_15 + 4) - .set FP_17, (FP_16 + 4) - .set FP_18, (FP_17 + 4) - .set FP_19, (FP_18 + 4) - .set FP_20, (FP_19 + 4) - .set FP_21, (FP_20 + 4) - .set FP_22, (FP_21 + 4) - .set FP_23, (FP_22 + 4) - .set FP_24, (FP_23 + 4) - .set FP_25, (FP_24 + 4) - .set FP_26, (FP_25 + 4) - .set FP_27, (FP_26 + 4) - .set FP_28, (FP_27 + 4) - .set FP_29, (FP_28 + 4) - .set FP_30, (FP_29 + 4) - .set FP_31, (FP_30 + 4) - .set FP_FPSCR, (FP_31 + 4) -#endif - - .set IP_LINK, 0 -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) - .set IP_0, (IP_LINK + 56) -#else - .set IP_0, (IP_LINK + 8) -#endif - .set IP_2, (IP_0 + 4) - - .set IP_3, (IP_2 + 4) - .set IP_4, (IP_3 + 4) - .set IP_5, (IP_4 + 4) - .set IP_6, (IP_5 + 4) - - .set IP_7, (IP_6 + 4) - .set IP_8, (IP_7 + 4) - .set IP_9, (IP_8 + 4) - .set IP_10, (IP_9 + 4) - - .set IP_11, (IP_10 + 4) - .set IP_12, (IP_11 + 4) - .set IP_13, (IP_12 + 4) - .set IP_28, (IP_13 + 4) - - .set IP_29, (IP_28 + 4) - .set IP_30, (IP_29 + 4) - .set IP_31, (IP_30 + 4) - .set IP_CR, (IP_31 + 4) - - .set IP_CTR, (IP_CR + 4) - .set IP_XER, (IP_CTR + 4) - .set IP_LR, (IP_XER + 4) - .set IP_PC, (IP_LR + 4) - - .set IP_MSR, (IP_PC + 4) - .set IP_END, (IP_MSR + 16) - - /* _CPU_IRQ_info offsets */ - /* These must be in this order */ - .set Nest_level, 0 - .set Disable_level, 4 - .set Vector_table, 8 - .set Stack, 12 -#if (PPC_ABI == PPC_ABI_POWEROPEN) - .set Dispatch_r2, 16 - .set Switch_necessary, 20 -#else - .set Default_r2, 16 -#if (PPC_ABI != PPC_ABI_GCC27) - .set Default_r13, 20 - .set Switch_necessary, 24 -#else - .set Switch_necessary, 20 -#endif -#endif - .set Signal, Switch_necessary + 4 - - BEGIN_CODE -/* - * _CPU_Context_save_fp_context - * - * This routine is responsible for saving the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - - ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) - PUBLIC_PROC (_CPU_Context_save_fp) -PROC (_CPU_Context_save_fp): -#if (PPC_HAS_FPU == 1) - lwz r3, 0(r3) -#if (PPC_HAS_DOUBLE == 1) - stfd f0, FP_0(r3) - stfd f1, FP_1(r3) - stfd f2, FP_2(r3) - stfd f3, FP_3(r3) - stfd f4, FP_4(r3) - stfd f5, FP_5(r3) - stfd f6, FP_6(r3) - stfd f7, FP_7(r3) - stfd f8, FP_8(r3) - stfd f9, FP_9(r3) - stfd f10, FP_10(r3) - stfd f11, FP_11(r3) - stfd f12, FP_12(r3) - stfd f13, FP_13(r3) - stfd f14, FP_14(r3) - stfd f15, FP_15(r3) - stfd f16, FP_16(r3) - stfd f17, FP_17(r3) - stfd f18, FP_18(r3) - stfd f19, FP_19(r3) - stfd f20, FP_20(r3) - stfd f21, FP_21(r3) - stfd f22, FP_22(r3) - stfd f23, FP_23(r3) - stfd f24, FP_24(r3) - stfd f25, FP_25(r3) - stfd f26, FP_26(r3) - stfd f27, FP_27(r3) - stfd f28, FP_28(r3) - stfd f29, FP_29(r3) - stfd f30, FP_30(r3) - stfd f31, FP_31(r3) - mffs f2 - stfd f2, FP_FPSCR(r3) -#else - stfs f0, FP_0(r3) - stfs f1, FP_1(r3) - stfs f2, FP_2(r3) - stfs f3, FP_3(r3) - stfs f4, FP_4(r3) - stfs f5, FP_5(r3) - stfs f6, FP_6(r3) - stfs f7, FP_7(r3) - stfs f8, FP_8(r3) - stfs f9, FP_9(r3) - stfs f10, FP_10(r3) - stfs f11, FP_11(r3) - stfs f12, FP_12(r3) - stfs f13, FP_13(r3) - stfs f14, FP_14(r3) - stfs f15, FP_15(r3) - stfs f16, FP_16(r3) - stfs f17, FP_17(r3) - stfs f18, FP_18(r3) - stfs f19, FP_19(r3) - stfs f20, FP_20(r3) - stfs f21, FP_21(r3) - stfs f22, FP_22(r3) - stfs f23, FP_23(r3) - stfs f24, FP_24(r3) - stfs f25, FP_25(r3) - stfs f26, FP_26(r3) - stfs f27, FP_27(r3) - stfs f28, FP_28(r3) - stfs f29, FP_29(r3) - stfs f30, FP_30(r3) - stfs f31, FP_31(r3) - mffs f2 - stfs f2, FP_FPSCR(r3) -#endif -#endif - blr - -/* - * _CPU_Context_restore_fp_context - * - * This routine is responsible for restoring the FP context - * at *fp_context_ptr. If the point to load the FP context - * from is changed then the pointer is modified by this routine. - * - * Sometimes a macro implementation of this is in cpu.h which dereferences - * the ** and a similarly named routine in this file is passed something - * like a (Context_Control_fp *). The general rule on making this decision - * is to avoid writing assembly language. - */ - - ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) - PUBLIC_PROC (_CPU_Context_restore_fp) -PROC (_CPU_Context_restore_fp): -#if (PPC_HAS_FPU == 1) - lwz r3, 0(r3) -#if (PPC_HAS_DOUBLE == 1) - lfd f2, FP_FPSCR(r3) - mtfsf 255, f2 - lfd f0, FP_0(r3) - lfd f1, FP_1(r3) - lfd f2, FP_2(r3) - lfd f3, FP_3(r3) - lfd f4, FP_4(r3) - lfd f5, FP_5(r3) - lfd f6, FP_6(r3) - lfd f7, FP_7(r3) - lfd f8, FP_8(r3) - lfd f9, FP_9(r3) - lfd f10, FP_10(r3) - lfd f11, FP_11(r3) - lfd f12, FP_12(r3) - lfd f13, FP_13(r3) - lfd f14, FP_14(r3) - lfd f15, FP_15(r3) - lfd f16, FP_16(r3) - lfd f17, FP_17(r3) - lfd f18, FP_18(r3) - lfd f19, FP_19(r3) - lfd f20, FP_20(r3) - lfd f21, FP_21(r3) - lfd f22, FP_22(r3) - lfd f23, FP_23(r3) - lfd f24, FP_24(r3) - lfd f25, FP_25(r3) - lfd f26, FP_26(r3) - lfd f27, FP_27(r3) - lfd f28, FP_28(r3) - lfd f29, FP_29(r3) - lfd f30, FP_30(r3) - lfd f31, FP_31(r3) -#else - lfs f2, FP_FPSCR(r3) - mtfsf 255, f2 - lfs f0, FP_0(r3) - lfs f1, FP_1(r3) - lfs f2, FP_2(r3) - lfs f3, FP_3(r3) - lfs f4, FP_4(r3) - lfs f5, FP_5(r3) - lfs f6, FP_6(r3) - lfs f7, FP_7(r3) - lfs f8, FP_8(r3) - lfs f9, FP_9(r3) - lfs f10, FP_10(r3) - lfs f11, FP_11(r3) - lfs f12, FP_12(r3) - lfs f13, FP_13(r3) - lfs f14, FP_14(r3) - lfs f15, FP_15(r3) - lfs f16, FP_16(r3) - lfs f17, FP_17(r3) - lfs f18, FP_18(r3) - lfs f19, FP_19(r3) - lfs f20, FP_20(r3) - lfs f21, FP_21(r3) - lfs f22, FP_22(r3) - lfs f23, FP_23(r3) - lfs f24, FP_24(r3) - lfs f25, FP_25(r3) - lfs f26, FP_26(r3) - lfs f27, FP_27(r3) - lfs f28, FP_28(r3) - lfs f29, FP_29(r3) - lfs f30, FP_30(r3) - lfs f31, FP_31(r3) -#endif -#endif - blr - - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - */ - ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) - PUBLIC_PROC (_CPU_Context_switch) -PROC (_CPU_Context_switch): - sync - isync -#if (PPC_CACHE_ALIGNMENT == 4) /* No cache */ - stw r1, GP_1(r3) - lwz r1, GP_1(r4) - stw r2, GP_2(r3) - lwz r2, GP_2(r4) -#if (PPC_USE_MULTIPLE == 1) - stmw r13, GP_13(r3) - lmw r13, GP_13(r4) -#else - stw r13, GP_13(r3) - lwz r13, GP_13(r4) - stw r14, GP_14(r3) - lwz r14, GP_14(r4) - stw r15, GP_15(r3) - lwz r15, GP_15(r4) - stw r16, GP_16(r3) - lwz r16, GP_16(r4) - stw r17, GP_17(r3) - lwz r17, GP_17(r4) - stw r18, GP_18(r3) - lwz r18, GP_18(r4) - stw r19, GP_19(r3) - lwz r19, GP_19(r4) - stw r20, GP_20(r3) - lwz r20, GP_20(r4) - stw r21, GP_21(r3) - lwz r21, GP_21(r4) - stw r22, GP_22(r3) - lwz r22, GP_22(r4) - stw r23, GP_23(r3) - lwz r23, GP_23(r4) - stw r24, GP_24(r3) - lwz r24, GP_24(r4) - stw r25, GP_25(r3) - lwz r25, GP_25(r4) - stw r26, GP_26(r3) - lwz r26, GP_26(r4) - stw r27, GP_27(r3) - lwz r27, GP_27(r4) - stw r28, GP_28(r3) - lwz r28, GP_28(r4) - stw r29, GP_29(r3) - lwz r29, GP_29(r4) - stw r30, GP_30(r3) - lwz r30, GP_30(r4) - stw r31, GP_31(r3) - lwz r31, GP_31(r4) -#endif - mfcr r5 - stw r5, GP_CR(r3) - lwz r5, GP_CR(r4) - mflr r6 - mtcrf 255, r5 - stw r6, GP_PC(r3) - lwz r6, GP_PC(r4) - mfmsr r7 - mtlr r6 - stw r7, GP_MSR(r3) - lwz r7, GP_MSR(r4) - mtmsr r7 -#endif -#if (PPC_CACHE_ALIGNMENT == 16) - /* This assumes that all the registers are in the given order */ - li r5, 16 - addi r3,r3,-4 - dcbz r5, r3 - stw r1, GP_1+4(r3) - stw r2, GP_2+4(r3) -#if (PPC_USE_MULTIPLE == 1) - addi r3, r3, GP_14+4 - dcbz r5, r3 - addi r3, r3, GP_18-GP_14 - dcbz r5, r3 - addi r3, r3, GP_22-GP_18 - dcbz r5, r3 - addi r3, r3, GP_26-GP_22 - dcbz r5, r3 - stmw r13, GP_13-GP_26(r3) -#else - stw r13, GP_13+4(r3) - stwu r14, GP_14+4(r3) - dcbz r5, r3 - stw r15, GP_15-GP_14(r3) - stw r16, GP_16-GP_14(r3) - stw r17, GP_17-GP_14(r3) - stwu r18, GP_18-GP_14(r3) - dcbz r5, r3 - stw r19, GP_19-GP_18(r3) - stw r20, GP_20-GP_18(r3) - stw r21, GP_21-GP_18(r3) - stwu r22, GP_22-GP_18(r3) - dcbz r5, r3 - stw r23, GP_23-GP_22(r3) - stw r24, GP_24-GP_22(r3) - stw r25, GP_25-GP_22(r3) - stwu r26, GP_26-GP_22(r3) - dcbz r5, r3 - stw r27, GP_27-GP_26(r3) - stw r28, GP_28-GP_26(r3) - stw r29, GP_29-GP_26(r3) - stw r30, GP_30-GP_26(r3) - stw r31, GP_31-GP_26(r3) -#endif - dcbt r0, r4 - mfcr r6 - stw r6, GP_CR-GP_26(r3) - mflr r7 - stw r7, GP_PC-GP_26(r3) - mfmsr r8 - stw r8, GP_MSR-GP_26(r3) - - dcbt r5, r4 - lwz r1, GP_1(r4) - lwz r2, GP_2(r4) -#if (PPC_USE_MULTIPLE == 1) - addi r4, r4, GP_15 - dcbt r5, r4 - addi r4, r4, GP_19-GP_15 - dcbt r5, r4 - addi r4, r4, GP_23-GP_19 - dcbt r5, r4 - addi r4, r4, GP_27-GP_23 - dcbt r5, r4 - lmw r13, GP_13-GP_27(r4) -#else - lwz r13, GP_13(r4) - lwz r14, GP_14(r4) - lwzu r15, GP_15(r4) - dcbt r5, r4 - lwz r16, GP_16-GP_15(r4) - lwz r17, GP_17-GP_15(r4) - lwz r18, GP_18-GP_15(r4) - lwzu r19, GP_19-GP_15(r4) - dcbt r5, r4 - lwz r20, GP_20-GP_19(r4) - lwz r21, GP_21-GP_19(r4) - lwz r22, GP_22-GP_19(r4) - lwzu r23, GP_23-GP_19(r4) - dcbt r5, r4 - lwz r24, GP_24-GP_23(r4) - lwz r25, GP_25-GP_23(r4) - lwz r26, GP_26-GP_23(r4) - lwzu r27, GP_27-GP_23(r4) - dcbt r5, r4 - lwz r28, GP_28-GP_27(r4) - lwz r29, GP_29-GP_27(r4) - lwz r30, GP_30-GP_27(r4) - lwz r31, GP_31-GP_27(r4) -#endif - lwz r6, GP_CR-GP_27(r4) - lwz r7, GP_PC-GP_27(r4) - lwz r8, GP_MSR-GP_27(r4) - mtcrf 255, r6 - mtlr r7 - mtmsr r8 -#endif -#if (PPC_CACHE_ALIGNMENT == 32) - /* This assumes that all the registers are in the given order */ - li r5, 32 - addi r3,r3,-4 - dcbz r5, r3 - stw r1, GP_1+4(r3) - stw r2, GP_2+4(r3) -#if (PPC_USE_MULTIPLE == 1) - addi r3, r3, GP_18+4 - dcbz r5, r3 - stmw r13, GP_13-GP_18(r3) -#else - stw r13, GP_13+4(r3) - stw r14, GP_14+4(r3) - stw r15, GP_15+4(r3) - stw r16, GP_16+4(r3) - stw r17, GP_17+4(r3) - stwu r18, GP_18+4(r3) - dcbz r5, r3 - stw r19, GP_19-GP_18(r3) - stw r20, GP_20-GP_18(r3) - stw r21, GP_21-GP_18(r3) - stw r22, GP_22-GP_18(r3) - stw r23, GP_23-GP_18(r3) - stw r24, GP_24-GP_18(r3) - stw r25, GP_25-GP_18(r3) - stw r26, GP_26-GP_18(r3) - stw r27, GP_27-GP_18(r3) - stw r28, GP_28-GP_18(r3) - stw r29, GP_29-GP_18(r3) - stw r30, GP_30-GP_18(r3) - stw r31, GP_31-GP_18(r3) -#endif - dcbt r0, r4 - mfcr r6 - stw r6, GP_CR-GP_18(r3) - mflr r7 - stw r7, GP_PC-GP_18(r3) - mfmsr r8 - stw r8, GP_MSR-GP_18(r3) - - dcbt r5, r4 - lwz r1, GP_1(r4) - lwz r2, GP_2(r4) -#if (PPC_USE_MULTIPLE == 1) - addi r4, r4, GP_19 - dcbt r5, r4 - lmw r13, GP_13-GP_19(r4) -#else - lwz r13, GP_13(r4) - lwz r14, GP_14(r4) - lwz r15, GP_15(r4) - lwz r16, GP_16(r4) - lwz r17, GP_17(r4) - lwz r18, GP_18(r4) - lwzu r19, GP_19(r4) - dcbt r5, r4 - lwz r20, GP_20-GP_19(r4) - lwz r21, GP_21-GP_19(r4) - lwz r22, GP_22-GP_19(r4) - lwz r23, GP_23-GP_19(r4) - lwz r24, GP_24-GP_19(r4) - lwz r25, GP_25-GP_19(r4) - lwz r26, GP_26-GP_19(r4) - lwz r27, GP_27-GP_19(r4) - lwz r28, GP_28-GP_19(r4) - lwz r29, GP_29-GP_19(r4) - lwz r30, GP_30-GP_19(r4) - lwz r31, GP_31-GP_19(r4) -#endif - lwz r6, GP_CR-GP_19(r4) - lwz r7, GP_PC-GP_19(r4) - lwz r8, GP_MSR-GP_19(r4) - mtcrf 255, r6 - mtlr r7 - mtmsr r8 -#endif - blr - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ -/* - * ACB: Don't worry about cache optimisation here - this is not THAT critical. - */ - ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) - PUBLIC_PROC (_CPU_Context_restore) -PROC (_CPU_Context_restore): - lwz r5, GP_CR(r3) - lwz r6, GP_PC(r3) - lwz r7, GP_MSR(r3) - mtcrf 255, r5 - mtlr r6 - mtmsr r7 - lwz r1, GP_1(r3) - lwz r2, GP_2(r3) -#if (PPC_USE_MULTIPLE == 1) - lmw r13, GP_13(r3) -#else - lwz r13, GP_13(r3) - lwz r14, GP_14(r3) - lwz r15, GP_15(r3) - lwz r16, GP_16(r3) - lwz r17, GP_17(r3) - lwz r18, GP_18(r3) - lwz r19, GP_19(r3) - lwz r20, GP_20(r3) - lwz r21, GP_21(r3) - lwz r22, GP_22(r3) - lwz r23, GP_23(r3) - lwz r24, GP_24(r3) - lwz r25, GP_25(r3) - lwz r26, GP_26(r3) - lwz r27, GP_27(r3) - lwz r28, GP_28(r3) - lwz r29, GP_29(r3) - lwz r30, GP_30(r3) - lwz r31, GP_31(r3) -#endif - - blr - -/* Individual interrupt prologues look like this: - * #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) - * #if (PPC_HAS_FPU) - * stwu r1, -(20*4 + 18*8 + IP_END)(r1) - * #else - * stwu r1, -(20*4 + IP_END)(r1) - * #endif - * #else - * stwu r1, -(IP_END)(r1) - * #endif - * stw r0, IP_0(r1) - * - * li r0, vectornum - * b PROC (_ISR_Handler{,C}) - */ - -/* void __ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * The vector number is in r0. R0 has already been stacked. - * - */ - ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) - PUBLIC_PROC (_ISR_Handler) -PROC (_ISR_Handler): -#define LABEL(x) x -#define MTSAVE(x) mtspr sprg0, x -#define MFSAVE(x) mfspr x, sprg0 -#define MTPC(x) mtspr srr0, x -#define MFPC(x) mfspr x, srr0 -#define MTMSR(x) mtspr srr1, x -#define MFMSR(x) mfspr x, srr1 - #include "irq_stub.s" - rfi - -#if (PPC_HAS_RFCI == 1) -/* void __ISR_HandlerC() - * - * This routine provides the RTEMS interrupt management. - * For critical interrupts - * - */ - ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) - PUBLIC_PROC (_ISR_HandlerC) -PROC (_ISR_HandlerC): -#undef LABEL -#undef MTSAVE -#undef MFSAVE -#undef MTPC -#undef MFPC -#undef MTMSR -#undef MFMSR -#define LABEL(x) x##_C -#define MTSAVE(x) mtspr sprg1, x -#define MFSAVE(x) mfspr x, sprg1 -#define MTPC(x) mtspr srr2, x -#define MFPC(x) mfspr x, srr2 -#define MTMSR(x) mtspr srr3, x -#define MFMSR(x) mfspr x, srr3 - #include "irq_stub.s" - rfci -#endif - -/* PowerOpen descriptors for indirect function calls. - */ - -#if (PPC_ABI == PPC_ABI_POWEROPEN) - DESCRIPTOR (_CPU_Context_save_fp) - DESCRIPTOR (_CPU_Context_restore_fp) - DESCRIPTOR (_CPU_Context_switch) - DESCRIPTOR (_CPU_Context_restore) - DESCRIPTOR (_ISR_Handler) -#if (PPC_HAS_RFCI == 1) - DESCRIPTOR (_ISR_HandlerC) -#endif -#endif diff --git a/c/src/exec/score/cpu/powerpc/irq_stub.s b/c/src/exec/score/cpu/powerpc/irq_stub.s deleted file mode 100644 index 42a63e991f..0000000000 --- a/c/src/exec/score/cpu/powerpc/irq_stub.s +++ /dev/null @@ -1,228 +0,0 @@ -/* irq_stub.s 1.1 - 95/12/04 - * - * This file contains the interrupt handler assembly code for the PowerPC - * implementation of RTEMS. It is #included from cpu_asm.s. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * $Id$ - */ - -/* void __ISR_Handler() - * - * This routine provides the RTEMS interrupt management. - * The vector number is in r0. R0 has already been stacked. - * - */ - /* Finish off the interrupt frame */ - stw r2, IP_2(r1) - stw r3, IP_3(r1) - stw r4, IP_4(r1) - stw r5, IP_5(r1) - stw r6, IP_6(r1) - stw r7, IP_7(r1) - stw r8, IP_8(r1) - stw r9, IP_9(r1) - stw r10, IP_10(r1) - stw r11, IP_11(r1) - stw r12, IP_12(r1) - stw r13, IP_13(r1) - stmw r28, IP_28(r1) - mfcr r5 - mfctr r6 - mfxer r7 - mflr r8 - MFPC (r9) - MFMSR (r10) - /* Establish addressing */ - mfspr r11, sprg3 - dcbt r0, r11 - stw r5, IP_CR(r1) - stw r6, IP_CTR(r1) - stw r7, IP_XER(r1) - stw r8, IP_LR(r1) - stw r9, IP_PC(r1) - stw r10, IP_MSR(r1) - - lwz r30, Vector_table(r11) - slwi r4,r0,2 - lwz r28, Nest_level(r11) - add r4, r4, r30 - - lwz r30, 0(r28) - mr r3, r0 - lwz r31, Stack(r11) - /* - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * if ( _ISR_Nest_level == 0 ) - * switch to software interrupt stack - * #endif - */ - /* Switch stacks, here we must prevent ALL interrupts */ - mfmsr r5 - mfspr r6, sprg2 - mtmsr r6 - cmpwi r30, 0 - lwz r29, Disable_level(r11) - subf r31,r1,r31 - bne LABEL (nested) - stwux r1,r1,r31 -LABEL (nested): - /* - * _ISR_Nest_level++; - */ - lwz r31, 0(r29) - addi r30,r30,1 - stw r30,0(r28) - /* From here on out, interrupts can be re-enabled. RTEMS - * convention says not. - */ - lwz r4,0(r4) - /* - * _Thread_Dispatch_disable_level++; - */ - addi r31,r31,1 - stw r31, 0(r29) - mtmsr r5 - /* - * (*_ISR_Vector_table[ vector ])( vector ); - */ -#if (PPC_ABI == PPC_ABI_POWEROPEN) - lwz r6,0(r4) - lwz r2,4(r4) - mtlr r6 - lwz r11,8(r4) -#endif -#if (PPC_ABI == PPC_ABI_GCC27) - lwz r2, Default_r2(r11) - mtlr r4 - lwz r2, 0(r2) -#endif -#if (PPC_ABI == PPC_ABI_SVR4 || PPC_ABI == PPC_ABI_EABI) - mtlr r4 - lwz r2, Default_r2(r11) - lwz r13, Default_r13(r11) - lwz r2, 0(r2) - lwz r13, 0(r13) -#endif - mr r4,r1 - blrl - /* NOP marker for debuggers */ - or r6,r6,r6 - - /* We must re-disable the interrupts */ - mfspr r11, sprg3 - mfspr r0, sprg2 - mtmsr r0 - lwz r30, 0(r28) - lwz r31, 0(r29) - - /* - * if (--Thread_Dispatch_disable,--_ISR_Nest_level) - * goto easy_exit; - */ - addi r30, r30, -1 - cmpwi r30, 0 - addi r31, r31, -1 - stw r30, 0(r28) - stw r31, 0(r29) - bne LABEL (easy_exit) - cmpwi r31, 0 - - lwz r30, Switch_necessary(r11) - - /* - * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) - * restore stack - * #endif - */ - lwz r1,0(r1) - bne LABEL (easy_exit) - lwz r30, 0(r30) - lwz r31, Signal(r11) - - /* - * if ( _Context_Switch_necessary ) - * goto switch - */ - cmpwi r30, 0 - lwz r28, 0(r31) - li r6,0 - bne LABEL (switch) - /* - * if ( !_ISR_Signals_to_thread_executing ) - * goto easy_exit - * _ISR_Signals_to_thread_executing = 0; - */ - cmpwi r28, 0 - beq LABEL (easy_exit) - - /* - * switch: - * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch - */ -LABEL (switch): - stw r6, 0(r31) - /* Re-enable interrupts */ - lwz r0, IP_MSR(r1) -#if (PPC_ABI == PPC_ABI_POWEROPEN) - lwz r2, Dispatch_r2(r11) -#else - /* R2 and R13 still hold their values from the last call */ -#endif - mtmsr r0 - bl SYM (_Thread_Dispatch) - /* NOP marker for debuggers */ - or r6,r6,r6 - /* - * prepare to get out of interrupt - */ - /* Re-disable IRQs */ - mfspr r0, sprg2 - mtmsr r0 - /* - * easy_exit: - * prepare to get out of interrupt - * return from interrupt - */ -LABEL (easy_exit): - lwz r5, IP_CR(r1) - lwz r6, IP_CTR(r1) - lwz r7, IP_XER(r1) - lwz r8, IP_LR(r1) - lwz r9, IP_PC(r1) - lwz r10, IP_MSR(r1) - mtcrf 255,r5 - mtctr r6 - mtxer r7 - mtlr r8 - MTPC (r9) - MTMSR (r10) - lwz r0, IP_0(r1) - lwz r2, IP_2(r1) - lwz r3, IP_3(r1) - lwz r4, IP_4(r1) - lwz r5, IP_5(r1) - lwz r6, IP_6(r1) - lwz r7, IP_7(r1) - lwz r8, IP_8(r1) - lwz r9, IP_9(r1) - lwz r10, IP_10(r1) - lwz r11, IP_11(r1) - lwz r12, IP_12(r1) - lwz r13, IP_13(r1) - lmw r28, IP_28(r1) - lwz r1, 0(r1) diff --git a/c/src/exec/score/cpu/powerpc/ppc.h b/c/src/exec/score/cpu/powerpc/ppc.h deleted file mode 100644 index c05760ed53..0000000000 --- a/c/src/exec/score/cpu/powerpc/ppc.h +++ /dev/null @@ -1,318 +0,0 @@ -/* ppc.h - * - * This file contains definitions for the IBM/Motorola PowerPC - * family members. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * - * Note: - * This file is included by both C and assembler code ( -DASM ) - * - * $Id$ - */ - -#ifndef _INCLUDE_PPC_h -#define _INCLUDE_PPC_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The following define the CPU Family and Model within the family - * - * NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced - * with the name of the appropriate macro for this target CPU. - */ - -#ifdef ppc -#undef ppc -#endif -#define ppc - -#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL -#undef REPLACE_THIS_WITH_THE_CPU_MODEL -#endif -#define REPLACE_THIS_WITH_THE_CPU_MODEL - -#ifdef REPLACE_THIS_WITH_THE_BSP -#undef REPLACE_THIS_WITH_THE_BSP -#endif -#define REPLACE_THIS_WITH_THE_BSP - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "no cpu" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#if defined(ppc403) - -#define CPU_MODEL_NAME "PowerPC 403" - -#define PPC_ALIGNMENT 4 -#define PPC_CACHE_ALIGNMENT 16 -#define PPC_CACHE_ALIGN_POWER 4 -#define PPC_INTERRUPT_MAX 16 -#define PPC_HAS_FPU 0 -#define PPC_HAS_DOUBLE 0 -#define PPC_HAS_RFCI 1 -#define PPC_MSR_DISABLE_MASK 0x00029200 -#define PPC_MSR_INITIAL 0x00000000 -#define PPC_INIT_FPSCR 0x00000000 -#define PPC_USE_MULTIPLE 1 -#define PPC_I_CACHE 2048 -#define PPC_D_CACHE 1024 - -#define PPC_MSR_0 0x00029200 -#define PPC_MSR_1 0x00021200 -#define PPC_MSR_2 0x00021000 -#define PPC_MSR_3 0x00000000 - -#elif defined(ppc601) - -#define CPU_MODEL_NAME "PowerPC 601" - -#define PPC_ALIGNMENT 8 -#define PPC_CACHE_ALIGNMENT 32 -#define PPC_CACHE_ALIGN_POWER 5 -#define PPC_INTERRUPT_MAX 16 -#define PPC_HAS_FPU 1 -#define PPC_HAS_DOUBLE 1 -#define PPC_HAS_RFCI 0 -#define PPC_MSR_DISABLE_MASK 0x00009900 -#define PPC_MSR_INITIAL 0x00002000 -#define PPC_INIT_FPSCR 0x000000f8 -#define PPC_USE_MULTIPLE 1 -#define PPC_I_CACHE 0 -#define PPC_D_CACHE 32768 - -#define PPC_MSR_0 0x00009900 -#define PPC_MSR_1 0x00001000 -#define PPC_MSR_2 0x00001000 -#define PPC_MSR_3 0x00000000 - -#elif defined(ppc602) - -#define CPU_MODEL_NAME "PowerPC 602" - -#define PPC_ALIGNMENT 4 -#define PPC_CACHE_ALIGNMENT 32 -#define PPC_CACHE_ALIGN_POWER 5 -#define PPC_INTERRUPT_MAX 16 -#define PPC_HAS_FPU 1 -#define PPC_HAS_DOUBLE 0 -#define PPC_HAS_RFCI 0 -#define PPC_MSR_DISABLE_MASK -#define PPC_MSR_INITIAL -#define PPC_INIT_FPSCR -#define PPC_USE_MULTIPLE 0 -#define PPC_I_CACHE 4096 -#define PPC_D_CACHE 4096 - -#elif defined(ppc603) - -#define CPU_MODEL_NAME "PowerPC 603" - -#define PPC_ALIGNMENT 8 -#define PPC_CACHE_ALIGNMENT 32 -#define PPC_CACHE_ALIGN_POWER 5 -#define PPC_INTERRUPT_MAX 16 -#define PPC_HAS_FPU 1 -#define PPC_HAS_DOUBLE 1 -#define PPC_HAS_RFCI 0 -#define PPC_MSR_DISABLE_MASK 0x00009900 -#define PPC_MSR_INITIAL 0x00002000 -#define PPC_INIT_FPSCR 0x000000f8 -#define PPC_USE_MULTIPLE 0 -#define PPC_I_CACHE 8192 -#define PPC_D_CACHE 8192 - -#define PPC_MSR_0 0x00009900 -#define PPC_MSR_1 0x00001000 -#define PPC_MSR_2 0x00001000 -#define PPC_MSR_3 0x00000000 - -#elif defined(ppc603e) - -#define CPU_MODEL_NAME "PowerPC 603e" - -#define PPC_ALIGNMENT 8 -#define PPC_CACHE_ALIGNMENT 32 -#define PPC_CACHE_ALIGN_POWER 5 -#define PPC_INTERRUPT_MAX 16 -#define PPC_HAS_FPU 1 -#define PPC_HAS_DOUBLE 1 -#define PPC_HAS_RFCI 0 -#define PPC_MSR_DISABLE_MASK 0x00009900 -#define PPC_MSR_INITIAL 0x00002000 -#define PPC_INIT_FPSCR 0x000000f8 -#define PPC_USE_MULTIPLE 0 -#define PPC_I_CACHE 16384 -#define PPC_D_CACHE 16384 - -#define PPC_MSR_0 0x00009900 -#define PPC_MSR_1 0x00001000 -#define PPC_MSR_2 0x00001000 -#define PPC_MSR_3 0x00000000 - -#elif defined(ppc604) - -#define CPU_MODEL_NAME "PowerPC 604" - -#define PPC_ALIGNMENT 8 -#define PPC_CACHE_ALIGNMENT 32 -#define PPC_CACHE_ALIGN_POWER 5 -#define PPC_INTERRUPT_MAX 16 -#define PPC_HAS_FPU 1 -#define PPC_HAS_DOUBLE 1 -#define PPC_HAS_RFCI 0 -#define PPC_MSR_DISABLE_MASK 0x00009900 -#define PPC_MSR_INITIAL 0x00002000 -#define PPC_INIT_FPSCR 0x000000f8 -#define PPC_USE_MULTIPLE 0 -#define PPC_I_CACHE 16384 -#define PPC_D_CACHE 16384 - -#define PPC_MSR_0 0x00009900 -#define PPC_MSR_1 0x00001000 -#define PPC_MSR_2 0x00001000 -#define PPC_MSR_3 0x00000000 - -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Application binary interfaces. - * PPC_ABI MUST be defined as one of these. - * Only PPC_ABI_POWEROPEN is currently fully supported. - * Only EABI will be supported in the end when - * the tools are there. - * Only big endian is currently supported. - */ -/* - * PowerOpen ABI. This is Andy's hack of the - * PowerOpen ABI to ELF. ELF rather than a - * XCOFF assembler is used. This may work - * if PPC_ASM == PPC_ASM_XCOFF is defined. - */ -#define PPC_ABI_POWEROPEN 0 -/* - * GCC 2.7.0 munched version of EABI, with - * PowerOpen calling convention and stack frames, - * but EABI style indirect function calls. - */ -#define PPC_ABI_GCC27 1 -/* - * SVR4 ABI - */ -#define PPC_ABI_SVR4 2 -/* - * Embedded ABI - */ -#define PPC_ABI_EABI 3 - -#if (PPC_ABI == PPC_ABI_POWEROPEN) -#define PPC_STACK_ALIGNMENT 8 -#elif (PPC_ABI == PPC_ABI_GCC27) -#define PPC_STACK_ALIGNMENT 8 -#elif (PPC_ABI == PPC_ABI_SVR4) -#define PPC_STACK_ALIGNMENT 16 -#elif (PPC_ABI == PPC_ABI_EABI) -#define PPC_STACK_ALIGNMENT 8 -#else -#error "PPC_ABI is not properly defined" -#endif -#ifndef PPC_ABI -#error "PPC_ABI is not properly defined" -#endif - -/* - * Assemblers. - * PPC_ASM MUST be defined as one of these. - * Only PPC_ABI_ELF is currently fully supported. - */ -/* - * ELF assembler. Currently used for all ABIs. - */ -#define PPC_ASM_ELF 0 -/* - * XCOFF assembler, may be needed for PowerOpen ABI. - */ -#define PPC_ASM_XCOFF 1 - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "PowerPC" - -/* - * Interrupt vectors. - */ -/* Machine check */ -#define PPC_IRQ_MCHECK 0 -/* Protection violation */ -#define PPC_IRQ_PROTECT 1 -/* External interrupt */ -#define PPC_IRQ_EXTERNAL 2 -/* Program exception */ -#define PPC_IRQ_PROGRAM 3 -/* System call */ -#define PPC_IRQ_SCALL 4 -/* Floating point unavailable */ -#define PPC_IRQ_NOFP 5 -/* Program interval timer */ -#define PPC_IRQ_PIT 6 -/* Fixed interval timer */ -#define PPC_IRQ_FIT 7 -/* Critical interrupt pin */ -#define PPC_IRQ_CRIT 8 -/* Watchdog timer */ -#define PPC_IRQ_WATCHDOG 9 -/* Debug exceptions */ -#define PPC_IRQ_DEBUG 10 - -/* - * The following exceptions are not maskable, and are not - * necessarily predictable, so cannot be offered to RTEMS: - * Alignment exception - handled by the CPU module - * Data exceptions. - * Instruction exceptions. - */ - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_PPC_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/powerpc/ppctypes.h b/c/src/exec/score/cpu/powerpc/ppctypes.h deleted file mode 100644 index 4bbb436bf8..0000000000 --- a/c/src/exec/score/cpu/powerpc/ppctypes.h +++ /dev/null @@ -1,74 +0,0 @@ -/* ppctypes.h - * - * This include file contains type definitions pertaining to the PowerPC - * processor family. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cputypes.h: - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * All rights assigned to U.S. Government, 1994. - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - */ - -#ifndef __PPC_TYPES_h -#define __PPC_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned32 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void ppc_isr; -typedef void ( *ppc_isr_entry )( int, struct CPU_Interrupt_frame * ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ diff --git a/c/src/exec/score/cpu/powerpc/rtems.s b/c/src/exec/score/cpu/powerpc/rtems.s deleted file mode 100644 index ae6022d24b..0000000000 --- a/c/src/exec/score/cpu/powerpc/rtems.s +++ /dev/null @@ -1,132 +0,0 @@ -/* rtems.s - * - * This file contains the single entry point code for - * the PowerPC implementation of RTEMS. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/rtems.c: - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * All rights assigned to U.S. Government, 1994. - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - */ - -#include "asm.h" - - BEGIN_CODE -/* - * RTEMS - * - * This routine jumps to the directive indicated in r11. - * This routine is used when RTEMS is linked by itself and placed - * in ROM. This routine is the first address in the ROM space for - * RTEMS. The user "calls" this address with the directive arguments - * in the normal place. - * This routine then jumps indirectly to the correct directive - * preserving the arguments. The directive should not realize - * it has been "wrapped" in this way. The table "_Entry_points" - * is used to look up the directive. - */ - - ALIGN (4, 2) - PUBLIC_PROC (RTEMS) -PROC (RTEMS): -#if (PPC_ABI == PPC_ABI_POWEROPEN) - mflr r0 - stw r0, 8(r1) - stwu r1, -64(r1) - - /* Establish addressing */ - bl base -base: - mflr r12 - addi r12, r12, tabaddr - base - - lwz r12, Entry_points-abase(r12) - slwi r11, r11, 2 - lwzx r12, r12, r11 - - stw r2, 56(r1) - lwz r0, 0(r12) - mtlr r0 - lwz r2, 4(r12) - lwz r11, 8(r12) - blrl - lwz r2, 56(r1) - addi r1, r1, 64 - lwz r0, 8(r1) - mtlr r0 -#else - mflr r0 - stw r0, 4(r1) - stwu r1, -16(r1) - - /* Establish addressing */ - bl base -base: - mflr r12 - addi r12, r12, tabaddr - base - - lwz r12, Entry_points-abase(r12) - slwi r11, r11, 2 - lwzx r11, r12, r11 - - stw r2, 8(r1) -#if (PPC_ABI != PPC_ABI_GCC27) - stw r13, 12(r1) -#endif - mtlr r11 - lwz r11, irqinfo-abase(r12) - lwz r2, 0(r11) -#if (PPC_ABI != PPC_ABI_GCC27) - lwz r13, 4(r11) -#endif - blrl - lwz r2, 8(r1) -#if (PPC_ABI != PPC_ABI_GCC27) - lwz r13, 12(r1) -#endif - addi r1, r1, 16 - lwz r0, 4(r1) - mtlr r0 -#endif - blr - - - /* Addressability stuff */ -tabaddr: -abase: - EXTERN_VAR (_Entry_points) -Entry_points: - EXT_SYM_REF (_Entry_points) -#if (PPC_ABI != PPC_ABI_POWEROPEN) - EXTERN_VAR (_CPU_IRQ_info) -irqinfo: - EXT_SYM_REF (_CPU_IRQ_info) -#endif - -#if (PPC_ABI == PPC_ABI_POWEROPEN) - DESCRIPTOR (RTEMS) -#endif - - |