diff options
Diffstat (limited to 'c/src/exec/score/cpu/unix')
| -rw-r--r-- | c/src/exec/score/cpu/unix/cpu.c | 529 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/unix/cpu.h | 929 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/unix/unix.h | 90 |
3 files changed, 0 insertions, 1548 deletions
diff --git a/c/src/exec/score/cpu/unix/cpu.c b/c/src/exec/score/cpu/unix/cpu.c deleted file mode 100644 index ed94953d58..0000000000 --- a/c/src/exec/score/cpu/unix/cpu.c +++ /dev/null @@ -1,529 +0,0 @@ -/* - * HP PA-RISC CPU Dependent Source - * - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Division Incorporated not be - * used in advertising or publicity pertaining to distribution - * of the software without specific, written prior permission. - * Division Incorporated makes no representations about the - * suitability of this software for any purpose. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/fatal.h> -#include <rtems/isr.h> -#include <rtems/wkspace.h> -/* - * In order to get the types and prototypes used in this file under - * Solaris 2.3, it is necessary to pull the following magic. - */ - -#if defined(solaris) -#warning "Ignore the undefining __STDC__ warning" -#undef __STDC__ -#define __STDC__ 0 -#undef _POSIX_C_SOURCE -#endif - -#include <stdio.h> -#include <stdlib.h> -#include <unistd.h> -#include <string.h> -#include <signal.h> -#include <time.h> - -extern void set_vector(proc_ptr, int, int); -extern void _Thread_Dispatch(void); - -extern unsigned32 _Thread_Dispatch_disable_level; -extern unsigned32 _SYSTEM_ID; -extern boolean _Context_Switch_necessary; - - -rtems_status_code signal_initialize(void); -void Stray_signal(int); -void signal_enable(unsigned32); -void signal_disable(unsigned32); -void interrupt_handler(); - -sigset_t UNIX_SIGNAL_MASK; -jmp_buf default_context; - -/* - * Which cpu are we? Used by libcpu and libbsp. - */ - -int cpu_number; - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of disptaching routine - */ - - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - unsigned32 i; - - if ( cpu_table == NULL ) - rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED ); - - /* - * The thread_dispatch argument is the address of the entry point - * for the routine called at the end of an ISR once it has been - * decided a context switch is necessary. On some compilation - * systems it is difficult to call a high-level language routine - * from assembly. This allows us to trick these systems. - * - * If you encounter this problem save the entry point in a CPU - * dependent variable. - */ - - _CPU_Thread_dispatch_pointer = thread_dispatch; - - /* - * XXX; If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* XXX: FP context initialization support */ - - _CPU_Table = *cpu_table; - -#if defined(hppa1_1) && defined(RTEMS_UNIXLIB) - /* - * HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp - * will handle the full 32 floating point registers. - * - * NOTE: Is this a bug in HPUX9? - */ - - _SYSTEM_ID = 0x20c; -#endif - - /* - * get default values to use in _CPU_Context_Initialize() - */ - - setjmp(default_context); - - /* - * Block all the signals except SIGTRAP for the debugger - * and SIGABRT for fatal errors. - */ - - _CPU_ISR_Set_signal_level(1); - - sigfillset(&UNIX_SIGNAL_MASK); - sigdelset(&UNIX_SIGNAL_MASK, SIGTRAP); - sigdelset(&UNIX_SIGNAL_MASK, SIGABRT); - sigdelset(&UNIX_SIGNAL_MASK, SIGIOT); - sigdelset(&UNIX_SIGNAL_MASK, SIGCONT); - - sigprocmask(SIG_BLOCK, &UNIX_SIGNAL_MASK, 0); - - /* - * Set the handler for all signals to be signal_handler - * which will then vector out to the correct handler - * for whichever signal actually happened. Initially - * set the vectors to the stray signal handler. - */ - - for (i = 0; i < 32; i++) - (void)set_vector(Stray_signal, i, 1); - - signal_initialize(); -} - -/* _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - */ - - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -} - -/*PAGE - * - * _CPU_Internal_threads_Idle_thread_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -void _CPU_Internal_threads_Idle_thread_body( void ) -{ - while (1) - pause(); -} - -void _CPU_Context_Initialize( - Context_Control *_the_context, - unsigned32 *_stack_base, - unsigned32 _size, - unsigned32 _new_level, - proc_ptr *_entry_point -) -{ - unsigned32 *addr; - unsigned32 jmp_addr; - unsigned32 _stack; - unsigned32 _the_size; - - jmp_addr = (unsigned32) _entry_point; - - _stack = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT); - _stack &= ~(CPU_STACK_ALIGNMENT - 1); - - _the_size = _size & ~(CPU_STACK_ALIGNMENT - 1); - - /* - * Slam our jmp_buf template into the context we are creating - */ - - memcpy(_the_context, default_context, sizeof(jmp_buf)); - - addr = (unsigned32 *)_the_context; - -#if defined(hppa1_1) - *(addr + RP_OFF) = jmp_addr; - *(addr + SP_OFF) = (unsigned32)(_stack + CPU_FRAME_SIZE); - - /* - * See if we are using shared libraries by checking - * bit 30 in 24 off of newp. If bit 30 is set then - * we are using shared libraries and the jump address - * is at what 24 off of newp points to so shove that - * into 24 off of newp instead. - */ - - if (jmp_addr & 0x40000000) { - jmp_addr &= 0xfffffffc; - *(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr; - } -#elif defined(sparc) - - /* - * See /usr/include/sys/stack.h in Solaris 2.3 for a nice - * diagram of the stack. - */ - - asm ("ta 0x03"); /* flush registers */ - - *(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET; - *(addr + SP_OFF) = (unsigned32)(_stack +_the_size - CPU_FRAME_SIZE); - *(addr + FP_OFF) = (unsigned32)(_stack +_the_size); -#else -#error "UNKNOWN CPU!!!" -#endif - - if (_new_level) - _CPU_ISR_Set_signal_level(1); - else - _CPU_ISR_Set_signal_level(0); - -} - -void _CPU_Context_restore( - Context_Control *next -) -{ - longjmp(next->regs, 0); -} - -void _CPU_Context_switch( - Context_Control *current, - Context_Control *next -) -{ - /* - * Save the current context - */ - - if (setjmp(current->regs) == 0) { - - /* - * Switch to the new context - */ - - longjmp(next->regs, 0); - } -} - -void _CPU_Save_float_context( - Context_Control_fp *fp_context -) -{ -} - -void _CPU_Restore_float_context( - Context_Control_fp *fp_context -) -{ -} - -void _CPU_ISR_Set_signal_level(unsigned32 level) -{ - if (level) - _CPU_Disable_signal(); - else - _CPU_Enable_signal(0); -} - - -unsigned32 _CPU_Disable_signal(void) -{ - sigset_t old_mask; - sigset_t empty_mask; - - sigemptyset(&empty_mask); - sigemptyset(&old_mask); - sigprocmask(SIG_BLOCK, &UNIX_SIGNAL_MASK, &old_mask); - - if (memcmp((char *)&empty_mask, (char *)&old_mask, sizeof(sigset_t)) != 0) - return 1; - - return 0; -} - - -void _CPU_Enable_signal(unsigned32 level) -{ - if (level == 0) - sigprocmask(SIG_UNBLOCK, &UNIX_SIGNAL_MASK, 0); -} - - -/* - * Support for external and spurious interrupts on HPPA - * - * TODO: - * delete interrupt.c etc. - * Count interrupts - * make sure interrupts disabled properly - * should handler check again for more interrupts before exit? - * How to enable interrupts from an interrupt handler? - * Make sure there is an entry for everything in ISR_Vector_Table - */ - -/* - * Init the external interrupt scheme - * called by bsp_start() - */ - -rtems_status_code -signal_initialize(void) -{ - struct sigaction act; - sigset_t mask; - - /* mark them all active except for TraceTrap and Abort */ - - sigfillset(&mask); - sigdelset(&mask, SIGTRAP); - sigdelset(&mask, SIGABRT); - sigdelset(&mask, SIGIOT); - sigdelset(&mask, SIGCONT); - sigprocmask(SIG_UNBLOCK, &mask, 0); - - act.sa_handler = interrupt_handler; - act.sa_mask = mask; -#if defined(solaris) - act.sa_flags = SA_RESTART; -#else - act.sa_flags = 0; -#endif - - sigaction(SIGHUP, &act, 0); - sigaction(SIGINT, &act, 0); - sigaction(SIGQUIT, &act, 0); - sigaction(SIGILL, &act, 0); - sigaction(SIGEMT, &act, 0); - sigaction(SIGFPE, &act, 0); - sigaction(SIGKILL, &act, 0); - sigaction(SIGBUS, &act, 0); - sigaction(SIGSEGV, &act, 0); - sigaction(SIGSYS, &act, 0); - sigaction(SIGPIPE, &act, 0); - sigaction(SIGALRM, &act, 0); - sigaction(SIGTERM, &act, 0); - sigaction(SIGUSR1, &act, 0); - sigaction(SIGUSR2, &act, 0); - sigaction(SIGCHLD, &act, 0); - sigaction(SIGCLD, &act, 0); - sigaction(SIGPWR, &act, 0); - sigaction(SIGVTALRM, &act, 0); - sigaction(SIGPROF, &act, 0); - sigaction(SIGIO, &act, 0); - sigaction(SIGWINCH, &act, 0); - sigaction(SIGSTOP, &act, 0); - sigaction(SIGTTIN, &act, 0); - sigaction(SIGTTOU, &act, 0); - sigaction(SIGURG, &act, 0); -/* - * XXX: Really should be on HPUX. - */ - -#if defined(hppa1_1) - sigaction(SIGLOST, &act, 0); -#endif - - return RTEMS_SUCCESSFUL; -} - - -/* - * External interrupt handler. - * This is installed as cpu interrupt handler. - * It vectors out to specific external interrupt handlers. - */ - -void -interrupt_handler(int vector) -{ - if (_ISR_Nest_level++ == 0) { - /* switch to interrupt stack */ - } - - _Thread_Dispatch_disable_level++; - - if (_ISR_Vector_table[vector]) { - _ISR_Vector_table[vector](vector); - } - else { - Stray_signal(vector); - } - - if (_ISR_Nest_level-- == 0) { - /* switch back to original stack */ - } - - _Thread_Dispatch_disable_level--; - - if (_Thread_Dispatch_disable_level == 0 && - (_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) { - _CPU_Enable_signal(0); - _Thread_Dispatch(); - } -} - - -void -Stray_signal(int sig_num) -{ - char buffer[ 80 ]; - - /* - * We avoid using the stdio section of the library. - * The following is generally safe. - */ - - write( - 2, - buffer, - sprintf( buffer, "Stray signal %d\n", sig_num ) - ); - - /* - * If it was a "fatal" signal, then exit here - * If app code has installed a hander for one of these, then - * we won't call Stray_signal, so this is ok. - */ - - switch (sig_num) - { - case SIGINT: - case SIGHUP: - case SIGQUIT: - case SIGILL: - case SIGEMT: - case SIGKILL: - case SIGBUS: - case SIGSEGV: - case SIGTERM: - _CPU_Fatal_error(0x100 + sig_num); - } -} - - -void -_CPU_Fatal_error(unsigned32 error) -{ - setitimer(ITIMER_REAL, 0, 0); - - _exit(error); -} - -int -_CPU_ffs(unsigned32 value) -{ - int output; - - output = ffs(value); - output = output - 1; - - return(output); -} diff --git a/c/src/exec/score/cpu/unix/cpu.h b/c/src/exec/score/cpu/unix/cpu.h deleted file mode 100644 index e6b29bcd74..0000000000 --- a/c/src/exec/score/cpu/unix/cpu.h +++ /dev/null @@ -1,929 +0,0 @@ -/* cpu.h - * - * This include file contains information pertaining to the HP - * PA-RISC processor (Level 1.1). - * - * COPYRIGHT (c) 1994 by Division Incorporated - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Division Incorporated not be - * used in advertising or publicity pertaining to distribution - * of the software without specific, written prior permission. - * Division Incorporated makes no representations about the - * suitability of this software for any purpose. - * - * $Id$ - */ - -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <setjmp.h> -#include <string.h> -#include <unix.h> - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#define CPU_HARDWARE_FP TRUE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#if defined(hppa1_1) -#define CPU_STACK_GROWS_UP TRUE -#elif defined(sparc) -#define CPU_STACK_GROWS_UP FALSE -#else -#error "unknown CPU!!" -#endif - - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_NAME "UNIX" - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -#if defined(hppa1_1) -/* - * Word indices within a jmp_buf structure - */ - -#ifdef RTEMS_NEWLIB -#define RP_OFF 6 -#define SP_OFF 2 -#define R3_OFF 10 -#define R4_OFF 11 -#define R5_OFF 12 -#define R6_OFF 13 -#define R7_OFF 14 -#define R8_OFF 15 -#define R9_OFF 16 -#define R10_OFF 17 -#define R11_OFF 18 -#define R12_OFF 19 -#define R13_OFF 20 -#define R14_OFF 21 -#define R15_OFF 22 -#define R16_OFF 23 -#define R17_OFF 24 -#define R18_OFF 25 -#define DP_OFF 26 -#endif - -#ifdef RTEMS_UNIXLIB -#define RP_OFF 0 -#define SP_OFF 1 -#define R3_OFF 4 -#define R4_OFF 5 -#define R5_OFF 6 -#define R6_OFF 7 -#define R7_OFF 8 -#define R8_OFF 9 -#define R9_OFF 10 -#define R10_OFF 11 -#define R11_OFF 12 -#define R12_OFF 13 -#define R13_OFF 14 -#define R14_OFF 15 -#define R15_OFF 16 -#define R16_OFF 17 -#define R17_OFF 18 -#define R18_OFF 19 -#define DP_OFF 20 -#endif -#endif - -#if defined(sparc) - -/* - * Word indices within a jmp_buf structure - */ - -#ifdef RTEMS_NEWLIB -#define ADDR_ADJ_OFFSET -8 -#define SP_OFF 0 -#define RP_OFF 1 -#define FP_OFF 2 -#endif - -#ifdef RTEMS_UNIXLIB -#define ADDR_ADJ_OFFSET 0 -#define G0_OFF 0 -#define SP_OFF 1 -#define RP_OFF 2 -#define FP_OFF 3 -#define I7_OFF 4 -#endif - -#endif - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - jmp_buf regs; -} Context_Control; - -typedef struct { -} Context_Control_fp; - -typedef struct { -} CPU_Interrupt_frame; - - -/* - * The following table contains the information required to configure - * the XXX processor specific parameters. - * - * NOTE: The interrupt_stack_size field is required if - * CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE. - * - * The pretasking_hook, predriver_hook, and postdriver_hook, - * and the do_zero_of_workspace fields are required on ALL CPUs. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 interrupt_stack_size; - unsigned32 extra_system_initialization_stack; -} rtems_cpu_table; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -EXTERN void *_CPU_Interrupt_stack_low; -EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * The size of a frame on the stack - */ - -#if defined(hppa1_1) -#define CPU_FRAME_SIZE (32 * 4) -#elif defined(sparc) -#define CPU_FRAME_SIZE (112) /* based on disassembled test code */ -#else -#error "Unknown CPU!!!" -#endif - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - */ - -#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (16 * 1024) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT 64 - -/* ISR handler macros */ - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level ) \ - do { \ - (_level) = _CPU_Disable_signal(); \ - } while ( 0 ) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - do { \ - _CPU_Enable_signal( (_level) ); \ - } while ( 0 ) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level ) \ - do { \ - register _ignored = 0; \ - _CPU_ISR_Enable( (_level) ); \ - _CPU_ISR_Disable( _ignored ); \ - } while ( 0 ) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -#define _CPU_ISR_Set_level( new_level ) \ - { \ - if ( new_level ) \ - (void) _CPU_Disable_signal(); \ - else \ - _CPU_Enable_signal( 0 ); \ - } - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) (_base) + (_offset) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } - -#define _CPU_Context_save_fp( _fp_context ) \ - _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context)) - -#define _CPU_Context_restore_fp( _fp_context ) \ - _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context)) - -extern void _CPU_Context_Initialize( - Context_Control *_the_context, - unsigned32 *_stack_base, - unsigned32 _size, - unsigned32 _new_level, - proc_ptr *_entry_point -); - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - _CPU_Fatal_error( _error ) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_Bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - _output = _CPU_ffs( _value ) - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#define _CPU_Priority_Bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void _CPU_Internal_threads_Idle_thread_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Save_float_context - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Save_float_context( - Context_Control_fp *fp_context_ptr -); - -/* - * _CPU_Restore_float_context - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Restore_float_context( - Context_Control_fp *fp_context_ptr -); - - -void _CPU_ISR_Set_signal_level( - unsigned32 level -); - -unsigned32 _CPU_Disable_signal( void ); - -void _CPU_Enable_signal( - unsigned32 level -); - -void _CPU_Fatal_error( - unsigned32 _error -); - -int _CPU_ffs( - unsigned32 _value -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/unix/unix.h b/c/src/exec/score/cpu/unix/unix.h deleted file mode 100644 index 823bbcfb34..0000000000 --- a/c/src/exec/score/cpu/unix/unix.h +++ /dev/null @@ -1,90 +0,0 @@ -/* unix.h - * - * This include file contains the basic type definitions required by RTEMS - * which are typical for a modern UNIX computer using GCC. - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * All rights assigned to U.S. Government, 1994. - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - */ - -#ifndef __UNIX_h -#define __UNIX_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The following define the CPU Family and Model within the family - * - * NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced - * with the name of the appropriate macro for this target CPU. - */ - -#define unix -#define REPLACE_THIS_WITH_THE_CPU_FAMILY -#define REPLACE_THIS_WITH_THE_BSP -#define REPLACE_THIS_WITH_THE_CPU_MODEL -#define REPLACE_THIS_WITH_THE_UNIX_FLAVOR - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "unix" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ - -#if defined(hpux) - -#define RTEMS_MODEL_NAME "hpux" - -#elif defined(solaris) - -#define RTEMS_MODEL_NAME "solaris" - -#else - -#error "Unsupported CPU Model" - -#endif - -#ifndef ASM - -/* type definitions */ - -typedef unsigned char unsigned8; /* 8-bit unsigned integer */ -typedef unsigned short unsigned16; /* 16-bit unsigned integer */ -typedef unsigned int unsigned32; /* 32-bit unsigned integer */ -typedef unsigned long long unsigned64; /* 64-bit unsigned integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef char signed8; /* 8-bit signed integer */ -typedef short signed16; /* 16-bit signed integer */ -typedef int signed32; /* 32-bit signed integer */ -typedef long long signed64; /* 64-bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void ( *unix_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ -#endif -/* end of include file */ - |