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Diffstat (limited to 'c/src/exec/score/cpu/mips/ChangeLog')
| -rw-r--r-- | c/src/exec/score/cpu/mips/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog index 9edafc7635..84248074af 100644 --- a/c/src/exec/score/cpu/mips/ChangeLog +++ b/c/src/exec/score/cpu/mips/ChangeLog @@ -1,3 +1,8 @@ +2000-12-06 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: When mips ISA level is 1, registers in the + context should be 32 not 64 bits. + 2000-11-30 Joel Sherrill <joel@OARcorp.com> * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to |