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Diffstat (limited to 'c/src/exec/score/cpu/mips/ChangeLog')
| -rw-r--r-- | c/src/exec/score/cpu/mips/ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog index 03daf07e5e..c299901989 100644 --- a/c/src/exec/score/cpu/mips/ChangeLog +++ b/c/src/exec/score/cpu/mips/ChangeLog @@ -1,3 +1,9 @@ +2001-04-20 Joel Sherrill <joel@OARcorp.com> + + * cpu_asm.S: Added code to save and restore SR and EPC to + properly support nested interrupts. Note that the ISR + (not RTEMS) enables interrupts allowing the nesting to occur. + 2001-03-14 Joel Sherrill <joel@OARcorp.com> * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: |