diff options
Diffstat (limited to 'bsps')
-rw-r--r-- | bsps/shared/dev/irq/arm-gicv2-get-attributes.c | 77 | ||||
-rw-r--r-- | bsps/shared/dev/irq/arm-gicv2-zynqmp.c | 76 | ||||
-rw-r--r-- | bsps/shared/dev/irq/arm-gicv2.c | 61 |
3 files changed, 180 insertions, 34 deletions
diff --git a/bsps/shared/dev/irq/arm-gicv2-get-attributes.c b/bsps/shared/dev/irq/arm-gicv2-get-attributes.c new file mode 100644 index 0000000000..62aa504678 --- /dev/null +++ b/bsps/shared/dev/irq/arm-gicv2-get-attributes.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsShared + * + * @brief This source file contains the interrupt get attribute implementation. + */ + +/* + * Copyright (c) 2013, 2021 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dev/irq/arm-gic.h> +#include <bsp/irq-generic.h> + +rtems_status_code bsp_interrupt_get_attributes( + rtems_vector_number vector, + rtems_interrupt_attributes *attributes +) +{ + attributes->is_maskable = true; + attributes->maybe_enable = true; + attributes->maybe_disable = true; + attributes->can_raise = true; + + if ( vector <= ARM_GIC_IRQ_SGI_LAST ) { + /* + * It is implementation-defined whether implemented SGIs are permanently + * enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and + * GICD_ICENABLER0. + */ + attributes->can_raise_on = true; + attributes->cleared_by_acknowledge = true; + attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL; + } else { + attributes->can_disable = true; + attributes->can_clear = true; + attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL; + + if ( vector > ARM_GIC_IRQ_PPI_LAST ) { + /* SPI */ + attributes->can_get_affinity = true; + attributes->can_set_affinity = true; + } + } + + return RTEMS_SUCCESSFUL; +} diff --git a/bsps/shared/dev/irq/arm-gicv2-zynqmp.c b/bsps/shared/dev/irq/arm-gicv2-zynqmp.c new file mode 100644 index 0000000000..ee4479155a --- /dev/null +++ b/bsps/shared/dev/irq/arm-gicv2-zynqmp.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsShared + * + * @brief This source file contains the interrupt get attribute implementation. + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * Written by Kinsey Moore <kinsey.moore@oarcorp.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dev/irq/arm-gic.h> +#include <bsp/irq-generic.h> + +rtems_status_code bsp_interrupt_get_attributes( + rtems_vector_number vector, + rtems_interrupt_attributes *attributes +) +{ + attributes->is_maskable = true; + attributes->maybe_enable = true; + attributes->maybe_disable = true; + attributes->can_raise = true; + + if ( vector <= ARM_GIC_IRQ_SGI_LAST ) { + /* + * It is implementation-defined whether implemented SGIs are permanently + * enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and + * GICD_ICENABLER0. + */ + attributes->can_raise_on = true; + attributes->cleared_by_acknowledge = true; + attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL; + } else { + attributes->can_disable = true; + attributes->can_clear = true; + attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL; + + /* + * Interrupt 67 affinity value presents as unimplemented in the + * configuration of the GICv2 instance used in ZynqMP CPUs. + */ + if ( vector > ARM_GIC_IRQ_PPI_LAST && vector != 67 ) { + /* SPI */ + attributes->can_get_affinity = true; + attributes->can_set_affinity = true; + } + } + + return RTEMS_SUCCESSFUL; +} diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c index 9c47a4d47b..b7898e2e97 100644 --- a/bsps/shared/dev/irq/arm-gicv2.c +++ b/bsps/shared/dev/irq/arm-gicv2.c @@ -64,40 +64,6 @@ void bsp_interrupt_dispatch(void) } } -rtems_status_code bsp_interrupt_get_attributes( - rtems_vector_number vector, - rtems_interrupt_attributes *attributes -) -{ - attributes->is_maskable = true; - attributes->maybe_enable = true; - attributes->maybe_disable = true; - attributes->can_raise = true; - - if ( vector <= ARM_GIC_IRQ_SGI_LAST ) { - /* - * It is implementation-defined whether implemented SGIs are permanently - * enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and - * GICD_ICENABLER0. - */ - attributes->can_raise_on = true; - attributes->cleared_by_acknowledge = true; - attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL; - } else { - attributes->can_disable = true; - attributes->can_clear = true; - attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL; - - if ( vector > ARM_GIC_IRQ_PPI_LAST ) { - /* SPI */ - attributes->can_get_affinity = true; - attributes->can_set_affinity = true; - } - } - - return RTEMS_SUCCESSFUL; -} - rtems_status_code bsp_interrupt_is_pending( rtems_vector_number vector, bool *pending @@ -348,11 +314,24 @@ rtems_status_code bsp_interrupt_set_affinity( { volatile gic_dist *dist = ARM_GIC_DIST; uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0); + rtems_interrupt_attributes attr; + rtems_status_code sc; + + memset( &attr, 0, sizeof( attr ) ); + sc = bsp_interrupt_get_attributes( vector, &attr ); + + if ( sc ) { + return sc; + } if ( vector <= ARM_GIC_IRQ_PPI_LAST ) { return RTEMS_UNSATISFIED; } + if ( attr.can_set_affinity == 0 ) { + return RTEMS_UNSATISFIED; + } + gic_id_set_targets(dist, vector, targets); return RTEMS_SUCCESSFUL; } @@ -364,12 +343,26 @@ rtems_status_code bsp_interrupt_get_affinity( { volatile gic_dist *dist = ARM_GIC_DIST; uint8_t targets; + rtems_interrupt_attributes attr; + rtems_status_code sc; + + memset( &attr, 0, sizeof( attr ) ); + sc = bsp_interrupt_get_attributes( vector, &attr ); + + if ( sc ) { + return sc; + } if ( vector <= ARM_GIC_IRQ_PPI_LAST ) { return RTEMS_UNSATISFIED; } targets = gic_id_get_targets(dist, vector); + + if ( attr.can_get_affinity == 0 ) { + return RTEMS_UNSATISFIED; + } + _Processor_mask_From_uint32_t(affinity, targets, 0); return RTEMS_SUCCESSFUL; } |