7 files changed, 171 insertions, 6 deletions

diff --git a/bsps/riscv/riscv/config/kendrytek210.cfg b/bsps/riscv/riscv/config/kendrytek210.cfg
new file mode 100644
index 0000000000..b04e78b0e9
--- /dev/null
+++ b/bsps/riscv/riscv/config/kendrytek210.cfg
@@ -0,0 +1,9 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = riscv
+
+CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany
+
+LDFLAGS = -Wl,--gc-sections
+
+CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections
diff --git a/bsps/riscv/riscv/console/console-config.c b/bsps/riscv/riscv/console/console-config.c
index 4916191e0b..72743fe9d5 100644
--- a/bsps/riscv/riscv/console/console-config.c
+++ b/bsps/riscv/riscv/console/console-config.c
@@ -55,7 +55,7 @@
 #include <libfdt.h>
 #include <string.h>
 
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
 #include <bsp/fe310-uart.h>
 static fe310_uart_context fe310_uart_instance;
 #endif
@@ -239,7 +239,7 @@ static void riscv_console_probe(void)
     }
 #endif
 
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
     if (fdt_stringlist_contains(compat, compat_len, "sifive,uart0")) {
       fe310_uart_context *ctx;
 
@@ -255,7 +255,7 @@ static void riscv_console_probe(void)
         riscv_console.getchar = fe310_uart_read;
       }
 
-      rtems_termios_device_context_initialize(&ctx->base, "FE310UART");
+      rtems_termios_device_context_initialize(&ctx->base, "SIFIVEUART");
     }
 #endif
 
@@ -290,7 +290,7 @@ rtems_status_code console_initialize(
   size_t i;
 #endif
 
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
   fe310_uart_context *ctx;
   char fe310_path[] = "/dev/ttyS0";
 #endif
@@ -326,7 +326,7 @@ rtems_status_code console_initialize(
   }
 #endif
 
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
   ctx = &fe310_uart_instance;
   rtems_termios_device_install(
     fe310_path,
diff --git a/bsps/riscv/riscv/console/fe310-uart.c b/bsps/riscv/riscv/console/fe310-uart.c
index 506521add0..ddabcff4c8 100644
--- a/bsps/riscv/riscv/console/fe310-uart.c
+++ b/bsps/riscv/riscv/console/fe310-uart.c
@@ -53,7 +53,7 @@ static void fe310_uart_write (
   fe310_uart_context * ctx = (fe310_uart_context*) base;
   size_t i;
 
-  ctx->regs->div = riscv_get_core_frequency() / 115200 - 1;
+  ctx->regs->div = (riscv_get_core_frequency() / 115200 - 1) & 0xFFFF;
   ctx->regs->txctrl |= 1;
   ctx->regs->rxctrl |= 1;
 
diff --git a/bsps/riscv/riscv/include/bsp.h b/bsps/riscv/riscv/include/bsp.h
index 911b85f4a3..c33de42aa7 100644
--- a/bsps/riscv/riscv/include/bsp.h
+++ b/bsps/riscv/riscv/include/bsp.h
@@ -60,6 +60,10 @@
 
 #include <rtems/devnull.h>
 
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+   #include <bsp/k210.h>
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/bsps/riscv/riscv/include/bsp/k210.h b/bsps/riscv/riscv/include/bsp/k210.h
new file mode 100644
index 0000000000..d5ae062863
--- /dev/null
+++ b/bsps/riscv/riscv/include/bsp/k210.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup k210_regs
+ *
+ * @brief k210 RISC-V CPU defines.
+ */
+
+/*
+ * Copyright (c) 2022 Alan Cudmore
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in the
+ *      documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_RISCV_RISCV_K210_H
+#define LIBBSP_RISCV_RISCV_K210_H
+
+#include <bspopts.h>
+#include <stdint.h>
+#include <bsp/utility.h>
+
+/**
+ * @defgroup K210 RISC V Register Definitions
+ *
+ * @ingroup RTEMSBSPsriscv
+ *
+ * @brief Register Definitions
+ *
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* For PLL / Clocks */
+#define K210_SYSCTL_BASE     0x50440000
+
+#define PLL_CLK_R(n)         (n & 0x00000F)
+#define PLL_CLK_F(n)         ((n & 0x0003F0) >> 4)
+#define PLL_CLK_OD(n)        ((n & 0x003C00) >> 10)
+#define CLKSEL0_ACLK_SEL(n)  (n & 0x00000001)
+
+typedef struct {
+  uint32_t git_id;
+  uint32_t clk_freq;
+  uint32_t pll0;
+  uint32_t pll1;
+  uint32_t pll2;
+  uint32_t resv5;
+  uint32_t pll_lock;
+  uint32_t rom_error;
+  uint32_t clk_sel0;
+  uint32_t clk_sel1;
+  uint32_t clk_en_cent;
+  uint32_t clk_en_peri;
+  uint32_t soft_reset;
+  uint32_t peri_reset;
+  uint32_t clk_th0;
+  uint32_t clk_th1;
+  uint32_t clk_th2;
+  uint32_t clk_th3;
+  uint32_t clk_th4;
+  uint32_t clk_th5;
+  uint32_t clk_th6;
+  uint32_t misc;
+  uint32_t peri;
+  uint32_t spi_sleep;
+  uint32_t reset_status;
+  uint32_t dma_sel0;
+  uint32_t dma_sel1;
+  uint32_t power_sel;
+  uint32_t resv28;
+  uint32_t resv29;
+  uint32_t resv30;
+  uint32_t resv31;
+} k210_sysctl_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+#endif /* LIBBSP_RISCV_RISCV_K210_H */
diff --git a/bsps/riscv/riscv/include/bsp/riscv.h b/bsps/riscv/riscv/include/bsp/riscv.h
index bbaaa246c1..d294f1ae58 100644
--- a/bsps/riscv/riscv/include/bsp/riscv.h
+++ b/bsps/riscv/riscv/include/bsp/riscv.h
@@ -56,6 +56,10 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle);
 void htif_poweroff(void);
 #endif
 
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+uint32_t k210_get_frequency(void);
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c
index f27713b5bf..fa1e978dc7 100644
--- a/bsps/riscv/riscv/start/bspstart.c
+++ b/bsps/riscv/riscv/start/bspstart.c
@@ -209,7 +209,16 @@ static uint32_t get_core_frequency(void)
     return fdt32_to_cpu(*val);
   }
 #endif
+
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+  uint32_t cpu_clock;
+
+  cpu_clock = k210_get_frequency();
+  return cpu_clock;
+#else
   return 0;
+#endif
+
 }
 
 uint32_t riscv_get_core_frequency(void)
@@ -223,6 +232,40 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
   return RISCV_INTERRUPT_VECTOR_EXTERNAL(intr[0]);
 }
 
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+uint32_t k210_get_frequency(void)
+{
+  k210_sysctl_t *sysctl = (k210_sysctl_t *)K210_SYSCTL_BASE;
+  uint32_t cpu_clock = 0;
+  uint32_t clk_freq;
+  uint32_t pll0, nr, nf, od;
+  uint32_t node;
+  const char *fdt;
+  const fdt32_t *val;
+  int len;
+
+  fdt = bsp_fdt_get();
+  node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");
+  val = fdt_getprop(fdt, node, "clock-frequency", &len);
+  if (val != NULL && len == 4) {
+    clk_freq = fdt32_to_cpu(*val);
+
+    if (CLKSEL0_ACLK_SEL(sysctl->clk_sel0) == 1) {
+       /* PLL0 selected */
+       pll0 = sysctl->pll0;
+       nr = PLL_CLK_R(pll0) + 1;
+       nf = PLL_CLK_F(pll0) + 1;
+       od = PLL_CLK_OD(pll0) + 1;
+       cpu_clock = (clk_freq / nr * nf / od)/2;
+    } else {
+       /* OSC selected */
+       cpu_clock = clk_freq;
+    }
+  }
+  return cpu_clock;
+}
+#endif
+
 void bsp_start(void)
 {
   riscv_find_harts();