diff options
Diffstat (limited to 'bsps/x86_64/amd64/include')
| -rw-r--r-- | bsps/x86_64/amd64/include/apic.h | 62 | ||||
| -rw-r--r-- | bsps/x86_64/amd64/include/clock.h | 99 | ||||
| -rw-r--r-- | bsps/x86_64/amd64/include/pic.h | 75 |
3 files changed, 236 insertions, 0 deletions
diff --git a/bsps/x86_64/amd64/include/apic.h b/bsps/x86_64/amd64/include/apic.h new file mode 100644 index 0000000000..f1e6495daa --- /dev/null +++ b/bsps/x86_64/amd64/include/apic.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2018. + * Amaan Cheval <amaan.cheval@gmail.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _AMD64_APIC_H +#define _AMD64_APIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* The address of the MSR pointing to the APIC base physical address */ +#define APIC_BASE_MSR 0x1B +/* Value to hardware-enable the APIC through the APIC_BASE_MSR */ +#define APIC_BASE_MSR_ENABLE 0x800 + +/* + * Since amd64_apic_base is an array of 32-bit elements, these byte-offsets + * need to be divided by 4 to index the array. + */ +#define APIC_OFFSET(val) (val >> 2) + +#define APIC_REGISTER_APICID APIC_OFFSET(0x20) +#define APIC_REGISTER_EOI APIC_OFFSET(0x0B0) +#define APIC_REGISTER_SPURIOUS APIC_OFFSET(0x0F0) +#define APIC_REGISTER_LVT_TIMER APIC_OFFSET(0x320) +#define APIC_REGISTER_TIMER_INITCNT APIC_OFFSET(0x380) +#define APIC_REGISTER_TIMER_CURRCNT APIC_OFFSET(0x390) +#define APIC_REGISTER_TIMER_DIV APIC_OFFSET(0x3E0) + +#define APIC_DISABLE 0x10000 +#define APIC_EOI_ACK 0 +#define APIC_SELECT_TMR_PERIODIC 0x20000 +#define APIC_SPURIOUS_ENABLE 0x100 + +#ifdef __cplusplus +} +#endif + +#endif /* _AMD64_APIC_H */ diff --git a/bsps/x86_64/amd64/include/clock.h b/bsps/x86_64/amd64/include/clock.h new file mode 100644 index 0000000000..4219c92d48 --- /dev/null +++ b/bsps/x86_64/amd64/include/clock.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2018. + * Amaan Cheval <amaan.cheval@gmail.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _AMD64_CLOCK_H +#define _AMD64_CLOCK_H + +#include <rtems/score/basedefs.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ASM + extern volatile uint32_t *amd64_apic_base; + bool has_apic_support(void); + void apic_initialize(void); + void apic_timer_install_handler(void); + uint32_t apic_timer_calibrate(void); + void apic_timer_initialize(uint64_t desired_freq_hz); + void amd64_clock_driver_initialize(void); +#endif + +/* Number of times to calibrate the APIC timer to average it out */ +#define APIC_TIMER_NUM_CALIBRATIONS 5 +/* Default divide value used by APIC timer */ +#define APIC_TIMER_DIVIDE_VALUE 16 +/* Value to set in register to pick the divide value above */ +#define APIC_TIMER_SELECT_DIVIDER 3 + +#define PIT_FREQUENCY 1193180 +/* + * The PIT_FREQUENCY determines how many times the PIT counter is decremented + * per second - therefore, we can calculate how many ticks we set based on what + * fraction of a second we're okay with spending on calibration + */ +#define PIT_CALIBRATE_DIVIDER 20 +#define PIT_CALIBRATE_TICKS (PIT_FREQUENCY/PIT_CALIBRATE_DIVIDER) +/* Since the PIT only has 2 one-byte registers, the maximum tick value is + * limited to 16-bits. We can set the PIT to use a frequency divider if + * needed. */ +RTEMS_STATIC_ASSERT( + PIT_CALIBRATE_TICKS <= 0xffff, + PIT_CALIBRATE_DIVIDER +); + +/* I/O ports for the PIT */ +#define PIT_PORT_CHAN0 0x40 +#define PIT_PORT_CHAN1 0x41 +#define PIT_PORT_CHAN2 0x42 +/* + * The input to channel 2 can be gated through software, using bit 0 of port + * 0x61. + */ +#define PIT_PORT_CHAN2_GATE 0x61 +#define PIT_CHAN2_TIMER_BIT 1 +#define PIT_CHAN2_SPEAKER_BIT 2 +/* The PIT mode/command register */ +#define PIT_PORT_MCR 0x43 + +/* PIT values to select channels, access, and operating modes */ +#define PIT_SELECT_CHAN0 0b00000000 +#define PIT_SELECT_CHAN1 0b01000000 +#define PIT_SELECT_CHAN2 0b10000000 +/* + * In the lo/hi mode, the low-byte is sent to the data port, followed by the + * high-byte; this makes it important that this be an atomic operation. + */ +#define PIT_SELECT_ACCESS_LOHI 0b00110000 +#define PIT_SELECT_ONE_SHOT_MODE 0b00000010 +#define PIT_SELECT_BINARY_MODE 0 + +#ifdef __cplusplus +} +#endif + +#endif /* _AMD64_CLOCK_H */ diff --git a/bsps/x86_64/amd64/include/pic.h b/bsps/x86_64/amd64/include/pic.h new file mode 100644 index 0000000000..f2b0aa83e2 --- /dev/null +++ b/bsps/x86_64/amd64/include/pic.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2018. + * Amaan Cheval <amaan.cheval@gmail.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _AMD64_PIC_H +#define _AMD64_PIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define PIC1 0x20 /* IO base address for master PIC */ +#define PIC2 0xA0 /* IO base address for slave PIC */ +#define PIC1_COMMAND PIC1 +#define PIC1_DATA (PIC1+1) +#define PIC2_COMMAND PIC2 +#define PIC2_DATA (PIC2+1) + +/* reinitialize the PIC controllers, giving them specified vector offsets + rather than 8h and 70h, as configured by default */ + +#define PIC_ICW1_ICW4 0x01 /* ICW4 (not) needed */ +#define PIC_ICW1_SINGLE 0x02 /* Single (cascade) mode */ +#define PIC_ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */ +#define PIC_ICW1_LEVEL 0x08 /* Level triggered (edge) mode */ +#define PIC_ICW1_INIT 0x10 /* Initialization - required! */ + +#define PIC_ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */ +#define PIC_ICW4_AUTO 0x02 /* Auto (normal) EOI */ +#define PIC_ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */ +#define PIC_ICW4_BUF_MASTER 0x0C /* Buffered mode/master */ +#define PIC_ICW4_SFNM 0x10 /* Special fully nested (not) */ + +/* This remaps IRQ0 to vector number 0x20 and so on (i.e. IDT[32]) */ +#define PIC1_REMAP_DEST 0x20 +#define PIC2_REMAP_DEST 0x28 + +/* Remap PIC1's interrupts to offset1 and PIC2's to offset2 */ +void pic_remap(uint8_t offset1, uint8_t offset2); + +/** + * Mask all interrupt requests on PIC. + * + * @note Even with all interrupts masked, the PIC may still send spurious + * interrupts (IRQ7), so we should handle them still. + */ +void pic_disable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _AMD64_PIC_H */ |