diff options
Diffstat (limited to 'bsps/sparc64/include/arch')
| -rw-r--r-- | bsps/sparc64/include/arch/arch.h | 61 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/boot.h | 98 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/mm/cache_spec.h | 58 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/mm/frame.h | 47 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/mm/mmu.h | 48 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/mm/page.h | 84 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/mm/sun4u/frame.h | 87 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/mm/sun4u/mmu.h | 123 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/mm/sun4u/page.h | 84 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/mm/sun4u/tlb.h | 693 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/mm/sun4u/tte.h | 104 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/mm/tlb.h | 48 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/mm/tte.h | 47 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/regdef.h | 67 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/stack.h | 72 | ||||
| -rw-r--r-- | bsps/sparc64/include/arch/sun4u/arch.h | 47 |
16 files changed, 1768 insertions, 0 deletions
diff --git a/bsps/sparc64/include/arch/arch.h b/bsps/sparc64/include/arch/arch.h new file mode 100644 index 0000000000..5fdd4a2cb2 --- /dev/null +++ b/bsps/sparc64/include/arch/arch.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** + * @file + * @brief Various sparc64-specific macros. + */ + +#ifndef KERN_sparc64_ARCH_H_ +#define KERN_sparc64_ARCH_H_ + +#if defined (SUN4U) +#include <arch/sun4u/arch.h> +#elif defined (SUN4V) +#include <arch/sun4v/arch.h> +#endif + +#define ASI_AIUP 0x10 /** Access to primary context with user privileges. */ +#define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ + +#define NWINDOWS 8 /** Number of register window sets. */ + +#ifndef __ASM__ + +extern void arch_pre_main(void); + +#endif /* __ASM__ */ + + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/boot.h b/bsps/sparc64/include/arch/boot.h new file mode 100644 index 0000000000..b0a997a957 --- /dev/null +++ b/bsps/sparc64/include/arch/boot.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_BOOT_H_ +#define KERN_sparc64_BOOT_H_ + +#if 0 +#define VMA 0x400000 +#endif +#define VMA 0x4000 +#define LMA VMA + +#ifndef __ASM__ +#ifndef __LINKER__ + +#include <config.h> +#include <arch/types.h> +#include <genarch/ofw/ofw_tree.h> + +#define TASKMAP_MAX_RECORDS 32 +#define MEMMAP_MAX_RECORDS 32 + +#define BOOTINFO_TASK_NAME_BUFLEN 32 + +typedef struct { + void * addr; + uint32_t size; + char name[BOOTINFO_TASK_NAME_BUFLEN]; +} utask_t; + +typedef struct { + uint32_t count; + utask_t tasks[TASKMAP_MAX_RECORDS]; +} taskmap_t; + +typedef struct { + uintptr_t start; + uint32_t size; +} memzone_t; + +typedef struct { + uint32_t total; + uint32_t count; + memzone_t zones[MEMMAP_MAX_RECORDS]; +} memmap_t; + +/** Bootinfo structure. + * + * Must be in sync with bootinfo structure used by the boot loader. + */ +typedef struct { + uintptr_t physmem_start; + taskmap_t taskmap; + memmap_t memmap; + ballocs_t ballocs; + ofw_tree_node_t *ofw_root; +} bootinfo_t; + +extern bootinfo_t bootinfo; + +#endif +#endif + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/cache_spec.h b/bsps/sparc64/include/arch/mm/cache_spec.h new file mode 100644 index 0000000000..1d9199db33 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/cache_spec.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2008 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_CACHE_SPEC_H_ +#define KERN_sparc64_CACHE_SPEC_H_ + +/* + * The following macros are valid for the following processors: + * + * UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III, + * UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+ + * + * Should we support other UltraSPARC processors, we need to make sure that + * the macros are defined correctly for them. + */ + +#if defined (US) +#define DCACHE_SIZE (16 * 1024) +#elif defined (US3) +#define DCACHE_SIZE (64 * 1024) +#endif +#define DCACHE_LINE_SIZE 32 + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/frame.h b/bsps/sparc64/include/arch/mm/frame.h new file mode 100644 index 0000000000..fb66e54bf1 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/frame.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_FRAME_H_ +#define KERN_sparc64_FRAME_H_ + +#if defined (SUN4U) +#include <arch/mm/sun4u/frame.h> +#elif defined (SUN4V) +#include <arch/mm/sun4v/frame.h> +#endif + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/mmu.h b/bsps/sparc64/include/arch/mm/mmu.h new file mode 100644 index 0000000000..1d445f2e24 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/mmu.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_MMU_H_ +#define KERN_sparc64_MMU_H_ + +#if defined (SUN4U) +#include <arch/mm/sun4u/mmu.h> +#elif defined (SUN4V) +#include <arch/mm/sun4v/mmu.h> +#endif + + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/page.h b/bsps/sparc64/include/arch/mm/page.h new file mode 100644 index 0000000000..f1451a2866 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/page.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_PAGE_H_ +#define KERN_sparc64_PAGE_H_ + +#include <arch/mm/frame.h> + +/* + * On the TLB and TSB level, we still use 8K pages, which are supported by the + * MMU. + */ +#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH +#define MMU_PAGE_SIZE MMU_FRAME_SIZE + +/* + * On the page table level, we use 16K pages. 16K pages are not supported by + * the MMU but we emulate them with pairs of 8K pages. + */ +#define PAGE_WIDTH FRAME_WIDTH +#define PAGE_SIZE FRAME_SIZE + +#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) + +#ifdef KERNEL + +#ifndef __ASM__ + +#include <arch/interrupt.h> + +extern uintptr_t physmem_base; + +#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) +#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) + +typedef union { + uintptr_t address; + struct { + uint64_t vpn : 51; /**< Virtual Page Number. */ + unsigned offset : 13; /**< Offset. */ + } __attribute__ ((packed)); +} page_address_t; + +extern void page_arch_init(void); + +#endif /* !def __ASM__ */ + +#endif /* KERNEL */ + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/frame.h b/bsps/sparc64/include/arch/mm/sun4u/frame.h new file mode 100644 index 0000000000..e30f504d08 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/sun4u/frame.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_SUN4U_FRAME_H_ +#define KERN_sparc64_SUN4U_FRAME_H_ + +/* + * Page size supported by the MMU. + * For 8K there is the nasty illegal virtual aliasing problem. + * Therefore, the kernel uses 8K only internally on the TLB and TSB levels. + */ +#define MMU_FRAME_WIDTH 13 /* 8K */ +#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) + +/* + * Page size exported to the generic memory management subsystems. + * This page size is not directly supported by the MMU, but we can emulate + * each 16K page with a pair of adjacent 8K pages. + */ +#define FRAME_WIDTH 14 /* 16K */ +#define FRAME_SIZE (1 << FRAME_WIDTH) + +#ifdef KERNEL +#ifndef __ASM__ + +#include <arch/types.h> + +union frame_address { + uintptr_t address; + struct { +#if defined (US) + unsigned : 23; + uint64_t pfn : 28; /**< Physical Frame Number. */ +#elif defined (US3) + unsigned : 21; + uint64_t pfn : 30; /**< Physical Frame Number. */ +#endif + unsigned offset : 13; /**< Offset. */ + } __attribute__ ((packed)); +}; + +typedef union frame_address frame_address_t; + +extern uintptr_t last_frame; +extern uintptr_t end_of_identity; + +extern void frame_arch_init(void); +#define physmem_print() + +#endif +#endif + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/mmu.h b/bsps/sparc64/include/arch/mm/sun4u/mmu.h new file mode 100644 index 0000000000..f887ebe7f4 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/sun4u/mmu.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_MMU_H_ +#define KERN_sparc64_sun4u_MMU_H_ + +#if defined(US) +/* LSU Control Register ASI. */ +#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ +#endif + +/* I-MMU ASIs. */ +#define ASI_IMMU 0x50 +#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 +#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 +#define ASI_ITLB_DATA_IN_REG 0x54 +#define ASI_ITLB_DATA_ACCESS_REG 0x55 +#define ASI_ITLB_TAG_READ_REG 0x56 +#define ASI_IMMU_DEMAP 0x57 + +/* Virtual Addresses within ASI_IMMU. */ +#define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ +#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ +#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ +#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ +#if defined (US3) +#define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ +#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ +#endif + + +/* D-MMU ASIs. */ +#define ASI_DMMU 0x58 +#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 +#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a +#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b +#define ASI_DTLB_DATA_IN_REG 0x5c +#define ASI_DTLB_DATA_ACCESS_REG 0x5d +#define ASI_DTLB_TAG_READ_REG 0x5e +#define ASI_DMMU_DEMAP 0x5f + +/* Virtual Addresses within ASI_DMMU. */ +#define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ +#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ +#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ +#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ +#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ +#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ +#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ +#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ +#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ +#if defined (US3) +#define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ +#define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ +#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ +#endif + +#ifndef __ASM__ + +#include <arch/asm.h> +#include <arch/barrier.h> +#include <arch/types.h> + +#if defined(US) +/** LSU Control Register. */ +typedef union { + uint64_t value; + struct { + unsigned : 23; + unsigned pm : 8; + unsigned vm : 8; + unsigned pr : 1; + unsigned pw : 1; + unsigned vr : 1; + unsigned vw : 1; + unsigned : 1; + unsigned fm : 16; + unsigned dm : 1; /**< D-MMU enable. */ + unsigned im : 1; /**< I-MMU enable. */ + unsigned dc : 1; /**< D-Cache enable. */ + unsigned ic : 1; /**< I-Cache enable. */ + + } __attribute__ ((packed)); +} lsu_cr_reg_t; +#endif /* US */ + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/page.h b/bsps/sparc64/include/arch/mm/sun4u/page.h new file mode 100644 index 0000000000..f1451a2866 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/sun4u/page.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_PAGE_H_ +#define KERN_sparc64_PAGE_H_ + +#include <arch/mm/frame.h> + +/* + * On the TLB and TSB level, we still use 8K pages, which are supported by the + * MMU. + */ +#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH +#define MMU_PAGE_SIZE MMU_FRAME_SIZE + +/* + * On the page table level, we use 16K pages. 16K pages are not supported by + * the MMU but we emulate them with pairs of 8K pages. + */ +#define PAGE_WIDTH FRAME_WIDTH +#define PAGE_SIZE FRAME_SIZE + +#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) + +#ifdef KERNEL + +#ifndef __ASM__ + +#include <arch/interrupt.h> + +extern uintptr_t physmem_base; + +#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) +#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) + +typedef union { + uintptr_t address; + struct { + uint64_t vpn : 51; /**< Virtual Page Number. */ + unsigned offset : 13; /**< Offset. */ + } __attribute__ ((packed)); +} page_address_t; + +extern void page_arch_init(void); + +#endif /* !def __ASM__ */ + +#endif /* KERNEL */ + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/tlb.h b/bsps/sparc64/include/arch/mm/sun4u/tlb.h new file mode 100644 index 0000000000..6f6e6542e6 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/sun4u/tlb.h @@ -0,0 +1,693 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TLB_sun4u_H_ +#define KERN_sparc64_TLB_sun4u_H_ + +#if defined (US) +#define ITLB_ENTRY_COUNT 64 +#define DTLB_ENTRY_COUNT 64 +#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT +#endif + +/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ +#if defined (US3) +#define DTLB_MAX_LOCKED_ENTRIES 16 +#endif + +#define MEM_CONTEXT_KERNEL 0 +#define MEM_CONTEXT_TEMP 1 + +/** Page sizes. */ +#define PAGESIZE_8K 0 +#define PAGESIZE_64K 1 +#define PAGESIZE_512K 2 +#define PAGESIZE_4M 3 + +/** Bit width of the TLB-locked portion of kernel address space. */ +#define KERNEL_PAGE_WIDTH 22 /* 4M */ + +/* TLB Demap Operation types. */ +#define TLB_DEMAP_PAGE 0 +#define TLB_DEMAP_CONTEXT 1 +#if defined (US3) +#define TLB_DEMAP_ALL 2 +#endif + +#define TLB_DEMAP_TYPE_SHIFT 6 + +/* TLB Demap Operation Context register encodings. */ +#define TLB_DEMAP_PRIMARY 0 +#define TLB_DEMAP_SECONDARY 1 +#define TLB_DEMAP_NUCLEUS 2 + +/* There are more TLBs in one MMU in US3, their codes are defined here. */ +#if defined (US3) +/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */ +#define TLB_DSMALL 0 +#define TLB_DBIG_0 2 +#define TLB_DBIG_1 3 + +/* I-MMU: one small (16-entry) TLB and one big TLB */ +#define TLB_ISMALL 0 +#define TLB_IBIG 2 +#endif + +#define TLB_DEMAP_CONTEXT_SHIFT 4 + +/* TLB Tag Access shifts */ +#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 +#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) +#define TLB_TAG_ACCESS_VPN_SHIFT 13 + +#ifndef __ASM__ + +#include <arch/mm/tte.h> +#include <arch/mm/mmu.h> +#include <arch/mm/page.h> +#include <arch/asm.h> +#include <arch/barrier.h> +#include <arch/types.h> +#include <arch/register.h> +#include <arch/cpu.h> + +union tlb_context_reg { + uint64_t v; + struct { + unsigned long : 51; + unsigned context : 13; /**< Context/ASID. */ + } __attribute__ ((packed)); +}; +typedef union tlb_context_reg tlb_context_reg_t; + +/** I-/D-TLB Data In/Access Register type. */ +typedef tte_data_t tlb_data_t; + +/** I-/D-TLB Data Access Address in Alternate Space. */ + +#if defined (US) + +union tlb_data_access_addr { + uint64_t value; + struct { + uint64_t : 55; + unsigned tlb_entry : 6; + unsigned : 3; + } __attribute__ ((packed)); +}; +typedef union tlb_data_access_addr dtlb_data_access_addr_t; +typedef union tlb_data_access_addr dtlb_tag_read_addr_t; +typedef union tlb_data_access_addr itlb_data_access_addr_t; +typedef union tlb_data_access_addr itlb_tag_read_addr_t; + +#elif defined (US3) + +/* + * In US3, I-MMU and D-MMU have different formats of the data + * access register virtual address. In the corresponding + * structures the member variable for the entry number is + * called "local_tlb_entry" - it contrasts with the "tlb_entry" + * for the US data access register VA structure. The rationale + * behind this is to prevent careless mistakes in the code + * caused by setting only the entry number and not the TLB + * number in the US3 code (when taking the code from US). + */ + +union dtlb_data_access_addr { + uint64_t value; + struct { + uint64_t : 45; + unsigned : 1; + unsigned tlb_number : 2; + unsigned : 4; + unsigned local_tlb_entry : 9; + unsigned : 3; + } __attribute__ ((packed)); +}; +typedef union dtlb_data_access_addr dtlb_data_access_addr_t; +typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; + +union itlb_data_access_addr { + uint64_t value; + struct { + uint64_t : 45; + unsigned : 1; + unsigned tlb_number : 2; + unsigned : 6; + unsigned local_tlb_entry : 7; + unsigned : 3; + } __attribute__ ((packed)); +}; +typedef union itlb_data_access_addr itlb_data_access_addr_t; +typedef union itlb_data_access_addr itlb_tag_read_addr_t; + +#endif + +/** I-/D-TLB Tag Read Register. */ +union tlb_tag_read_reg { + uint64_t value; + struct { + uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ + unsigned context : 13; /**< Context identifier. */ + } __attribute__ ((packed)); +}; +typedef union tlb_tag_read_reg tlb_tag_read_reg_t; +typedef union tlb_tag_read_reg tlb_tag_access_reg_t; + + +/** TLB Demap Operation Address. */ +union tlb_demap_addr { + uint64_t value; + struct { + uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ +#if defined (US) + unsigned : 6; /**< Ignored. */ + unsigned type : 1; /**< The type of demap operation. */ +#elif defined (US3) + unsigned : 5; /**< Ignored. */ + unsigned type: 2; /**< The type of demap operation. */ +#endif + unsigned context : 2; /**< Context register selection. */ + unsigned : 4; /**< Zero. */ + } __attribute__ ((packed)); +}; +typedef union tlb_demap_addr tlb_demap_addr_t; + +/** TLB Synchronous Fault Status Register. */ +union tlb_sfsr_reg { + uint64_t value; + struct { +#if defined (US) + unsigned long : 40; /**< Implementation dependent. */ + unsigned asi : 8; /**< ASI. */ + unsigned : 2; + unsigned ft : 7; /**< Fault type. */ +#elif defined (US3) + unsigned long : 39; /**< Implementation dependent. */ + unsigned nf : 1; /**< Non-faulting load. */ + unsigned asi : 8; /**< ASI. */ + unsigned tm : 1; /**< I-TLB miss. */ + unsigned : 3; /**< Reserved. */ + unsigned ft : 5; /**< Fault type. */ +#endif + unsigned e : 1; /**< Side-effect bit. */ + unsigned ct : 2; /**< Context Register selection. */ + unsigned pr : 1; /**< Privilege bit. */ + unsigned w : 1; /**< Write bit. */ + unsigned ow : 1; /**< Overwrite bit. */ + unsigned fv : 1; /**< Fault Valid bit. */ + } __attribute__ ((packed)); +}; +typedef union tlb_sfsr_reg tlb_sfsr_reg_t; + +#if defined (US3) + +/* + * Functions for determining the number of entries in TLBs. They either return + * a constant value or a value based on the CPU autodetection. + */ + +/** + * Determine the number of entries in the DMMU's small TLB. + */ +static inline uint16_t tlb_dsmall_size(void) +{ + return 16; +} + +/** + * Determine the number of entries in each DMMU's big TLB. + */ +static inline uint16_t tlb_dbig_size(void) +{ + return 512; +} + +/** + * Determine the number of entries in the IMMU's small TLB. + */ +static inline uint16_t tlb_ismall_size(void) +{ + return 16; +} + +/** + * Determine the number of entries in the IMMU's big TLB. + */ +static inline uint16_t tlb_ibig_size(void) +{ + if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) + return 512; + else + return 128; +} + +#endif + +/** Read MMU Primary Context Register. + * + * @return Current value of Primary Context Register. + */ +static inline uint64_t mmu_primary_context_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); +} + +/** Write MMU Primary Context Register. + * + * @param v New value of Primary Context Register. + */ +static inline void mmu_primary_context_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); + flush_pipeline(); +} + +/** Read MMU Secondary Context Register. + * + * @return Current value of Secondary Context Register. + */ +static inline uint64_t mmu_secondary_context_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); +} + +/** Write MMU Primary Context Register. + * + * @param v New value of Primary Context Register. + */ +static inline void mmu_secondary_context_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); + flush_pipeline(); +} + +#if defined (US) + +/** Read IMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Data Access + * Register. + */ +static inline uint64_t itlb_data_access_read(size_t entry) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); +} + +/** Write IMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * @param value Value to be written. + */ +static inline void itlb_data_access_write(size_t entry, uint64_t value) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); + flush_pipeline(); +} + +/** Read DMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Data Access + * Register. + */ +static inline uint64_t dtlb_data_access_read(size_t entry) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); +} + +/** Write DMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * @param value Value to be written. + */ +static inline void dtlb_data_access_write(size_t entry, uint64_t value) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); + membar(); +} + +/** Read IMMU TLB Tag Read Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Tag Read Register. + */ +static inline uint64_t itlb_tag_read_read(size_t entry) +{ + itlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_entry = entry; + return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); +} + +/** Read DMMU TLB Tag Read Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Tag Read Register. + */ +static inline uint64_t dtlb_tag_read_read(size_t entry) +{ + dtlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_entry = entry; + return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); +} + +#elif defined (US3) + + +/** Read IMMU TLB Data Access Register. + * + * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Data Access + * Register. + */ +static inline uint64_t itlb_data_access_read(int tlb, size_t entry) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); +} + +/** Write IMMU TLB Data Access Register. + * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) + * @param entry TLB Entry index. + * @param value Value to be written. + */ +static inline void itlb_data_access_write(int tlb, size_t entry, + uint64_t value) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); + flush_pipeline(); +} + +/** Read DMMU TLB Data Access Register. + * + * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Data Access + * Register. + */ +static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); +} + +/** Write DMMU TLB Data Access Register. + * + * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) + * @param entry TLB Entry index. + * @param value Value to be written. + */ +static inline void dtlb_data_access_write(int tlb, size_t entry, + uint64_t value) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); + membar(); +} + +/** Read IMMU TLB Tag Read Register. + * + * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Tag Read Register. + */ +static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) +{ + itlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_number = tlb; + tag.local_tlb_entry = entry; + return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); +} + +/** Read DMMU TLB Tag Read Register. + * + * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Tag Read Register. + */ +static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) +{ + dtlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_number = tlb; + tag.local_tlb_entry = entry; + return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); +} + +#endif + + +/** Write IMMU TLB Tag Access Register. + * + * @param v Value to be written. + */ +static inline void itlb_tag_access_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); + flush_pipeline(); +} + +/** Read IMMU TLB Tag Access Register. + * + * @return Current value of IMMU TLB Tag Access Register. + */ +static inline uint64_t itlb_tag_access_read(void) +{ + return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); +} + +/** Write DMMU TLB Tag Access Register. + * + * @param v Value to be written. + */ +static inline void dtlb_tag_access_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); + membar(); +} + +/** Read DMMU TLB Tag Access Register. + * + * @return Current value of DMMU TLB Tag Access Register. + */ +static inline uint64_t dtlb_tag_access_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); +} + + +/** Write IMMU TLB Data in Register. + * + * @param v Value to be written. + */ +static inline void itlb_data_in_write(uint64_t v) +{ + asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); + flush_pipeline(); +} + +/** Write DMMU TLB Data in Register. + * + * @param v Value to be written. + */ +static inline void dtlb_data_in_write(uint64_t v) +{ + asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); + membar(); +} + +/** Read ITLB Synchronous Fault Status Register. + * + * @return Current content of I-SFSR register. + */ +static inline uint64_t itlb_sfsr_read(void) +{ + return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); +} + +/** Write ITLB Synchronous Fault Status Register. + * + * @param v New value of I-SFSR register. + */ +static inline void itlb_sfsr_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); + flush_pipeline(); +} + +/** Read DTLB Synchronous Fault Status Register. + * + * @return Current content of D-SFSR register. + */ +static inline uint64_t dtlb_sfsr_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); +} + +/** Write DTLB Synchronous Fault Status Register. + * + * @param v New value of D-SFSR register. + */ +static inline void dtlb_sfsr_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); + membar(); +} + +/** Read DTLB Synchronous Fault Address Register. + * + * @return Current content of D-SFAR register. + */ +static inline uint64_t dtlb_sfar_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); +} + +/** Perform IMMU TLB Demap Operation. + * + * @param type Selects between context and page demap (and entire MMU + * demap on US3). + * @param context_encoding Specifies which Context register has Context ID for + * demap. + * @param page Address which is on the page to be demapped. + */ +static inline void itlb_demap(int type, int context_encoding, uintptr_t page) +{ + tlb_demap_addr_t da; + page_address_t pg; + + da.value = 0; + pg.address = page; + + da.type = type; + da.context = context_encoding; + da.vpn = pg.vpn; + + /* da.value is the address within the ASI */ + asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); + + flush_pipeline(); +} + +/** Perform DMMU TLB Demap Operation. + * + * @param type Selects between context and page demap (and entire MMU + * demap on US3). + * @param context_encoding Specifies which Context register has Context ID for + * demap. + * @param page Address which is on the page to be demapped. + */ +static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) +{ + tlb_demap_addr_t da; + page_address_t pg; + + da.value = 0; + pg.address = page; + + da.type = type; + da.context = context_encoding; + da.vpn = pg.vpn; + + /* da.value is the address within the ASI */ + asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); + + membar(); +} + +extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); +extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *); +extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *); + +extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); + +extern void dump_sfsr_and_sfar(void); +extern void describe_dmmu_fault(void); + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/sun4u/tte.h b/bsps/sparc64/include/arch/mm/sun4u/tte.h new file mode 100644 index 0000000000..46acaed47c --- /dev/null +++ b/bsps/sparc64/include/arch/mm/sun4u/tte.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_TTE_H_ +#define KERN_sparc64_sun4u_TTE_H_ + +#define TTE_G (1 << 0) +#define TTE_W (1 << 1) +#define TTE_P (1 << 2) +#define TTE_E (1 << 3) +#define TTE_CV (1 << 4) +#define TTE_CP (1 << 5) +#define TTE_L (1 << 6) + +#define TTE_V_SHIFT 63 +#define TTE_SIZE_SHIFT 61 + +#ifndef __ASM__ + +#include <arch/types.h> + +/* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */ +#define VA_TAG_PAGE_SHIFT 22 + +/** Translation Table Entry - Tag. */ +union tte_tag { + uint64_t value; + struct { + unsigned g : 1; /**< Global. */ + unsigned : 2; /**< Reserved. */ + unsigned context : 13; /**< Context identifier. */ + unsigned : 6; /**< Reserved. */ + uint64_t va_tag : 42; /**< Virtual Address Tag, bits 63:22. */ + } __attribute__ ((packed)); +}; + +typedef union tte_tag tte_tag_t; + +/** Translation Table Entry - Data. */ +union tte_data { + uint64_t value; + struct { + unsigned v : 1; /**< Valid. */ + unsigned size : 2; /**< Page size of this entry. */ + unsigned nfo : 1; /**< No-Fault-Only. */ + unsigned ie : 1; /**< Invert Endianness. */ + unsigned soft2 : 9; /**< Software defined field. */ +#if defined (US) + unsigned diag : 9; /**< Diagnostic data. */ + unsigned pfn : 28; /**< Physical Address bits, bits 40:13. */ +#elif defined (US3) + unsigned : 7; /**< Reserved. */ + unsigned pfn : 30; /**< Physical Address bits, bits 42:13 */ +#endif + unsigned soft : 6; /**< Software defined field. */ + unsigned l : 1; /**< Lock. */ + unsigned cp : 1; /**< Cacheable in physically indexed cache. */ + unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ + unsigned e : 1; /**< Side-effect. */ + unsigned p : 1; /**< Privileged. */ + unsigned w : 1; /**< Writable. */ + unsigned g : 1; /**< Global. */ + } __attribute__ ((packed)); +}; + +typedef union tte_data tte_data_t; + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/tlb.h b/bsps/sparc64/include/arch/mm/tlb.h new file mode 100644 index 0000000000..4adf26ca64 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/tlb.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TLB_H_ +#define KERN_sparc64_TLB_H_ + + +#if defined (SUN4U) +#include <arch/mm/sun4u/tlb.h> +#elif defined (SUN4V) +#include <arch/mm/sun4v/tlb.h> +#endif + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/mm/tte.h b/bsps/sparc64/include/arch/mm/tte.h new file mode 100644 index 0000000000..f0b746e8c6 --- /dev/null +++ b/bsps/sparc64/include/arch/mm/tte.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TTE_H_ +#define KERN_sparc64_TTE_H_ + +#if defined (SUN4U) +#include <arch/mm/sun4u/tte.h> +#elif defined (SUN4V) +#include <arch/mm/sun4v/tte.h> +#endif + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/regdef.h b/bsps/sparc64/include/arch/regdef.h new file mode 100644 index 0000000000..aae46fa99f --- /dev/null +++ b/bsps/sparc64/include/arch/regdef.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_REGDEF_H_ +#define KERN_sparc64_REGDEF_H_ + +#define PSTATE_IE_BIT (1 << 1) +#define PSTATE_AM_BIT (1 << 3) + +#define PSTATE_AG_BIT (1 << 0) +#define PSTATE_IG_BIT (1 << 11) +#define PSTATE_MG_BIT (1 << 10) + +#define PSTATE_PRIV_BIT (1 << 2) +#define PSTATE_PEF_BIT (1 << 4) + +#define TSTATE_PSTATE_SHIFT 8 +#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT << TSTATE_PSTATE_SHIFT) +#define TSTATE_IE_BIT (PSTATE_IE_BIT << TSTATE_PSTATE_SHIFT) +#define TSTATE_PEF_BIT (PSTATE_PEF_BIT << TSTATE_PSTATE_SHIFT) + +#define TSTATE_CWP_MASK 0x1f + +#define WSTATE_NORMAL(n) (n) +#define WSTATE_OTHER(n) ((n) << 3) + +/* + * The following definitions concern the UPA_CONFIG register on US and the + * FIREPLANE_CONFIG register on US3. + */ +#define ICBUS_CONFIG_MID_SHIFT 17 + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/stack.h b/bsps/sparc64/include/arch/stack.h new file mode 100644 index 0000000000..6364916912 --- /dev/null +++ b/bsps/sparc64/include/arch/stack.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_STACK_H_ +#define KERN_sparc64_STACK_H_ + +#define STACK_ITEM_SIZE 8 + +/** According to SPARC Compliance Definition, every stack frame is 16-byte aligned. */ +#define STACK_ALIGNMENT 16 + +/** + * 16-extended-word save area for %i[0-7] and %l[0-7] registers. + */ +#define STACK_WINDOW_SAVE_AREA_SIZE (16 * STACK_ITEM_SIZE) + +/** + * Six extended words for first six arguments. + */ +#define STACK_ARG_SAVE_AREA_SIZE (6 * STACK_ITEM_SIZE) + +/** + * By convention, the actual top of the stack is %sp + STACK_BIAS. + */ +#define STACK_BIAS 2047 + +/* + * Offsets of arguments on stack. + */ +#define STACK_ARG0 0 +#define STACK_ARG1 8 +#define STACK_ARG2 16 +#define STACK_ARG3 24 +#define STACK_ARG4 32 +#define STACK_ARG5 40 +#define STACK_ARG6 48 + +#endif + +/** @} + */ diff --git a/bsps/sparc64/include/arch/sun4u/arch.h b/bsps/sparc64/include/arch/sun4u/arch.h new file mode 100644 index 0000000000..9e883a37ff --- /dev/null +++ b/bsps/sparc64/include/arch/sun4u/arch.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** + * @file + * @brief Various sun4u-specific macros. + */ + +#ifndef KERN_sparc64_sun4u_ARCH_H_ +#define KERN_sparc64_sun4u_ARCH_H_ + +#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ +#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ +#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ + +#endif + +/** @} + */ |