diff options
Diffstat (limited to 'bsps/sparc/leon3/include')
| -rw-r--r-- | bsps/sparc/leon3/include/amba.h | 25 | ||||
| -rw-r--r-- | bsps/sparc/leon3/include/bsp.h | 19 | ||||
| -rw-r--r-- | bsps/sparc/leon3/include/bsp/gr740-bootstrap-regs.h | 137 | ||||
| -rw-r--r-- | bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h | 679 | ||||
| -rw-r--r-- | bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h | 229 | ||||
| -rw-r--r-- | bsps/sparc/leon3/include/bsp/irq.h | 40 | ||||
| -rw-r--r-- | bsps/sparc/leon3/include/bsp/irqimpl.h | 151 | ||||
| -rw-r--r-- | bsps/sparc/leon3/include/bsp/leon3.h | 387 | ||||
| -rw-r--r-- | bsps/sparc/leon3/include/bsp/watchdog.h | 25 | ||||
| -rw-r--r-- | bsps/sparc/leon3/include/leon.h | 265 | ||||
| -rw-r--r-- | bsps/sparc/leon3/include/tm27.h | 40 |
11 files changed, 1749 insertions, 248 deletions
diff --git a/bsps/sparc/leon3/include/amba.h b/bsps/sparc/leon3/include/amba.h index 1492661fa5..636187bb23 100644 --- a/bsps/sparc/leon3/include/amba.h +++ b/bsps/sparc/leon3/include/amba.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * @@ -12,9 +14,26 @@ * COPYRIGHT (c) 2004. * Gaisler Research * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AMBA_H__ diff --git a/bsps/sparc/leon3/include/bsp.h b/bsps/sparc/leon3/include/bsp.h index d47f5d2cdf..ae48d3fd4e 100644 --- a/bsps/sparc/leon3/include/bsp.h +++ b/bsps/sparc/leon3/include/bsp.h @@ -148,7 +148,7 @@ typedef void (*bsp_shared_isr)(void *arg); * isr Function pointer to the ISR * arg Second argument to function isr */ -static __inline__ int BSP_shared_interrupt_register +RTEMS_DEPRECATED static inline int BSP_shared_interrupt_register ( int irq, const char *info, @@ -167,7 +167,7 @@ static __inline__ int BSP_shared_interrupt_register * isr Function pointer to the ISR * arg Second argument to function isr */ -static __inline__ int BSP_shared_interrupt_unregister +RTEMS_DEPRECATED static inline int BSP_shared_interrupt_unregister ( int irq, bsp_shared_isr isr, @@ -185,7 +185,10 @@ static __inline__ int BSP_shared_interrupt_unregister * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_clear(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_clear( int irq ) +{ + (void) rtems_interrupt_clear( (rtems_vector_number) irq ); +} /* Enable Interrupt. This function will unmask the IRQ at the interrupt * controller. This is normally done by _register(). Note that this will @@ -194,7 +197,10 @@ extern void BSP_shared_interrupt_clear(int irq); * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_unmask(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_unmask( int irq ) +{ + (void) rtems_interrupt_vector_enable( (rtems_vector_number) irq ); +} /* Disable Interrupt. This function will mask one IRQ at the interrupt * controller. This is normally done by _unregister(). Note that this will @@ -203,7 +209,10 @@ extern void BSP_shared_interrupt_unmask(int irq); * Arguments * irq System IRQ number */ -extern void BSP_shared_interrupt_mask(int irq); +RTEMS_DEPRECATED static inline void BSP_shared_interrupt_mask( int irq ) +{ + (void) rtems_interrupt_vector_disable( (rtems_vector_number) irq ); +} #if defined(RTEMS_SMP) || defined(RTEMS_MULTIPROCESSING) /* Irq used by the shared memory driver and for inter-processor interrupts. diff --git a/bsps/sparc/leon3/include/bsp/gr740-bootstrap-regs.h b/bsps/sparc/leon3/include/bsp/gr740-bootstrap-regs.h new file mode 100644 index 0000000000..33fb71aaab --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/gr740-bootstrap-regs.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsGR740Bootstrap + * + * @brief This header file defines the GR740 Boostrap Signals register block + * interface. + */ + +/* + * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-bootstrap-header */ + +#ifndef _BSP_GR740_BOOTSTRAP_REGS_H +#define _BSP_GR740_BOOTSTRAP_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-bootstrap */ + +/** + * @defgroup RTEMSBSPsGR740Bootstrap GR740 Bootstrap Signals + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This group contains the GR740 Bootstrap Signals interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSBSPsGR740BootstrapBOOTSTRAP Bootstrap register (BOOTSTRAP) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_BOOTSTRAP_BOOTSTRAP_B10 0x2000000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B9 0x1000000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B8 0x800000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B7 0x400000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B6 0x200000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B5 0x100000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B4 0x80000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B3 0x40000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B2 0x20000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_B1 0x10000U + +#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT 0 +#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK 0xffffU +#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_GET( _reg ) \ + ( ( ( _reg ) & GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK ) >> \ + GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT ) +#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK ) | \ + ( ( ( _val ) << GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT ) & \ + GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK ) ) +#define GR740_BOOTSTRAP_BOOTSTRAP_GPIO( _val ) \ + ( ( ( _val ) << GR740_BOOTSTRAP_BOOTSTRAP_GPIO_SHIFT ) & \ + GR740_BOOTSTRAP_BOOTSTRAP_GPIO_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GR740 Bootstrap Signals register block + * memory map. + */ +typedef struct gr740_bootstrap { + /** + * @brief See @ref RTEMSBSPsGR740BootstrapBOOTSTRAP. + */ + uint32_t bootstrap; +} gr740_bootstrap; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_GR740_BOOTSTRAP_REGS_H */ diff --git a/bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h b/bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h new file mode 100644 index 0000000000..1614ebba8a --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/gr740-iopll-regs.h @@ -0,0 +1,679 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsGR740IOPLL + * + * @brief This header file defines the GR740 I/O and PLL configuration register + * block interface. + */ + +/* + * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-iopll-header */ + +#ifndef _BSP_GR740_IOPLL_REGS_H +#define _BSP_GR740_IOPLL_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-iopll */ + +/** + * @defgroup RTEMSBSPsGR740IOPLL GR740 I/0 and PLL Configuration + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This group contains the GR740 I/0 and PLL Configuration interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLFTMFUNC \ + * FTMCTRL function enable register (FTMFUNC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_FTMFUNC_FTMEN_SHIFT 0 +#define GR740_IOPLL_FTMFUNC_FTMEN_MASK 0x3fffffU +#define GR740_IOPLL_FTMFUNC_FTMEN_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_FTMFUNC_FTMEN_MASK ) >> \ + GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) +#define GR740_IOPLL_FTMFUNC_FTMEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_FTMFUNC_FTMEN_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) & \ + GR740_IOPLL_FTMFUNC_FTMEN_MASK ) ) +#define GR740_IOPLL_FTMFUNC_FTMEN( _val ) \ + ( ( ( _val ) << GR740_IOPLL_FTMFUNC_FTMEN_SHIFT ) & \ + GR740_IOPLL_FTMFUNC_FTMEN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLALTFUNC \ + * Alternative function enable register (ALTFUNC) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_ALTFUNC_ALTEN_SHIFT 0 +#define GR740_IOPLL_ALTFUNC_ALTEN_MASK 0x3fffffU +#define GR740_IOPLL_ALTFUNC_ALTEN_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_ALTFUNC_ALTEN_MASK ) >> \ + GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) +#define GR740_IOPLL_ALTFUNC_ALTEN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_ALTFUNC_ALTEN_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) & \ + GR740_IOPLL_ALTFUNC_ALTEN_MASK ) ) +#define GR740_IOPLL_ALTFUNC_ALTEN( _val ) \ + ( ( ( _val ) << GR740_IOPLL_ALTFUNC_ALTEN_SHIFT ) & \ + GR740_IOPLL_ALTFUNC_ALTEN_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLLVDSMCLK \ + * LVDS and memory clock pad enable register (LVDSMCLK) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_LVDSMCLK_SMEM 0x20000U + +#define GR740_IOPLL_LVDSMCLK_DMEM 0x10000U + +#define GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT 0 +#define GR740_IOPLL_LVDSMCLK_SPWOE_MASK 0xffU +#define GR740_IOPLL_LVDSMCLK_SPWOE_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) >> \ + GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) +#define GR740_IOPLL_LVDSMCLK_SPWOE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \ + GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) ) +#define GR740_IOPLL_LVDSMCLK_SPWOE( _val ) \ + ( ( ( _val ) << GR740_IOPLL_LVDSMCLK_SPWOE_SHIFT ) & \ + GR740_IOPLL_LVDSMCLK_SPWOE_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLPLLNEWCFG \ + * PLL new configuration register (PLLNEWCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT 27 +#define GR740_IOPLL_PLLNEWCFG_SWTAG_MASK 0x18000000U +#define GR740_IOPLL_PLLNEWCFG_SWTAG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) >> \ + GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) +#define GR740_IOPLL_PLLNEWCFG_SWTAG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) ) +#define GR740_IOPLL_PLLNEWCFG_SWTAG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SWTAG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SWTAG_MASK ) + +#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT 18 +#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK 0x7fc0000U +#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLNEWCFG_SPWPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SPWPLLCFG_MASK ) + +#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT 9 +#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK 0x3fe00U +#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLNEWCFG_MEMPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_MEMPLLCFG_MASK ) + +#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT 0 +#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK 0x1ffU +#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLNEWCFG_SYSPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLNEWCFG_SYSPLLCFG_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLPLLRECFG \ + * PLL reconfigure command register (PLLRECFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_PLLRECFG_RECONF_SHIFT 0 +#define GR740_IOPLL_PLLRECFG_RECONF_MASK 0x7U +#define GR740_IOPLL_PLLRECFG_RECONF_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLRECFG_RECONF_MASK ) >> \ + GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) +#define GR740_IOPLL_PLLRECFG_RECONF_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLRECFG_RECONF_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) & \ + GR740_IOPLL_PLLRECFG_RECONF_MASK ) ) +#define GR740_IOPLL_PLLRECFG_RECONF( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLRECFG_RECONF_SHIFT ) & \ + GR740_IOPLL_PLLRECFG_RECONF_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLPLLCURCFG \ + * PLL current configuration register (PLLCURCFG) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT 27 +#define GR740_IOPLL_PLLCURCFG_SWTAG_MASK 0x18000000U +#define GR740_IOPLL_PLLCURCFG_SWTAG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) >> \ + GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) +#define GR740_IOPLL_PLLCURCFG_SWTAG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) ) +#define GR740_IOPLL_PLLCURCFG_SWTAG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SWTAG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SWTAG_MASK ) + +#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT 18 +#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK 0x7fc0000U +#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLCURCFG_SPWPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SPWPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SPWPLLCFG_MASK ) + +#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT 9 +#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK 0x3fe00U +#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLCURCFG_MEMPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_MEMPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_MEMPLLCFG_MASK ) + +#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT 0 +#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK 0x1ffU +#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) >> \ + GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) +#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) ) +#define GR740_IOPLL_PLLCURCFG_SYSPLLCFG( _val ) \ + ( ( ( _val ) << GR740_IOPLL_PLLCURCFG_SYSPLLCFG_SHIFT ) & \ + GR740_IOPLL_PLLCURCFG_SYSPLLCFG_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLDRVSTR1 \ + * Drive strength configuration register 1 (DRVSTR1) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_DRVSTR1_S9_SHIFT 18 +#define GR740_IOPLL_DRVSTR1_S9_MASK 0xc0000U +#define GR740_IOPLL_DRVSTR1_S9_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S9_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S9_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S9_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S9_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S9_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S9( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S9_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S9_MASK ) + +#define GR740_IOPLL_DRVSTR1_S8_SHIFT 16 +#define GR740_IOPLL_DRVSTR1_S8_MASK 0x30000U +#define GR740_IOPLL_DRVSTR1_S8_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S8_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S8_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S8_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S8_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S8_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S8( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S8_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S8_MASK ) + +#define GR740_IOPLL_DRVSTR1_S7_SHIFT 14 +#define GR740_IOPLL_DRVSTR1_S7_MASK 0xc000U +#define GR740_IOPLL_DRVSTR1_S7_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S7_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S7_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S7_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S7_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S7_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S7( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S7_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S7_MASK ) + +#define GR740_IOPLL_DRVSTR1_S6_SHIFT 12 +#define GR740_IOPLL_DRVSTR1_S6_MASK 0x3000U +#define GR740_IOPLL_DRVSTR1_S6_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S6_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S6_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S6_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S6_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S6_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S6( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S6_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S6_MASK ) + +#define GR740_IOPLL_DRVSTR1_S5_SHIFT 10 +#define GR740_IOPLL_DRVSTR1_S5_MASK 0xc00U +#define GR740_IOPLL_DRVSTR1_S5_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S5_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S5_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S5_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S5_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S5_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S5( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S5_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S5_MASK ) + +#define GR740_IOPLL_DRVSTR1_S4_SHIFT 8 +#define GR740_IOPLL_DRVSTR1_S4_MASK 0x300U +#define GR740_IOPLL_DRVSTR1_S4_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S4_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S4_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S4_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S4_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S4_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S4( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S4_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S4_MASK ) + +#define GR740_IOPLL_DRVSTR1_S3_SHIFT 6 +#define GR740_IOPLL_DRVSTR1_S3_MASK 0xc0U +#define GR740_IOPLL_DRVSTR1_S3_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S3_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S3_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S3_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S3_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S3_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S3( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S3_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S3_MASK ) + +#define GR740_IOPLL_DRVSTR1_S2_SHIFT 4 +#define GR740_IOPLL_DRVSTR1_S2_MASK 0x30U +#define GR740_IOPLL_DRVSTR1_S2_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S2_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S2_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S2_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S2_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S2_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S2( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S2_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S2_MASK ) + +#define GR740_IOPLL_DRVSTR1_S1_SHIFT 2 +#define GR740_IOPLL_DRVSTR1_S1_MASK 0xcU +#define GR740_IOPLL_DRVSTR1_S1_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S1_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S1_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S1_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S1_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S1_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S1( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S1_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S1_MASK ) + +#define GR740_IOPLL_DRVSTR1_S0_SHIFT 0 +#define GR740_IOPLL_DRVSTR1_S0_MASK 0x3U +#define GR740_IOPLL_DRVSTR1_S0_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR1_S0_MASK ) >> \ + GR740_IOPLL_DRVSTR1_S0_SHIFT ) +#define GR740_IOPLL_DRVSTR1_S0_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR1_S0_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S0_MASK ) ) +#define GR740_IOPLL_DRVSTR1_S0( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR1_S0_SHIFT ) & \ + GR740_IOPLL_DRVSTR1_S0_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLDRVSTR2 \ + * Drive strength configuration register 2 (DRVSTR2) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_DRVSTR2_S19_SHIFT 18 +#define GR740_IOPLL_DRVSTR2_S19_MASK 0xc0000U +#define GR740_IOPLL_DRVSTR2_S19_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S19_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S19_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S19_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S19_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S19_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S19_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S19( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S19_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S19_MASK ) + +#define GR740_IOPLL_DRVSTR2_S18_SHIFT 16 +#define GR740_IOPLL_DRVSTR2_S18_MASK 0x30000U +#define GR740_IOPLL_DRVSTR2_S18_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S18_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S18_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S18_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S18_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S18_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S18_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S18( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S18_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S18_MASK ) + +#define GR740_IOPLL_DRVSTR2_S17_SHIFT 14 +#define GR740_IOPLL_DRVSTR2_S17_MASK 0xc000U +#define GR740_IOPLL_DRVSTR2_S17_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S17_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S17_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S17_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S17_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S17_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S17_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S17( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S17_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S17_MASK ) + +#define GR740_IOPLL_DRVSTR2_S16_SHIFT 12 +#define GR740_IOPLL_DRVSTR2_S16_MASK 0x3000U +#define GR740_IOPLL_DRVSTR2_S16_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S16_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S16_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S16_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S16_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S16_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S16_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S16( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S16_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S16_MASK ) + +#define GR740_IOPLL_DRVSTR2_S15_SHIFT 10 +#define GR740_IOPLL_DRVSTR2_S15_MASK 0xc00U +#define GR740_IOPLL_DRVSTR2_S15_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S15_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S15_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S15_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S15_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S15_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S15_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S15( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S15_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S15_MASK ) + +#define GR740_IOPLL_DRVSTR2_S14_SHIFT 8 +#define GR740_IOPLL_DRVSTR2_S14_MASK 0x300U +#define GR740_IOPLL_DRVSTR2_S14_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S14_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S14_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S14_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S14_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S14_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S14_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S14( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S14_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S14_MASK ) + +#define GR740_IOPLL_DRVSTR2_S13_SHIFT 6 +#define GR740_IOPLL_DRVSTR2_S13_MASK 0xc0U +#define GR740_IOPLL_DRVSTR2_S13_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S13_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S13_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S13_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S13_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S13_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S13_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S13( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S13_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S13_MASK ) + +#define GR740_IOPLL_DRVSTR2_S12_SHIFT 4 +#define GR740_IOPLL_DRVSTR2_S12_MASK 0x30U +#define GR740_IOPLL_DRVSTR2_S12_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S12_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S12_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S12_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S12_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S12_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S12_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S12( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S12_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S12_MASK ) + +#define GR740_IOPLL_DRVSTR2_S11_SHIFT 2 +#define GR740_IOPLL_DRVSTR2_S11_MASK 0xcU +#define GR740_IOPLL_DRVSTR2_S11_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S11_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S11_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S11_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S11_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S11_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S11_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S11( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S11_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S11_MASK ) + +#define GR740_IOPLL_DRVSTR2_S10_SHIFT 0 +#define GR740_IOPLL_DRVSTR2_S10_MASK 0x3U +#define GR740_IOPLL_DRVSTR2_S10_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_DRVSTR2_S10_MASK ) >> \ + GR740_IOPLL_DRVSTR2_S10_SHIFT ) +#define GR740_IOPLL_DRVSTR2_S10_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_DRVSTR2_S10_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S10_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S10_MASK ) ) +#define GR740_IOPLL_DRVSTR2_S10( _val ) \ + ( ( ( _val ) << GR740_IOPLL_DRVSTR2_S10_SHIFT ) & \ + GR740_IOPLL_DRVSTR2_S10_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740IOPLLLOCKDOWN \ + * Configuration lockdown register (LOCKDOWN) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT 16 +#define GR740_IOPLL_LOCKDOWN_PERMANENT_MASK 0xff0000U +#define GR740_IOPLL_LOCKDOWN_PERMANENT_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) >> \ + GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) +#define GR740_IOPLL_LOCKDOWN_PERMANENT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) & \ + GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) ) +#define GR740_IOPLL_LOCKDOWN_PERMANENT( _val ) \ + ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_PERMANENT_SHIFT ) & \ + GR740_IOPLL_LOCKDOWN_PERMANENT_MASK ) + +#define GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT 0 +#define GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK 0xffU +#define GR740_IOPLL_LOCKDOWN_REVOCABLE_GET( _reg ) \ + ( ( ( _reg ) & GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) >> \ + GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) +#define GR740_IOPLL_LOCKDOWN_REVOCABLE_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) | \ + ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) & \ + GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) ) +#define GR740_IOPLL_LOCKDOWN_REVOCABLE( _val ) \ + ( ( ( _val ) << GR740_IOPLL_LOCKDOWN_REVOCABLE_SHIFT ) & \ + GR740_IOPLL_LOCKDOWN_REVOCABLE_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GR740 I/0 and PLL Configuration register + * block memory map. + */ +typedef struct gr740_iopll { + /** + * @brief See @ref RTEMSBSPsGR740IOPLLFTMFUNC. + */ + uint32_t ftmfunc; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLALTFUNC. + */ + uint32_t altfunc; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLLVDSMCLK. + */ + uint32_t lvdsmclk; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLPLLNEWCFG. + */ + uint32_t pllnewcfg; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLPLLRECFG. + */ + uint32_t pllrecfg; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLPLLCURCFG. + */ + uint32_t pllcurcfg; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLDRVSTR1. + */ + uint32_t drvstr1; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLDRVSTR2. + */ + uint32_t drvstr2; + + /** + * @brief See @ref RTEMSBSPsGR740IOPLLLOCKDOWN. + */ + uint32_t lockdown; +} gr740_iopll; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_GR740_IOPLL_REGS_H */ diff --git a/bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h b/bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h new file mode 100644 index 0000000000..54f33adaee --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/gr740-thsens-regs.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsGR740ThSens + * + * @brief This header file defines the GR740 Temperatur Sensor Controller + * register block interface. + */ + +/* + * Copyright (C) 2021, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-thsens-header */ + +#ifndef _BSP_GR740_THSENS_REGS_H +#define _BSP_GR740_THSENS_REGS_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/bsp/sparc/leon3/if/gr740-thsens */ + +/** + * @defgroup RTEMSBSPsGR740ThSens GR740 Temperatur Sensor Controller + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This group contains the GR740 Temperatur Sensor Controller + * interfaces. + * + * @{ + */ + +/** + * @defgroup RTEMSBSPsGR740ThSensCTRL Control register (CTRL) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_THSENS_CTRL_DIV_SHIFT 16 +#define GR740_THSENS_CTRL_DIV_MASK 0x3ff0000U +#define GR740_THSENS_CTRL_DIV_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_CTRL_DIV_MASK ) >> \ + GR740_THSENS_CTRL_DIV_SHIFT ) +#define GR740_THSENS_CTRL_DIV_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_CTRL_DIV_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_CTRL_DIV_SHIFT ) & \ + GR740_THSENS_CTRL_DIV_MASK ) ) +#define GR740_THSENS_CTRL_DIV( _val ) \ + ( ( ( _val ) << GR740_THSENS_CTRL_DIV_SHIFT ) & \ + GR740_THSENS_CTRL_DIV_MASK ) + +#define GR740_THSENS_CTRL_ALEN 0x100U + +#define GR740_THSENS_CTRL_PDN 0x80U + +#define GR740_THSENS_CTRL_DCORRECT_SHIFT 2 +#define GR740_THSENS_CTRL_DCORRECT_MASK 0x7cU +#define GR740_THSENS_CTRL_DCORRECT_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_CTRL_DCORRECT_MASK ) >> \ + GR740_THSENS_CTRL_DCORRECT_SHIFT ) +#define GR740_THSENS_CTRL_DCORRECT_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_CTRL_DCORRECT_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_CTRL_DCORRECT_SHIFT ) & \ + GR740_THSENS_CTRL_DCORRECT_MASK ) ) +#define GR740_THSENS_CTRL_DCORRECT( _val ) \ + ( ( ( _val ) << GR740_THSENS_CTRL_DCORRECT_SHIFT ) & \ + GR740_THSENS_CTRL_DCORRECT_MASK ) + +#define GR740_THSENS_CTRL_SRSTN 0x2U + +#define GR740_THSENS_CTRL_CLKEN 0x1U + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740ThSensSTATUS Status register (STATUS) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_THSENS_STATUS_MAX_SHIFT 24 +#define GR740_THSENS_STATUS_MAX_MASK 0x7f000000U +#define GR740_THSENS_STATUS_MAX_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_STATUS_MAX_MASK ) >> \ + GR740_THSENS_STATUS_MAX_SHIFT ) +#define GR740_THSENS_STATUS_MAX_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_STATUS_MAX_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_STATUS_MAX_SHIFT ) & \ + GR740_THSENS_STATUS_MAX_MASK ) ) +#define GR740_THSENS_STATUS_MAX( _val ) \ + ( ( ( _val ) << GR740_THSENS_STATUS_MAX_SHIFT ) & \ + GR740_THSENS_STATUS_MAX_MASK ) + +#define GR740_THSENS_STATUS_MIN_SHIFT 16 +#define GR740_THSENS_STATUS_MIN_MASK 0x7f0000U +#define GR740_THSENS_STATUS_MIN_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_STATUS_MIN_MASK ) >> \ + GR740_THSENS_STATUS_MIN_SHIFT ) +#define GR740_THSENS_STATUS_MIN_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_STATUS_MIN_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_STATUS_MIN_SHIFT ) & \ + GR740_THSENS_STATUS_MIN_MASK ) ) +#define GR740_THSENS_STATUS_MIN( _val ) \ + ( ( ( _val ) << GR740_THSENS_STATUS_MIN_SHIFT ) & \ + GR740_THSENS_STATUS_MIN_MASK ) + +#define GR740_THSENS_STATUS_SCLK 0x8000U + +#define GR740_THSENS_STATUS_WE 0x400U + +#define GR740_THSENS_STATUS_UPD 0x200U + +#define GR740_THSENS_STATUS_ALACT 0x100U + +#define GR740_THSENS_STATUS_DATA_SHIFT 0 +#define GR740_THSENS_STATUS_DATA_MASK 0x7fU +#define GR740_THSENS_STATUS_DATA_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_STATUS_DATA_MASK ) >> \ + GR740_THSENS_STATUS_DATA_SHIFT ) +#define GR740_THSENS_STATUS_DATA_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_STATUS_DATA_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_STATUS_DATA_SHIFT ) & \ + GR740_THSENS_STATUS_DATA_MASK ) ) +#define GR740_THSENS_STATUS_DATA( _val ) \ + ( ( ( _val ) << GR740_THSENS_STATUS_DATA_SHIFT ) & \ + GR740_THSENS_STATUS_DATA_MASK ) + +/** @} */ + +/** + * @defgroup RTEMSBSPsGR740ThSensTHRES Threshold register (THRES) + * + * @brief This group contains register bit definitions. + * + * @{ + */ + +#define GR740_THSENS_THRES_THRES_SHIFT 0 +#define GR740_THSENS_THRES_THRES_MASK 0x7fU +#define GR740_THSENS_THRES_THRES_GET( _reg ) \ + ( ( ( _reg ) & GR740_THSENS_THRES_THRES_MASK ) >> \ + GR740_THSENS_THRES_THRES_SHIFT ) +#define GR740_THSENS_THRES_THRES_SET( _reg, _val ) \ + ( ( ( _reg ) & ~GR740_THSENS_THRES_THRES_MASK ) | \ + ( ( ( _val ) << GR740_THSENS_THRES_THRES_SHIFT ) & \ + GR740_THSENS_THRES_THRES_MASK ) ) +#define GR740_THSENS_THRES_THRES( _val ) \ + ( ( ( _val ) << GR740_THSENS_THRES_THRES_SHIFT ) & \ + GR740_THSENS_THRES_THRES_MASK ) + +/** @} */ + +/** + * @brief This structure defines the GR740 Temperatur Sensor Controller + * register block memory map. + */ +typedef struct gr740_thsens { + /** + * @brief See @ref RTEMSBSPsGR740ThSensCTRL. + */ + uint32_t ctrl; + + /** + * @brief See @ref RTEMSBSPsGR740ThSensSTATUS. + */ + uint32_t status; + + /** + * @brief See @ref RTEMSBSPsGR740ThSensTHRES. + */ + uint32_t thres; +} gr740_thsens; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_GR740_THSENS_REGS_H */ diff --git a/bsps/sparc/leon3/include/bsp/irq.h b/bsps/sparc/leon3/include/bsp/irq.h index 967086f8eb..dd6fd91aa1 100644 --- a/bsps/sparc/leon3/include/bsp/irq.h +++ b/bsps/sparc/leon3/include/bsp/irq.h @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file - * @ingroup sparc_leon3 + * @ingroup RTEMSBSPsSPARCLEON3 * @brief LEON3 generic shared IRQ setup * * Based on libbsp/shared/include/irq.h. @@ -10,16 +12,32 @@ * Copyright (c) 2012. * Aeroflex Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef LIBBSP_LEON3_IRQ_CONFIG_H #define LIBBSP_LEON3_IRQ_CONFIG_H -#include <leon.h> -#include <rtems/score/processormask.h> +#include <rtems.h> #define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ #define BSP_INTERRUPT_VECTOR_MAX_EXT 31 /* Extended IRQ controller */ @@ -29,14 +47,4 @@ /* The check is different depending on IRQ controller, runtime detected */ #define BSP_INTERRUPT_CUSTOM_VALID_VECTOR -rtems_status_code bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -rtems_status_code bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); - #endif /* LIBBSP_LEON3_IRQ_CONFIG_H */ diff --git a/bsps/sparc/leon3/include/bsp/irqimpl.h b/bsps/sparc/leon3/include/bsp/irqimpl.h new file mode 100644 index 0000000000..9a9eae51f7 --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/irqimpl.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This header file provides interfaces used by the interrupt support + * implementation. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H +#define LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H + +#include <rtems.h> +#include <grlib/irqamp-regs.h> +#include <grlib/io.h> + +#include <bspopts.h> + +struct ambapp_dev; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup RTEMSBSPsSPARCLEON3 + * + * @{ + */ + +/** + * @brief This object provides the index of the boot processor. + * + * This object should be read-only after initialization. + */ +extern uint32_t LEON3_Cpu_Index; + +/** + * @brief This lock serializes the interrupt controller access. + */ +extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; + +/** + * @brief Acquires the interrupt controller lock. + * + * @param[out] _lock_context is the lock context. + */ +#define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \ + rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context ) + +/** + * @brief Releases the interrupt controller lock. + * + * @param[in, out] _lock_context is the lock context. + */ +#define LEON3_IRQCTRL_RELEASE( _lock_context ) \ + rtems_interrupt_lock_release( &LEON3_IrqCtrl_Lock, _lock_context ) + +/** + * @brief This pointer provides the IRQ(A)MP register block address. + */ +#if defined(LEON3_IRQAMP_BASE) +#define LEON3_IrqCtrl_Regs ((irqamp *) LEON3_IRQAMP_BASE) +#else +extern irqamp *LEON3_IrqCtrl_Regs; + +/** + * @brief This pointer provides the IRQ(A)MP device information block. + */ +extern struct ambapp_dev *LEON3_IrqCtrl_Adev; +#endif + +/** + * @brief This object provides the interrupt number used to multiplex extended + * interrupts or is zero if no extended interrupts are available. + * + * This object should be read-only after initialization. + */ +#if defined(LEON3_IRQAMP_EXTENDED_INTERRUPT) +#define LEON3_IrqCtrl_EIrq LEON3_IRQAMP_EXTENDED_INTERRUPT +#else +extern uint32_t LEON3_IrqCtrl_EIrq; +#endif + +/** + * @brief Initializes the interrupt controller for the boot processor. + * + * @param[in, out] regs is the IRQ(A)MP register block address. + */ +void leon3_ext_irq_init( irqamp *regs ); + +/** + * @brief Acknowledges and maps extended interrupts if this feature is + * available and the interrupt for extended interrupts is present. + * + * @param irq is the standard interrupt number. + */ +static inline uint32_t bsp_irq_fixup( uint32_t irq ) +{ + uint32_t eirq; + uint32_t cpu_self; + + if ( irq != LEON3_IrqCtrl_EIrq ) { + return irq; + } + + cpu_self = _LEON3_Get_current_processor(); + eirq = grlib_load_32( &LEON3_IrqCtrl_Regs->pextack[ cpu_self ] ); + eirq = IRQAMP_PEXTACK_EID_4_0_GET( eirq ); + + if ( eirq < 16 ) { + return irq; + } + + return eirq; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_SPARC_LEON3_BSP_IRQIMPL_H */ diff --git a/bsps/sparc/leon3/include/bsp/leon3.h b/bsps/sparc/leon3/include/bsp/leon3.h new file mode 100644 index 0000000000..650e2db744 --- /dev/null +++ b/bsps/sparc/leon3/include/bsp/leon3.h @@ -0,0 +1,387 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 + * + * @brief This header file provides interfaces used by the BSP implementation. + */ + +/* + * Copyright (C) 2014, 2023 embedded brains GmbH & Co. KG + * + * Copyright (C) 2015 Cobham Gaisler AB + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_SPARC_LEON3_BSP_LEON3_H +#define LIBBSP_SPARC_LEON3_BSP_LEON3_H + +#include <grlib/apbuart-regs.h> +#include <grlib/gptimer-regs.h> + +#include <bspopts.h> +#include <bsp/irqimpl.h> + +#if !defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER) +#include <grlib/ambapp.h> +#endif + +#include <sys/timetc.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup RTEMSBSPsSPARCLEON3 + * + * @{ + */ + +/** + * @brief Sets %asr19 to zero to enter the power-down mode of the processor in + * an infinite loop. + */ +RTEMS_NO_RETURN void leon3_power_down_loop( void ); + +/** + * @brief This constant represents the flush instruction cache flag of the LEON + * cache control register. + */ +#define LEON3_REG_CACHE_CTRL_FI 0x00200000U + +/** + * @brief This constant represents the data cache snooping enable flag of the + * LEON cache control register. + */ +#define LEON3_REG_CACHE_CTRL_DS 0x00800000U + +/** + * @brief Sets the ASI 0x2 system register value. + * + * @param addr is the address of the ASI 0x2 system register. + * + * @param val is the value to set. + */ +static inline void leon3_set_system_register( uint32_t addr, uint32_t val ) +{ + __asm__ volatile( + "sta %1, [%0] 2" + : + : "r" ( addr ), "r" ( val ) + ); +} + +/** + * @brief Gets the ASI 0x2 system register value. + * + * @param addr is the address of the ASI 0x2 system register. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_get_system_register( uint32_t addr ) +{ + uint32_t val; + + __asm__ volatile( + "lda [%1] 2, %0" + : "=r" ( val ) + : "r" ( addr ) + ); + + return val; +} + +/** + * @brief Sets the LEON cache control register value. + * + * @param val is the value to set. + */ +static inline void leon3_set_cache_control_register( uint32_t val ) +{ + leon3_set_system_register( 0x0, val ); +} + +/** + * @brief Gets the LEON cache control register value. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_get_cache_control_register( void ) +{ + return leon3_get_system_register( 0x0 ); +} + +/** + * @brief Checks if the data cache snooping is enabled. + * + * @return Returns true, if the data cache snooping is enabled, otherwise + * false. + */ +static inline bool leon3_data_cache_snooping_enabled( void ) +{ + return ( leon3_get_cache_control_register() & LEON3_REG_CACHE_CTRL_DS ) != 0; +} + +/** + * @brief Gets the LEON instruction cache configuration register value. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_get_inst_cache_config_register( void ) +{ + return leon3_get_system_register( 0x8 ); +} + +/** + * @brief Gets the LEON data cache configuration register value. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_get_data_cache_config_register( void ) +{ + return leon3_get_system_register( 0xc ); +} + +/** + * @brief Gets the processor count. + * + * @param[in] regs is the IRQ(A)MP register block address. + * + * @return Returns the processor count. + */ +static inline uint32_t leon3_get_cpu_count( const irqamp *regs ) +{ + return IRQAMP_MPSTAT_NCPU_GET( grlib_load_32( ®s->mpstat ) ) + 1; +} + +#if !defined(LEON3_GPTIMER_BASE) +/** + * @brief This object lets the user override which on-chip GPTIMER core will be + * used for system clock timer. + * + * This controls which timer core will be accociated with LEON3_Timer_Regs + * registers base address. This value will by destroyed during initialization. + * + * * 0 = Default configuration. GPTIMER[0] + * + * * 1 = GPTIMER[1] + * + * * 2 = GPTIMER[2] + * + * * ... + */ +extern int leon3_timer_core_index; + +/** + * @brief This object lets the user override system clock timer prescaler. + * + * This affects all timer instances on the system clock timer core determined + * by ::leon3_timer_core_index. + * + * * 0 = Default configuration. Use bootloader configured value. + * + * * N = Prescaler is set to N. N must not be less that number of timers. + * + * * 8 = Prescaler is set to 8 (the fastest prescaler possible on all HW) + * + * * ... + */ +extern unsigned int leon3_timer_prescaler; +#endif + +/** + * @brief This constant defines the index of the GPTIMER timer used by the + * clock driver. + */ +#if defined(RTEMS_MULTIPROCESSING) +#define LEON3_CLOCK_INDEX \ + ( leon3_timer_core_index != 0 ? 0 : 2 * LEON3_Cpu_Index ) +#else +#define LEON3_CLOCK_INDEX 0 +#endif + +/** + * @brief This constant defines the index of the GPTIMER timer used by the + * CPU counter if the CPU counter uses the GPTIMER. + */ +#define LEON3_COUNTER_GPTIMER_INDEX ( LEON3_CLOCK_INDEX + 1 ) + +/** + * @brief This constant defines the frequency set by the boot loader of the + * first GPTIMER instance. + * + * We assume that a boot loader (usually GRMON) initialized the GPTIMER 0 to + * run with 1MHz. This is used to determine all clock frequencies of the PnP + * devices. See also ambapp_freq_init() and ambapp_freq_get(). + */ +#define LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER 1000000 + +/** + * @brief This pointer provides the GPTIMER register block address. + */ +#if defined(LEON3_GPTIMER_BASE) +#define LEON3_Timer_Regs ((gptimer *) LEON3_GPTIMER_BASE) +#else +extern gptimer *LEON3_Timer_Regs; + +/** + * @brief This pointer provides the GPTIMER device information block. + */ +extern struct ambapp_dev *LEON3_Timer_Adev; +#endif + +/** + * @brief Gets the processor local bus frequency in Hz. + * + * @return Returns the frequency. + */ +static inline uint32_t leon3_processor_local_bus_frequency( void ) +{ +#if defined(LEON3_PLB_FREQUENCY_DEFINED_BY_GPTIMER) + return ( grlib_load_32( &LEON3_Timer_Regs->sreload ) + 1 ) * + LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER; +#else + /* + * For simplicity, assume that the interrupt controller uses the processor + * clock. This is at least true on the GR740. + */ + return ambapp_freq_get( ambapp_plb(), LEON3_IrqCtrl_Adev ); +#endif +} + +/** + * @brief Gets the LEON up-counter low register (%ASR23) value. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_up_counter_low( void ) +{ + uint32_t asr23; + + __asm__ volatile ( + "mov %%asr23, %0" + : "=&r" (asr23) + ); + + return asr23; +} + +/** + * @brief Gets the LEON up-counter high register (%ASR22) value. + * + * @return Returns the register value. + */ +static inline uint32_t leon3_up_counter_high(void) +{ + uint32_t asr22; + + __asm__ volatile ( + "mov %%asr22, %0" + : "=&r" (asr22) + ); + + return asr22; +} + +/** + * @brief Enables the LEON up-counter. + */ +static inline void leon3_up_counter_enable( void ) +{ + __asm__ volatile ( + "mov %g0, %asr22" + ); +} + +#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER) +/** + * @brief Checks if the LEON up-counter is available. + * + * The LEON up-counter must have been enabled. + * + * @return Returns true, if the LEON up-counter is available, otherwise false. + */ +static inline bool leon3_up_counter_is_available( void ) +{ + return leon3_up_counter_low() != leon3_up_counter_low(); +} +#endif + +/** + * @brief Gets the LEON up-counter frequency in Hz. + * + * @return Returns the frequency. + */ +static inline uint32_t leon3_up_counter_frequency( void ) +{ + return leon3_processor_local_bus_frequency(); +} + +/** + * @brief This pointer provides the debug APBUART register block address. + */ +#if defined(LEON3_APBUART_BASE) +#define leon3_debug_uart ((struct apbuart *) LEON3_APBUART_BASE) +#else +extern apbuart *leon3_debug_uart; +#endif + +/** + * @brief Represents the LEON3-specific timecounter. + */ +typedef struct { + /** + * @brief This member contains the base timecounter. + */ + struct timecounter base; + +#if !defined(LEON3_HAS_ASR_22_23_UP_COUNTER) + /** + * @brief This member provides a software fall-back counter. + */ + uint32_t software_counter; + + /** + * @brief This member may reference a hardware counter register. + */ + volatile uint32_t *counter_register; +#endif +} leon3_timecounter; + +/** + * @brief Provides the LEON3-specific timecounter. + * + * It is also used by the CPU counter implementation. + */ +extern leon3_timecounter leon3_timecounter_instance; + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_SPARC_LEON3_BSP_LEON3_H */ diff --git a/bsps/sparc/leon3/include/bsp/watchdog.h b/bsps/sparc/leon3/include/bsp/watchdog.h index 3c63be2a8f..8bffd3c95e 100644 --- a/bsps/sparc/leon3/include/bsp/watchdog.h +++ b/bsps/sparc/leon3/include/bsp/watchdog.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* watchdog.h * * The LEON3 BSP timer watch-dog interface @@ -5,9 +7,26 @@ * COPYRIGHT (c) 2012. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __WATCHDOG_H__ diff --git a/bsps/sparc/leon3/include/leon.h b/bsps/sparc/leon3/include/leon.h index 5fadb08052..28ba59ff21 100644 --- a/bsps/sparc/leon3/include/leon.h +++ b/bsps/sparc/leon3/include/leon.h @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file - * @ingroup sparc_leon3 + * @ingroup RTEMSBSPsSPARCLEON3 * @brief LEON3 BSP data types and macros */ @@ -15,9 +17,26 @@ * COPYRIGHT (c) 2004. * Gaisler Research. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _INCLUDE_LEON_h @@ -25,6 +44,8 @@ #include <rtems.h> #include <amba.h> +#include <grlib/io.h> +#include <bsp/leon3.h> #ifdef __cplusplus extern "C" { @@ -121,41 +142,6 @@ extern "C" { #define LEON_REG_UART_CTRL_FA 0x80000000 /* FIFO Available */ #define LEON_REG_UART_CTRL_FA_BIT 31 -/* - * The following defines the bits in the LEON Cache Control Register. - */ -#define LEON3_REG_CACHE_CTRL_FI 0x00200000 /* Flush instruction cache */ -#define LEON3_REG_CACHE_CTRL_DS 0x00800000 /* Data cache snooping */ - -/* LEON3 Interrupt Controller */ -extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; -extern struct ambapp_dev *LEON3_IrqCtrl_Adev; - -/* LEON3 GP Timer */ -extern volatile struct gptimer_regs *LEON3_Timer_Regs; -extern struct ambapp_dev *LEON3_Timer_Adev; - -/* LEON3 CPU Index of boot CPU */ -extern uint32_t LEON3_Cpu_Index; - -/* The external IRQ number, -1 if not external interrupts */ -extern int LEON3_IrqCtrl_EIrq; - -static __inline__ int bsp_irq_fixup(int irq) -{ - int eirq, cpu; - - if (LEON3_IrqCtrl_EIrq != 0 && irq == LEON3_IrqCtrl_EIrq) { - /* Get interrupt number from IRQ controller */ - cpu = _LEON3_Get_current_processor(); - eirq = LEON3_IrqCtrl_Regs->intid[cpu] & 0x1f; - if (eirq & 0x10) - irq = eirq; - } - - return irq; -} - /* Macros used for manipulating bits in LEON3 GP Timer Control Register */ #define LEON3_IRQMPSTATUS_CPUNR 28 @@ -174,30 +160,21 @@ static __inline__ int bsp_irq_fixup(int irq) * store the result back are vulnerable. */ -extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; - -#define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \ - rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context ) - -#define LEON3_IRQCTRL_RELEASE( _lock_context ) \ - rtems_interrupt_lock_release( &LEON3_IrqCtrl_Lock, _lock_context ) - #define LEON_Clear_interrupt( _source ) \ - do { \ - LEON3_IrqCtrl_Regs->iclear = (1U << (_source)); \ - } while (0) + grlib_store_32(&LEON3_IrqCtrl_Regs->iclear, 1U << (_source)) #define LEON_Force_interrupt( _source ) \ - do { \ - LEON3_IrqCtrl_Regs->iforce = (1U << (_source)); \ - } while (0) + grlib_store_32(&LEON3_IrqCtrl_Regs->iforce0, 1U << (_source)) #define LEON_Enable_interrupt_broadcast( _source ) \ do { \ rtems_interrupt_lock_context _lock_context; \ uint32_t _mask = 1U << ( _source ); \ + uint32_t _brdcst; \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->bcast |= _mask; \ + _brdcst = grlib_load_32(&LEON3_IrqCtrl_Regs->brdcst); \ + _brdcst |= _mask; \ + grlib_store_32(&LEON3_IrqCtrl_Regs->brdcst, _brdcst); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ } while (0) @@ -205,30 +182,39 @@ extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; do { \ rtems_interrupt_lock_context _lock_context; \ uint32_t _mask = 1U << ( _source ); \ + uint32_t _brdcst; \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->bcast &= ~_mask; \ + _brdcst = grlib_load_32(&LEON3_IrqCtrl_Regs->brdcst); \ + _brdcst &= ~_mask; \ + grlib_store_32(&LEON3_IrqCtrl_Regs->brdcst, _brdcst); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ } while (0) #define LEON_Is_interrupt_pending( _source ) \ - (LEON3_IrqCtrl_Regs->ipend & (1U << (_source))) + (grlib_load_32(&LEON3_IrqCtrl_Regs->ipend) & (1U << (_source))) #define LEON_Cpu_Is_interrupt_masked( _source, _cpu ) \ - (!(LEON3_IrqCtrl_Regs->mask[_cpu] & (1U << (_source)))) + (!(grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu]) & (1U << (_source)))) #define LEON_Cpu_Mask_interrupt( _source, _cpu ) \ do { \ rtems_interrupt_lock_context _lock_context; \ + uint32_t _pimask; \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] &= ~(1U << (_source)); \ + _pimask = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \ + _pimask &= ~(1U << (_source)); \ + grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], _pimask); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ } while (0) #define LEON_Cpu_Unmask_interrupt( _source, _cpu ) \ do { \ rtems_interrupt_lock_context _lock_context; \ + uint32_t _pimask; \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] |= (1U << (_source)); \ + _pimask = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \ + _pimask |= 1U << (_source); \ + grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], _pimask); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ } while (0) @@ -237,8 +223,8 @@ extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; rtems_interrupt_lock_context _lock_context; \ uint32_t _mask = 1U << (_source); \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - (_previous) = LEON3_IrqCtrl_Regs->mask[_cpu]; \ - LEON3_IrqCtrl_Regs->mask[_cpu] = _previous & ~_mask; \ + (_previous) = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \ + grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], (_previous) & ~_mask); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ (_previous) &= _mask; \ } while (0) @@ -246,10 +232,12 @@ extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; #define LEON_Cpu_Restore_interrupt( _source, _previous, _cpu ) \ do { \ rtems_interrupt_lock_context _lock_context; \ - uint32_t _mask = 1U << (_source); \ + uint32_t _pimask; \ LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] = \ - (LEON3_IrqCtrl_Regs->mask[_cpu] & ~_mask) | (_previous); \ + _pimask = grlib_load_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ]); \ + _pimask &= ~(1U << (_source)); \ + _pimask |= _previous; \ + grlib_store_32(&LEON3_IrqCtrl_Regs->pimask[_cpu ], _pimask); \ LEON3_IRQCTRL_RELEASE( &_lock_context ); \ } while (0) @@ -324,26 +312,6 @@ extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; #define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 #define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 -#if defined(RTEMS_MULTIPROCESSING) - #define LEON3_CLOCK_INDEX \ - (rtems_configuration_get_user_multiprocessing_table() ? LEON3_Cpu_Index : 0) -#else - #define LEON3_CLOCK_INDEX 0 -#endif - -#if defined(RTEMS_SMP) -#define LEON3_COUNTER_GPTIMER_INDEX (LEON3_CLOCK_INDEX + 1) -#else -#define LEON3_COUNTER_GPTIMER_INDEX LEON3_CLOCK_INDEX -#endif - -/* - * We assume that a boot loader (usually GRMON) initialized the GPTIMER 0 to - * run with 1MHz. This is used to determine all clock frequencies of the PnP - * devices. See also ambapp_freq_init() and ambapp_freq_get(). - */ -#define LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER 1000000 - /* Load 32-bit word by forcing a cache-miss */ static inline unsigned int leon_r32_no_cache(uintptr_t addr) { @@ -361,6 +329,7 @@ static inline unsigned int leon_r32_no_cache(uintptr_t addr) */ extern int syscon_uart_index; +#if !defined(LEON3_APBUART_BASE) /* Let user override which on-chip APBUART will be debug UART * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... * 1 = APBUART[0] @@ -369,133 +338,7 @@ extern int syscon_uart_index; * ... */ extern int leon3_debug_uart_index; - -/* Let user override which on-chip TIMER core will be used for system clock - * timer. This controls which timer core will be accociated with - * LEON3_Timer_Regs registers base address. This value will by destroyed during - * initialization. - * 0 = Default configuration. GPTIMER[0] - * 1 = GPTIMER[1] - * 2 = GPTIMER[2] - * ... - */ -extern int leon3_timer_core_index; - -/* Let user override system clock timer prescaler. This affects all timer - * instances on the system clock timer core determined by - * leon3_timer_core_index. - * 0 = Default configuration. Use bootloader configured value. - * N = Prescaler is set to N. N must not be less that number of timers. - * 8 = Prescaler is set to 8 (the fastest prescaler possible on all HW) - * ... - */ -extern unsigned int leon3_timer_prescaler; - -/* GRLIB extended IRQ controller register */ -void leon3_ext_irq_init(void); - -RTEMS_NO_RETURN void leon3_power_down_loop(void); - -static inline uint32_t leon3_get_cpu_count( - volatile struct irqmp_regs *irqmp -) -{ - uint32_t mpstat = irqmp->mpstat; - - return ((mpstat >> LEON3_IRQMPSTATUS_CPUNR) & 0xf) + 1; -} - -static inline void leon3_set_system_register(uint32_t addr, uint32_t val) -{ - __asm__ volatile( - "sta %1, [%0] 2" - : - : "r" (addr), "r" (val) - ); -} - -static inline uint32_t leon3_get_system_register(uint32_t addr) -{ - uint32_t val; - - __asm__ volatile( - "lda [%1] 2, %0" - : "=r" (val) - : "r" (addr) - ); - - return val; -} - -static inline void leon3_set_cache_control_register(uint32_t val) -{ - leon3_set_system_register(0x0, val); -} - -static inline uint32_t leon3_get_cache_control_register(void) -{ - return leon3_get_system_register(0x0); -} - -static inline bool leon3_data_cache_snooping_enabled(void) -{ - return leon3_get_cache_control_register() & LEON3_REG_CACHE_CTRL_DS; -} - -static inline uint32_t leon3_get_inst_cache_config_register(void) -{ - return leon3_get_system_register(0x8); -} - -static inline uint32_t leon3_get_data_cache_config_register(void) -{ - return leon3_get_system_register(0xc); -} - -static inline uint32_t leon3_up_counter_low(void) -{ - uint32_t asr23; - - __asm__ volatile ( - "mov %%asr23, %0" - : "=&r" (asr23) - ); - - return asr23; -} - -static inline uint32_t leon3_up_counter_high(void) -{ - uint32_t asr22; - - __asm__ volatile ( - "mov %%asr22, %0" - : "=&r" (asr22) - ); - - return asr22; -} - -static inline void leon3_up_counter_enable(void) -{ - __asm__ volatile ( - "mov %g0, %asr22" - ); -} - -static inline bool leon3_up_counter_is_available(void) -{ - return leon3_up_counter_low() != leon3_up_counter_low(); -} - -static inline uint32_t leon3_up_counter_frequency(void) -{ - /* - * For simplicity, assume that the interrupt controller uses the processor - * clock. This is at least true on the GR740. - */ - return ambapp_freq_get(ambapp_plb(), LEON3_IrqCtrl_Adev); -} +#endif #endif /* !ASM */ diff --git a/bsps/sparc/leon3/include/tm27.h b/bsps/sparc/leon3/include/tm27.h index 99c79012bd..75004ef5ae 100644 --- a/bsps/sparc/leon3/include/tm27.h +++ b/bsps/sparc/leon3/include/tm27.h @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file - * @ingroup sparc_leon3 + * @ingroup RTEMSBSPsSPARCLEON3 * @brief Implementations for interrupt mechanisms for Time Test 27 */ @@ -8,9 +10,26 @@ * COPYRIGHT (c) 2006. * Aeroflex Gaisler AB. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_TMTEST27 @@ -21,7 +40,7 @@ #define __tm27_h #include <bsp.h> -#include <bsp/irq.h> +#include <bsp/irq-generic.h> #if defined(RTEMS_SMP) #include <rtems/score/smpimpl.h> @@ -47,6 +66,8 @@ #define MUST_WAIT_FOR_INTERRUPT 1 +#define TM27_USE_VECTOR_HANDLER + #define Install_tm27_vector( handler ) \ set_vector( (handler), TEST_VECTOR, 1 ); @@ -68,10 +89,9 @@ extern uint32_t Interrupt_nest; #define TEST_INTERRUPT_SOURCE 5 #define TEST_INTERRUPT_SOURCE2 6 #define MUST_WAIT_FOR_INTERRUPT 1 +#define TM27_INTERRUPT_VECTOR_DEFAULT TEST_INTERRUPT_SOURCE -static inline void Install_tm27_vector( - void ( *handler )( rtems_vector_number ) -) +static inline void Install_tm27_vector( rtems_interrupt_handler handler ) { static rtems_interrupt_entry entry_low; static rtems_interrupt_entry entry_high; @@ -89,7 +109,7 @@ static inline void Install_tm27_vector( rtems_interrupt_entry_initialize( &entry_low, - (rtems_interrupt_handler) handler, + handler, NULL, "tm27 low" ); @@ -100,7 +120,7 @@ static inline void Install_tm27_vector( ); rtems_interrupt_entry_initialize( &entry_high, - (rtems_interrupt_handler) handler, + handler, NULL, "tm27 high" ); |