diff options
Diffstat (limited to 'bsps/sparc/include')
| -rw-r--r-- | bsps/sparc/include/bsp/gnatcommon.h | 15 | ||||
| -rw-r--r-- | bsps/sparc/include/bsp/gr_leon4_n2x.h | 35 | ||||
| -rw-r--r-- | bsps/sparc/include/bsp/sparc-counter.h | 89 | ||||
| -rw-r--r-- | bsps/sparc/include/drvmgr/leon2_amba_bus.h | 35 | ||||
| -rw-r--r-- | bsps/sparc/include/grlib/io.h | 210 |
5 files changed, 376 insertions, 8 deletions
diff --git a/bsps/sparc/include/bsp/gnatcommon.h b/bsps/sparc/include/bsp/gnatcommon.h index 1a04449293..40e8829bb9 100644 --- a/bsps/sparc/include/bsp/gnatcommon.h +++ b/bsps/sparc/include/bsp/gnatcommon.h @@ -1,3 +1,18 @@ +/** + * @file + * + * @ingroup RTEMSImplGnat + * + * @brief This header file provides interfaces of the + * gnat/rtems interrupts and exception handling. + */ + +/** + * @defgroup RTEMSImplGnat GNAT/RTEMS interrupts and exception handling + * + * @ingroup RTEMSImpl + */ + #ifndef __GNATCOMMON_H #define __GNATCOMMON_H diff --git a/bsps/sparc/include/bsp/gr_leon4_n2x.h b/bsps/sparc/include/bsp/gr_leon4_n2x.h index 9a8041202a..97ca6d5dfb 100644 --- a/bsps/sparc/include/bsp/gr_leon4_n2x.h +++ b/bsps/sparc/include/bsp/gr_leon4_n2x.h @@ -1,11 +1,38 @@ -/* GR-CPCI-LEON4-N2X (NGFP) PCI Peripheral driver +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON3 * + * @brief This header file provides interfaces of the + * GR-CPCI-LEON4-N2X (NGFP) PCI Peripheral driver. + */ + +/* * COPYRIGHT (c) 2013. * Cobham Gaisler AB. * - * The license and distribution terms for this file may be - * found in found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. * * Configures the GR-CPIC-LEON4-N2X interface PCI board in peripheral * mode. This driver provides a AMBA PnP bus by using the general part diff --git a/bsps/sparc/include/bsp/sparc-counter.h b/bsps/sparc/include/bsp/sparc-counter.h new file mode 100644 index 0000000000..bc4f2220e7 --- /dev/null +++ b/bsps/sparc/include/bsp/sparc-counter.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCShared + * + * @brief This header file provides interfaces of a CPU counter implementation + * for SPARC BSPs. + */ + +/* + * Copyright (C) 2016, 2023 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _BSP_SPARC_COUNTER_H +#define _BSP_SPARC_COUNTER_H + +#include <rtems/score/cpu.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct timecounter; + +void _SPARC_Counter_at_tick_clock( void ); + +CPU_Counter_ticks _SPARC_Counter_read_default( void ); + +CPU_Counter_ticks _SPARC_Counter_read_clock_isr_disabled( void ); + +CPU_Counter_ticks _SPARC_Counter_read_clock( void ); + +uint32_t _SPARC_Get_timecount_clock( struct timecounter * ); + +typedef CPU_Counter_ticks ( *SPARC_Counter_read )( void ); + +/* + * The SPARC processors supported by RTEMS have no built-in CPU counter + * support. We have to use some hardware counter module for this purpose, for + * example the GPTIMER instance used by the clock driver. The BSP must provide + * an implementation of the CPU counter read function. This allows the use of + * dynamic hardware enumeration. + */ +typedef struct { + SPARC_Counter_read read_isr_disabled; + SPARC_Counter_read read; + volatile const CPU_Counter_ticks *counter_register; + volatile const uint32_t *pending_register; + uint32_t pending_mask; + CPU_Counter_ticks accumulated; + CPU_Counter_ticks interval; +} SPARC_Counter; + +extern SPARC_Counter _SPARC_Counter; + +#define SPARC_COUNTER_DEFINITION \ + SPARC_Counter _SPARC_Counter = { \ + .read_isr_disabled = _SPARC_Counter_read_default, \ + .read = _SPARC_Counter_read_default \ + } + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _BSP_SPARC_COUNTER_H */ diff --git a/bsps/sparc/include/drvmgr/leon2_amba_bus.h b/bsps/sparc/include/drvmgr/leon2_amba_bus.h index 1b35413c30..0dea2a9426 100644 --- a/bsps/sparc/include/drvmgr/leon2_amba_bus.h +++ b/bsps/sparc/include/drvmgr/leon2_amba_bus.h @@ -1,5 +1,15 @@ -/* LEON2 Hardcoded bus driver interface. +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsSPARCLEON2 * + * @brief This header file provides interfaces of the + * LEON2 Hardcoded bus driver. + */ + +/* * COPYRIGHT (c) 2008. * Cobham Gaisler AB. * @@ -11,9 +21,26 @@ * A Core is described by assigning a base register and * IRQ0..IRQ15 using the leon2_core structure. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __LEON2_AMBA_BUS_H__ diff --git a/bsps/sparc/include/grlib/io.h b/bsps/sparc/include/grlib/io.h new file mode 100644 index 0000000000..3035859d11 --- /dev/null +++ b/bsps/sparc/include/grlib/io.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief This header file defines the register load/store interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/bsp/sparc/if/grlib-io-header */ + +#ifndef _GRLIB_IO_H +#define _GRLIB_IO_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/bsp/sparc/if/grlib-io-group */ + +/** + * @defgroup RTEMSDeviceGRLIBIO Register Load/Store + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRLIB register load/store API. + */ + +/* Generated from spec:/bsp/sparc/if/grlib-load-08 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 8-bit register. + * + * @param address is the address of the memory-mapped unsigned 8-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint8_t grlib_load_8( const volatile uint8_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-load-16 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 16-bit register. + * + * @param address is the address of the memory-mapped unsigned 16-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint16_t grlib_load_16( const volatile uint16_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-load-32 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 32-bit register. + * + * @param address is the address of the memory-mapped unsigned 32-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint32_t grlib_load_32( const volatile uint32_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-load-64 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 64-bit register. + * + * @param address is the address of the memory-mapped unsigned 64-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint64_t grlib_load_64( const volatile uint64_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-08 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 8-bit register. + * + * @param address is the address of the memory-mapped unsigned 8-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_8( volatile uint8_t *address, uint8_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-16 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 16-bit register. + * + * @param address is the address of the memory-mapped unsigned 16-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_16( volatile uint16_t *address, uint16_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-32 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 32-bit register. + * + * @param address is the address of the memory-mapped unsigned 32-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_32( volatile uint32_t *address, uint32_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/sparc/if/grlib-store-64 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 64-bit register. + * + * @param address is the address of the memory-mapped unsigned 64-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_64( volatile uint64_t *address, uint64_t value ) +{ + *address = value; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_IO_H */ |