diff options
Diffstat (limited to 'bsps/sh/gensh1/include/sh')
| -rw-r--r-- | bsps/sh/gensh1/include/sh/sci.h | 82 | ||||
| -rw-r--r-- | bsps/sh/gensh1/include/sh/sh7_pfc.h | 115 | ||||
| -rw-r--r-- | bsps/sh/gensh1/include/sh/sh7_sci.h | 79 |
3 files changed, 276 insertions, 0 deletions
diff --git a/bsps/sh/gensh1/include/sh/sci.h b/bsps/sh/gensh1/include/sh/sci.h new file mode 100644 index 0000000000..5653afca3c --- /dev/null +++ b/bsps/sh/gensh1/include/sh/sci.h @@ -0,0 +1,82 @@ +/* + * Driver for the sh1 703x on-chip serial devices (sci) + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _sh_sci_h +#define _sh_sci_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Devices are set to 9600 bps, 8 databits, 1 stopbit, no + * parity and asynchronous mode by default. + * + * NOTE: + * The onboard serial devices of the SH do not support hardware + * handshake. + */ + +#define DEVSCI_DRIVER_TABLE_ENTRY \ + { sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \ + sh_sci_write, sh_sci_control } + +extern rtems_device_driver sh_sci_initialize( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_open( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_close( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_read( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_write( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +extern rtems_device_driver sh_sci_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/sh/gensh1/include/sh/sh7_pfc.h b/bsps/sh/gensh1/include/sh/sh7_pfc.h new file mode 100644 index 0000000000..1045af6af8 --- /dev/null +++ b/bsps/sh/gensh1/include/sh/sh7_pfc.h @@ -0,0 +1,115 @@ +/* + * Bit values for the pin function controller of the Hitachi SH703X + * + * From Hitachi tutorials + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _sh7_pfc_h +#define _sh7_pfc_h + +#include <rtems/score/iosh7032.h> + +/* + * Port B IO Register (PBIOR) + */ +#define PBIOR PFC_PBIOR +#define PB15IOR 0x8000 +#define PB14IOR 0x4000 +#define PB13IOR 0x2000 +#define PB12IOR 0x1000 +#define PB11IOR 0x0800 +#define PB10IOR 0x0400 +#define PB9IOR 0x0200 +#define PB8IOR 0x0100 +#define PB7IOR 0x0080 +#define PB6IOR 0x0040 +#define PB5IOR 0x0020 +#define PB4IOR 0x0010 +#define PB3IOR 0x0008 +#define PB2IOR 0x0004 +#define PB1IOR 0x0002 +#define PB0IOR 0x0001 + +/* + * Port B Control Register (PBCR1) + */ +#define PBCR1 PFC_PBCR1 +#define PB15MD1 0x8000 +#define PB15MD0 0x4000 +#define PB14MD1 0x2000 +#define PB14MD0 0x1000 +#define PB13MD1 0x0800 +#define PB13MD0 0x0400 +#define PB12MD1 0x0200 +#define PB12MD0 0x0100 +#define PB11MD1 0x0080 +#define PB11MD0 0x0040 +#define PB10MD1 0x0020 +#define PB10MD0 0x0010 +#define PB9MD1 0x0008 +#define PB9MD0 0x0004 +#define PB8MD1 0x0002 +#define PB8MD0 0x0001 + +#define PB15MD PB15MD1|PB14MD0 +#define PB14MD PB14MD1|PB14MD0 +#define PB13MD PB13MD1|PB13MD0 +#define PB12MD PB12MD1|PB12MD0 +#define PB11MD PB11MD1|PB11MD0 +#define PB10MD PB10MD1|PB10MD0 +#define PB9MD PB9MD1|PB9MD0 +#define PB8MD PB8MD1|PB8MD0 + +#define PB_TXD1 PB11MD1 +#define PB_RXD1 PB10MD1 +#define PB_TXD0 PB9MD1 +#define PB_RXD0 PB8MD1 + +/* + * Port B Control Register (PBCR2) + */ +#define PBCR2 PFC_PBCR2 +#define PB7MD1 0x8000 +#define PB7MD0 0x4000 +#define PB6MD1 0x2000 +#define PB6MD0 0x1000 +#define PB5MD1 0x0800 +#define PB5MD0 0x0400 +#define PB4MD1 0x0200 +#define PB4MD0 0x0100 +#define PB3MD1 0x0080 +#define PB3MD0 0x0040 +#define PB2MD1 0x0020 +#define PB2MD0 0x0010 +#define PB1MD1 0x0008 +#define PB1MD0 0x0004 +#define PB0MD1 0x0002 +#define PB0MD0 0x0001 + +#define PB7MD PB7MD1|PB7MD0 +#define PB6MD PB6MD1|PB6MD0 +#define PB5MD PB5MD1|PB5MD0 +#define PB4MD PB4MD1|PB4MD0 +#define PB3MD PB3MD1|PB3MD0 +#define PB2MD PB2MD1|PB2MD0 +#define PB1MD PB1MD1|PB1MD0 +#define PB0MD PB0MD1|PB0MD0 + +#endif /* _sh7_pfc_h */ diff --git a/bsps/sh/gensh1/include/sh/sh7_sci.h b/bsps/sh/gensh1/include/sh/sh7_sci.h new file mode 100644 index 0000000000..0b80a485d3 --- /dev/null +++ b/bsps/sh/gensh1/include/sh/sh7_sci.h @@ -0,0 +1,79 @@ +/* + * Bit values for the serial control registers of the Hitachi SH703X + * + * From Hitachi tutorials + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _sh7_sci_h +#define _sh7_sci_h + +#include <rtems/score/iosh7032.h> + +/* + * Serial mode register bits + */ + +#define SCI_SYNC_MODE 0x80 +#define SCI_SEVEN_BIT_DATA 0x40 +#define SCI_PARITY_ON 0x20 +#define SCI_ODD_PARITY 0x10 +#define SCI_STOP_BITS_2 0x08 +#define SCI_ENABLE_MULTIP 0x04 +#define SCI_PHI_64 0x03 +#define SCI_PHI_16 0x02 +#define SCI_PHI_4 0x01 +#define SCI_PHI_0 0x00 + +/* + * Serial register offsets, relative to SCI0_SMR or SCI1_SMR + */ + +#define SCI_SMR 0x00 +#define SCI_BRR 0x01 +#define SCI_SCR 0x02 +#define SCI_TDR 0x03 +#define SCI_SSR 0x04 +#define SCI_RDR 0x05 + +/* + * Serial control register bits + */ +#define SCI_TIE 0x80 /* Transmit interrupt enable */ +#define SCI_RIE 0x40 /* Receive interrupt enable */ +#define SCI_TE 0x20 /* Transmit enable */ +#define SCI_RE 0x10 /* Receive enable */ +#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ +#define SCI_TEIE 0x04 /* Transmit end interrupt enable */ +#define SCI_CKE1 0x02 /* Clock enable 1 */ +#define SCI_CKE0 0x01 /* Clock enable 0 */ + +/* + * Serial status register bits + */ +#define SCI_TDRE 0x80 /* Transmit data register empty */ +#define SCI_RDRF 0x40 /* Receive data register full */ +#define SCI_ORER 0x20 /* Overrun error */ +#define SCI_FER 0x10 /* Framing error */ +#define SCI_PER 0x08 /* Parity error */ +#define SCI_TEND 0x04 /* Transmit end */ +#define SCI_MPB 0x02 /* Multiprocessor bit */ +#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ + +#endif /* _sh7_sci_h */ |