diff options
Diffstat (limited to 'bsps/powerpc/virtex/include/bsp')
| -rw-r--r-- | bsps/powerpc/virtex/include/bsp/irq.h | 94 | ||||
| -rw-r--r-- | bsps/powerpc/virtex/include/bsp/opbintctrl.h | 75 |
2 files changed, 169 insertions, 0 deletions
diff --git a/bsps/powerpc/virtex/include/bsp/irq.h b/bsps/powerpc/virtex/include/bsp/irq.h new file mode 100644 index 0000000000..1ce5b68b98 --- /dev/null +++ b/bsps/powerpc/virtex/include/bsp/irq.h @@ -0,0 +1,94 @@ +/*===============================================================*\ +| Project: RTEMS virtex BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares constants of the interrupt controller | +\*===============================================================*/ +#ifndef VIRTEX_IRQ_IRQ_H +#define VIRTEX_IRQ_IRQ_H + +#include <rtems/irq.h> +#include <rtems/irq-extension.h> +#include <bsp/opbintctrl.h> + +/* + * the following definitions specify the indices used + * to interface the interrupt handler API + */ + +/* + * Peripheral IRQ handlers related definitions + */ +#define BSP_OPBINTC_PER_IRQ_NUMBER XPAR_INTC_MAX_NUM_INTR_INPUTS +#define BSP_OPBINTC_IRQ_LOWEST_OFFSET 0 +#define BSP_OPBINTC_IRQ_MAX_OFFSET (BSP_OPBINTC_IRQ_LOWEST_OFFSET\ + +BSP_OPBINTC_PER_IRQ_NUMBER-1) + +#define BSP_IS_OPBINTC_IRQ(irqnum) \ + (((irqnum) >= BSP_OPBINTC_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_OPBINTC_IRQ_MAX_OFFSET)) +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 3 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_OPBINTC_IRQ_MAX_OFFSET+1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ + +BSP_PROCESSOR_IRQ_NUMBER-1) + +#define BSP_IS_PROCESSOR_IRQ(irqnum) \ + (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) +#define BSP_LOWEST_OFFSET BSP_OPBINTC_IRQ_LOWEST_OFFSET +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET + +#define BSP_IS_VALID_IRQ(irqnum) \ + (BSP_IS_PROCESSOR_IRQ(irqnum) \ + || BSP_IS_OPBINTC_IRQ(irqnum)) + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX BSP_PROCESSOR_IRQ_MAX_OFFSET + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ + typedef enum { + BSP_OPBINTC_IRQ_FIRST = BSP_OPBINTC_IRQ_LOWEST_OFFSET, + /* + * Note: for this BSP, the peripheral names are derived + * from the Xilinx parameter file + */ + BSP_OPBINTC_IRQ_LAST = BSP_OPBINTC_IRQ_MAX_OFFSET, + BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, + BSP_PIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, + BSP_CRIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + } rtems_irq_symbolic_name; + +#define BSP_OPBINTC_XPAR(xname) (BSP_OPBINTC_IRQ_LOWEST_OFFSET+xname) + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ + +#endif /* VIRTEX_IRQ_IRQ_H */ diff --git a/bsps/powerpc/virtex/include/bsp/opbintctrl.h b/bsps/powerpc/virtex/include/bsp/opbintctrl.h new file mode 100644 index 0000000000..4ade0e48f8 --- /dev/null +++ b/bsps/powerpc/virtex/include/bsp/opbintctrl.h @@ -0,0 +1,75 @@ +/* opbintctrl.h + * + * This file contains definitions and declarations for the + * Xilinx Off Processor Bus (OPB) Interrupt Controller + * + * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca> + * COPYRIGHT (c) 2005 by Linn Products Ltd, Scotland + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _INCLUDE_OPBINTCTRL_H +#define _INCLUDE_OPBINTCTRL_H + +#include <rtems.h> +#include <rtems/system.h> +#include <rtems/score/isr.h> +#include <rtems/irq.h> +#include <bspopts.h> +#include RTEMS_XPARAMETERS_H + +#define USE_GREG_INTERRUPTS + +#ifdef __cplusplus +extern "C" { +#endif + + +/* extern XIntc InterruptController; + */ + + +/* Maximum number of IRQs. Defined in vhdl model */ +#define OPB_INTC_IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS + +/* Width of INTC registers. Defined in vhdl model */ +#define OPB_INTC_REGISTER_WIDTH 32 + +/* Base Register address and register offsets. Defined in vhdl model */ +#define OPB_INTC_BASE XPAR_INTC_SINGLE_BASEADDR + + + + + +/* Interrupt Status Register */ +#define OPB_INTC_ISR 0x0 +/* Interrupt Pending Register (ISR && IER) */ +#define OPB_INTC_IPR 0x4 +/* Interrupt Enable Register */ +#define OPB_INTC_IER 0x8 +/* Interrupt Acknowledge Register */ +#define OPB_INTC_IAR 0xC +/* Set Interrupt Enable (same as read/mask/write to IER) */ +#define OPB_INTC_SIE 0x10 +/* Clear Interrupt Enable (same as read/mask/write to IER) */ +#define OPB_INTC_CIE 0x14 +/* Interrupt Vector Address (highest priority vector number from IPR) */ +#define OPB_INTC_IVR 0x18 +/* Master Enable Register */ +#define OPB_INTC_MER 0x1C + +/* Master Enable Register: Hardware Interrupt Enable */ +#define OPB_INTC_MER_HIE 0x2 + +/* Master Enable Register: Master IRQ Enable */ +#define OPB_INTC_MER_ME 0x1 + +#ifdef __cplusplus +} +#endif + +#endif /* _INCLUDE_OPBINTCTRL_H */ |