diff options
Diffstat (limited to 'bsps/powerpc/ss555/include')
| -rw-r--r-- | bsps/powerpc/ss555/include/bsp.h | 91 | ||||
| -rw-r--r-- | bsps/powerpc/ss555/include/bsp/irq.h | 66 | ||||
| -rw-r--r-- | bsps/powerpc/ss555/include/tm27.h | 56 |
3 files changed, 213 insertions, 0 deletions
diff --git a/bsps/powerpc/ss555/include/bsp.h b/bsps/powerpc/ss555/include/bsp.h new file mode 100644 index 0000000000..a82d10a667 --- /dev/null +++ b/bsps/powerpc/ss555/include/bsp.h @@ -0,0 +1,91 @@ +/* + * This file includes definitions for the Intec SS555. + */ + +/* + * SS555 port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h: + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SS555_BSP_H +#define LIBBSP_POWERPC_SS555_BSP_H + +#ifndef ASM + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <mpc5xx.h> +#include <mpc5xx/console.h> +#include <libcpu/vectors.h> +#include <bsp/irq.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Clock definitions + */ + +#define BSP_CRYSTAL_HZ 4000000 /* crystal frequency, Hz */ +#define BSP_CLOCK_HZ 40000000 /* CPU clock frequency, Hz + +/* + * I/O definitions + * + * The SS555 board includes a CPLD to control on-board features and + * off-board devices. + */ +typedef struct cpld_ { + uint8_t cs3a[32]; /* Chip select 3A */ + uint8_t pad0[0x200000 - 0x000020]; + + uint8_t cs3b[32]; /* Chip select 3B */ + uint8_t pad2[0x400000 - 0x200020]; + + uint8_t cs3c[32]; /* Chip select 3C */ + uint8_t pad4[0x600000 - 0x400020]; + + uint8_t cs3d[32]; /* Chip select 3D */ + uint8_t pad6[0x800000 - 0x600020]; + + uint8_t serial_ints; /* Enable/disable serial interrupts */ + uint8_t serial_resets; /* Enable/disable serial resets */ + uint8_t serial_ack; /* Acknowledge serial transfers */ + uint8_t pad8[0xA00000 - 0x800003]; + + uint8_t iflash_writess; /* Enable/disable internal-flash writes */ + uint8_t nflash_writess; /* Enable/disable NAND-flash writes */ + uint8_t padA[0xC00000 - 0xA00002]; +} cpld_t; + +extern volatile cpld_t cpld; /* defined in linkcmds */ + +/* clock/p_clock.c */ +extern int BSP_disconnect_clock_handler (void); + +extern int BSP_connect_clock_handler (rtems_irq_hdl hdl); + +/* + * Prototypes for methods called from .S to support dependency tracking. + */ +void _InitSS555(void); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/powerpc/ss555/include/bsp/irq.h b/bsps/powerpc/ss555/include/bsp/irq.h new file mode 100644 index 0000000000..44e39608b1 --- /dev/null +++ b/bsps/powerpc/ss555/include/bsp/irq.h @@ -0,0 +1,66 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * + * SS555 port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from libbsp/powerpc/mbx8xx/irq/irq.h: + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * <http://www.chorus.com/Documentation/index.html> by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SS555_IRQ_IRQ_H +#define LIBBSP_POWERPC_SS555_IRQ_IRQ_H + +#include <libcpu/irq.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * These are no longer prototyped anywhere else. This appears to be + * remnants of the IRQ code upgrade. + * + * --joel 28 April 2010 + */ +int CPU_install_rtems_irq_handler(const rtems_irq_connect_data* irq); +int CPU_get_current_rtems_irq_handler(rtems_irq_connect_data* irq); +int CPU_remove_rtems_irq_handler(const rtems_irq_connect_data* irq); +int CPU_rtems_irq_mngt_set(rtems_irq_global_settings* config); +int CPU_rtems_irq_mngt_get(rtems_irq_global_settings** config); +void C_default_exception_handler(CPU_Exception_frame* excPtr); + +/* + * The SS555 has no external interrupt controller chip, so use the standard + * routines from the CPU-dependent code. + */ +#define BSP_install_rtems_irq_handler(ptr) CPU_install_rtems_irq_handler(ptr) +#define BSP_get_current_rtems_irq_handler(ptr) CPU_get_current_rtems_irq_handler(ptr) +#define BSP_remove_rtems_irq_handler(ptr) CPU_remove_rtems_irq_handler(ptr) +#define BSP_rtems_irq_mngt_set(config) CPU_rtems_irq_mngt_set(config) +#define BSP_rtems_irq_mngt_get(config) CPU_rtems_irq_mngt_get(config) +#define BSP_rtems_irq_mng_init(cpuId) CPU_rtems_irq_mng_init(cpuId) + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* LIBBSP_POWERPC_SS555_IRQ_IRQ_H */ diff --git a/bsps/powerpc/ss555/include/tm27.h b/bsps/powerpc/ss555/include/tm27.h new file mode 100644 index 0000000000..5106801744 --- /dev/null +++ b/bsps/powerpc/ss555/include/tm27.h @@ -0,0 +1,56 @@ +/* + * @file + * @ingroup powerpc_ss555 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * + * The following require that IRQ7 be jumpered to ground. On the SS555, + * this can be done by shorting together CN5 pin 48 and CN5 pin 50. + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ +{ \ + extern rtems_irq_connect_data tm27IrqData; \ + usiu.siel |= (1 << 17); \ + usiu.sipend |= (1 << 17); \ + \ + tm27IrqData.hdl = (rtems_irq_hdl)handler; \ + BSP_install_rtems_irq_handler (&tm27IrqData); \ +} + +#define Cause_tm27_intr() \ +{ \ + usiu.siel &= ~(1 << 17); \ +} + +#define Clear_tm27_intr() \ +{ \ + usiu.siel |= (1 << 17); \ + usiu.sipend |= (1 << 17); \ +} + +#define Lower_tm27_intr() \ +{ \ + ppc_cached_irq_mask |= (1 << 17); \ + usiu.simask = ppc_cached_irq_mask; \ +} + +#endif |