diff options
Diffstat (limited to 'bsps/powerpc/shared')
27 files changed, 397 insertions, 48 deletions
diff --git a/bsps/powerpc/shared/clock/clock.c b/bsps/powerpc/shared/clock/clock.c index 6e8cc52ee5..072e470a92 100644 --- a/bsps/powerpc/shared/clock/clock.c +++ b/bsps/powerpc/shared/clock/clock.c @@ -9,7 +9,7 @@ */ /* - * Copyright (c) 2008-2015 embedded brains GmbH. All rights reserved. + * Copyright (C) 2008, 2015 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/powerpc/shared/cpu.c b/bsps/powerpc/shared/cpu.c index a06b8c0868..c38b60b4ee 100644 --- a/bsps/powerpc/shared/cpu.c +++ b/bsps/powerpc/shared/cpu.c @@ -130,7 +130,7 @@ void _CPU_Context_Initialize( #endif if ( tls_area != NULL ) { - void *tls_block = _TLS_TCB_before_TLS_block_initialize( tls_area ); + void *tls_block = _TLS_Initialize_area( tls_area ); the_ppc_context->tp = (uintptr_t) tls_block + 0x7000; } diff --git a/bsps/powerpc/shared/cpu_asm.S b/bsps/powerpc/shared/cpu_asm.S index 63f6a3fdfe..9800d0d2c6 100644 --- a/bsps/powerpc/shared/cpu_asm.S +++ b/bsps/powerpc/shared/cpu_asm.S @@ -23,7 +23,7 @@ * COPYRIGHT (c) 1989-1997. * On-Line Applications Research Corporation (OAR). * - * Copyright (c) 2011, 2017 embedded brains GmbH + * Copyright (C) 2011, 2020 embedded brains GmbH & Co. KG * * The license and distribution terms for this file may in * the file LICENSE in this distribution or at @@ -267,6 +267,10 @@ PROC (_CPU_Context_switch_no_return): isync #endif +#if defined(PPC_MULTILIB_ALTIVEC) && defined(__PPC_VRSAVE__) + mfvrsave r9 +#endif + /* Align to a cache line */ CLEAR_RIGHT_IMMEDIATE r3, r3, PPC_DEFAULT_CACHE_LINE_POWER CLEAR_RIGHT_IMMEDIATE r5, r4, PPC_DEFAULT_CACHE_LINE_POWER @@ -284,6 +288,14 @@ PROC (_CPU_Context_switch_no_return): mfmsr r6 #endif /* END PPC_DISABLE_MSR_ACCESS */ mfcr r7 +#ifdef PPC_MULTILIB_ALTIVEC +#ifdef __PPC_VRSAVE__ + /* Mark v0 as used since we need it to get the VSCR */ + oris r8, r9, 0x8000 + mtvrsave r8 +#endif + mfvscr v0 +#endif mflr r8 lwz r11, PER_CPU_ISR_DISPATCH_DISABLE(r12) @@ -356,6 +368,16 @@ PROC (_CPU_Context_switch_no_return): stw r11, PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE(r3) #ifdef PPC_MULTILIB_ALTIVEC + li r10, PPC_CONTEXT_OFFSET_VSCR + stvewx v0, r3, r10 + +#ifdef __PPC_VRSAVE__ + stw r9, PPC_CONTEXT_OFFSET_VRSAVE(r3) + andi. r9, r9, 0xfff + bne .Laltivec_save + +.Laltivec_save_continue: +#else /* __PPC_VRSAVE__ */ li r9, PPC_CONTEXT_OFFSET_V20 stvx v20, r3, r9 li r9, PPC_CONTEXT_OFFSET_V21 @@ -397,7 +419,8 @@ PROC (_CPU_Context_switch_no_return): stvx v31, r3, r9 mfvrsave r9 stw r9, PPC_CONTEXT_OFFSET_VRSAVE(r3) -#endif +#endif /* __PPC_VRSAVE__ */ +#endif /* PPC_MULTILIB_ALTIVEC */ #ifdef PPC_MULTILIB_FPU stfd f14, PPC_CONTEXT_OFFSET_F14(r3) @@ -461,6 +484,14 @@ restore_context: PPC_REG_LOAD r1, PPC_CONTEXT_OFFSET_GPR1(r5) PPC_REG_LOAD r8, PPC_CONTEXT_OFFSET_LR(r5) +#ifdef PPC_MULTILIB_ALTIVEC + li r10, PPC_CONTEXT_OFFSET_VSCR + lvewx v0, r5, r10 +#ifdef __PPC_VRSAVE__ + lwz r9, PPC_CONTEXT_OFFSET_VRSAVE(r5) +#endif +#endif + PPC_GPR_LOAD r14, PPC_CONTEXT_OFFSET_GPR14(r5) PPC_GPR_LOAD r15, PPC_CONTEXT_OFFSET_GPR15(r5) @@ -494,6 +525,15 @@ restore_context: lwz r11, PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE(r5) #ifdef PPC_MULTILIB_ALTIVEC + mtvscr v0 + +#ifdef __PPC_VRSAVE__ + mtvrsave r9 + andi. r9, r9, 0xfff + bne .Laltivec_restore + +.Laltivec_restore_continue: +#else /* __PPC_VRSAVE__ */ li r9, PPC_CONTEXT_OFFSET_V20 lvx v20, r5, r9 li r9, PPC_CONTEXT_OFFSET_V21 @@ -520,7 +560,8 @@ restore_context: lvx v31, r5, r9 lwz r9, PPC_CONTEXT_OFFSET_VRSAVE(r5) mtvrsave r9 -#endif +#endif /* __PPC_VRSAVE__ */ +#endif /* PPC_MULTILIB_ALTIVEC */ #ifdef PPC_MULTILIB_FPU lfd f14, PPC_CONTEXT_OFFSET_F14(r5) @@ -567,6 +608,13 @@ PROC (_CPU_Context_restore): li r3, 0 #endif +#if defined(PPC_MULTILIB_ALTIVEC) && defined(__PPC_VRSAVE__) + /* Mark v0 as used since we need it to get the VSCR */ + mfvrsave r9 + oris r8, r9, 0x8000 + mtvrsave r8 +#endif + b restore_context #ifdef RTEMS_SMP @@ -595,3 +643,105 @@ PROC (_CPU_Context_restore): b .Lcheck_is_executing #endif + +#if defined(PPC_MULTILIB_ALTIVEC) && defined(__PPC_VRSAVE__) +.Laltivec_save: + + /* + * Let X be VRSAVE, calculate: + * + * Z = X & 0x777 + * Z = Z + 0x777 + * X = X | Z + * + * Afterwards, we have in X for each group of four non-volatile VR + * registers: + * + * 0111b, if VRSAVE group of four registers == 0 + * 1XXXb, if VRSAVE group of four registers != 0 + */ + andi. r10, r9, 0x777 + addi r10, r10, 0x777 + or r9, r9, r10 + mtcr r9 + + bf 20, .Laltivec_save_v24 + li r9, PPC_CONTEXT_OFFSET_V20 + stvx v20, r3, r9 + li r9, PPC_CONTEXT_OFFSET_V21 + stvx v21, r3, r9 + li r9, PPC_CONTEXT_OFFSET_V22 + stvx v22, r3, r9 + li r9, PPC_CONTEXT_OFFSET_V23 + stvx v23, r3, r9 + +.Laltivec_save_v24: + + bf 24, .Laltivec_save_v28 + li r9, PPC_CONTEXT_OFFSET_V24 + stvx v24, r3, r9 + li r9, PPC_CONTEXT_OFFSET_V25 + stvx v25, r3, r9 + li r9, PPC_CONTEXT_OFFSET_V26 + stvx v26, r3, r9 + li r9, PPC_CONTEXT_OFFSET_V27 + stvx v27, r3, r9 + +.Laltivec_save_v28: + + bf 28, .Laltivec_save_continue + li r9, PPC_CONTEXT_OFFSET_V28 + stvx v28, r3, r9 + li r9, PPC_CONTEXT_OFFSET_V29 + stvx v29, r3, r9 + li r9, PPC_CONTEXT_OFFSET_V30 + stvx v30, r3, r9 + li r9, PPC_CONTEXT_OFFSET_V31 + stvx v31, r3, r9 + + b .Laltivec_save_continue + +.Laltivec_restore: + + /* See comment at .Laltivec_save */ + andi. r10, r9, 0x777 + addi r10, r10, 0x777 + or r9, r9, r10 + mtcr r9 + + bf 20, .Laltivec_restore_v24 + li r9, PPC_CONTEXT_OFFSET_V20 + lvx v20, r5, r9 + li r9, PPC_CONTEXT_OFFSET_V21 + lvx v21, r5, r9 + li r9, PPC_CONTEXT_OFFSET_V22 + lvx v22, r5, r9 + li r9, PPC_CONTEXT_OFFSET_V23 + lvx v23, r5, r9 + +.Laltivec_restore_v24: + + bf 24, .Laltivec_restore_v28 + li r9, PPC_CONTEXT_OFFSET_V24 + lvx v24, r5, r9 + li r9, PPC_CONTEXT_OFFSET_V25 + lvx v25, r5, r9 + li r9, PPC_CONTEXT_OFFSET_V26 + lvx v26, r5, r9 + li r9, PPC_CONTEXT_OFFSET_V27 + lvx v27, r5, r9 + +.Laltivec_restore_v28: + + bf 28, .Laltivec_restore_continue + li r9, PPC_CONTEXT_OFFSET_V28 + lvx v28, r5, r9 + li r9, PPC_CONTEXT_OFFSET_V29 + lvx v29, r5, r9 + li r9, PPC_CONTEXT_OFFSET_V30 + lvx v30, r5, r9 + li r9, PPC_CONTEXT_OFFSET_V31 + lvx v31, r5, r9 + + b .Laltivec_restore_continue +#endif /* PPC_MULTILIB_ALTIVEC && __PPC_VRSAVE__ */ diff --git a/bsps/powerpc/shared/doxygen.h b/bsps/powerpc/shared/doxygen.h index ca5c2b2a58..d4a7794bc8 100644 --- a/bsps/powerpc/shared/doxygen.h +++ b/bsps/powerpc/shared/doxygen.h @@ -1,4 +1,12 @@ /** + * @file + * + * @ingroup RTEMSImplDoxygen + * + * @brief This header file defines powerpc-specific groups. + */ + +/** * @defgroup RTEMSBSPsPowerPC PowerPC * * @ingroup RTEMSBSPs diff --git a/bsps/powerpc/shared/exceptions/ppc-code-copy.c b/bsps/powerpc/shared/exceptions/ppc-code-copy.c index 1c4d99a8d1..d63b7a9f53 100644 --- a/bsps/powerpc/shared/exceptions/ppc-code-copy.c +++ b/bsps/powerpc/shared/exceptions/ppc-code-copy.c @@ -9,7 +9,7 @@ */ /* - * Copyright (c) 2009 embedded brains GmbH. All rights reserved. + * Copyright (c) 2009 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/powerpc/shared/exceptions/ppc-exc-handler-table.c b/bsps/powerpc/shared/exceptions/ppc-exc-handler-table.c index ca0760ad30..34cc194afb 100644 --- a/bsps/powerpc/shared/exceptions/ppc-exc-handler-table.c +++ b/bsps/powerpc/shared/exceptions/ppc-exc-handler-table.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2012 embedded brains GmbH. All rights reserved. + * Copyright (c) 2012 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_address.c b/bsps/powerpc/shared/exceptions/ppc_exc_address.c index 08a5433641..8d277c3b86 100644 --- a/bsps/powerpc/shared/exceptions/ppc_exc_address.c +++ b/bsps/powerpc/shared/exceptions/ppc_exc_address.c @@ -10,7 +10,7 @@ * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) * Canon Centre Recherche France. * - * Copyright (C) 2009 embedded brains GmbH. + * Copyright (C) 2009 embedded brains GmbH & Co. KG * * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> * to support 603, 603e, 604, 604e exceptions diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_alignment.c b/bsps/powerpc/shared/exceptions/ppc_exc_alignment.c index e0b7f0a435..16d904063e 100644 --- a/bsps/powerpc/shared/exceptions/ppc_exc_alignment.c +++ b/bsps/powerpc/shared/exceptions/ppc_exc_alignment.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * Copyright (c) 2011 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_async_normal.S b/bsps/powerpc/shared/exceptions/ppc_exc_async_normal.S index de4621ef55..701fc20bbb 100644 --- a/bsps/powerpc/shared/exceptions/ppc_exc_async_normal.S +++ b/bsps/powerpc/shared/exceptions/ppc_exc_async_normal.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2011, 2017 embedded brains GmbH. All rights reserved. + * Copyright (C) 2011, 2020 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -173,8 +173,15 @@ ppc_exc_interrupt: evstdd SCRATCH_5_REGISTER, PPC_EXC_ACC_OFFSET(r1) #endif -#ifdef PPC_MULTILIB_ALTIVEC /* Save volatile AltiVec context */ +#ifdef PPC_MULTILIB_ALTIVEC +#ifdef __PPC_VRSAVE__ + mfvrsave SCRATCH_0_REGISTER + cmpwi SCRATCH_0_REGISTER, 0 + bne .Laltivec_save + +.Laltivec_save_continue: +#else /* __PPC_VRSAVE__ */ li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(0) stvx v0, r1, SCRATCH_0_REGISTER mfvscr v0 @@ -218,7 +225,8 @@ ppc_exc_interrupt: stvx v19, r1, SCRATCH_0_REGISTER li SCRATCH_0_REGISTER, PPC_EXC_MIN_VSCR_OFFSET stvewx v0, r1, SCRATCH_0_REGISTER -#endif +#endif /* __PPC_VRSAVE__ */ +#endif /* PPC_MULTILIB_ALTIVEC */ #ifdef PPC_MULTILIB_FPU /* Save volatile FPU context */ @@ -334,8 +342,15 @@ ppc_exc_interrupt: .Lthread_dispatch_done: -#ifdef PPC_MULTILIB_ALTIVEC /* Restore volatile AltiVec context */ +#ifdef PPC_MULTILIB_ALTIVEC +#ifdef __PPC_VRSAVE__ + mfvrsave SCRATCH_0_REGISTER + cmpwi SCRATCH_0_REGISTER, 0 + bne .Laltivec_restore + +.Laltivec_restore_continue: +#else /* __PPC_VRSAVE__ */ li SCRATCH_0_REGISTER, PPC_EXC_MIN_VSCR_OFFSET lvewx v0, r1, SCRATCH_0_REGISTER mtvscr v0 @@ -379,7 +394,8 @@ ppc_exc_interrupt: lvx v18, r1, SCRATCH_0_REGISTER li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(19) lvx v19, r1, SCRATCH_0_REGISTER -#endif +#endif /* __PPC_VRSAVE__ */ +#endif /* PPC_MULTILIB_ALTIVEC */ #ifdef PPC_MULTILIB_FPU /* Restore volatile FPU context */ @@ -478,6 +494,169 @@ ppc_exc_interrupt: /* Return */ rfi +#if defined(PPC_MULTILIB_ALTIVEC) && defined(__PPC_VRSAVE__) +.Laltivec_save: + + /* + * Let X be VRSAVE, calculate: + * + * Y = 0x77777777 + * Z = X & Y + * Z = Z + Y + * X = X | Z + * + * Afterwards, we have in X for each group of four VR registers: + * + * 0111b, if VRSAVE group of four registers == 0 + * 1XXXb, if VRSAVE group of four registers != 0 + */ + lis SCRATCH_5_REGISTER, 0x7777 + ori SCRATCH_5_REGISTER, SCRATCH_5_REGISTER, 0x7777 + and SCRATCH_6_REGISTER, SCRATCH_0_REGISTER, SCRATCH_5_REGISTER + add SCRATCH_6_REGISTER, SCRATCH_5_REGISTER, SCRATCH_6_REGISTER + or SCRATCH_0_REGISTER, SCRATCH_0_REGISTER, SCRATCH_6_REGISTER + mtcr SCRATCH_0_REGISTER + + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(0) + stvx v0, r1, SCRATCH_0_REGISTER + + /* Move VCSR to V0 */ + mfvscr v0 + + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(1) + stvx v1, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(2) + stvx v2, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(3) + stvx v3, r1, SCRATCH_0_REGISTER + + /* Save VCSR using V0 */ + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VSCR_OFFSET + stvewx v0, r1, SCRATCH_0_REGISTER + + bf 4, .Laltivec_save_v8 + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(4) + stvx v4, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(5) + stvx v5, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(6) + stvx v6, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(7) + stvx v7, r1, SCRATCH_0_REGISTER + +.Laltivec_save_v8: + + bf 8, .Laltivec_save_v12 + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(8) + stvx v8, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(9) + stvx v9, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(10) + stvx v10, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(11) + stvx v11, r1, SCRATCH_0_REGISTER + +.Laltivec_save_v12: + + bf 12, .Laltivec_save_v16 + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(12) + stvx v12, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(13) + stvx v13, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(14) + stvx v14, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(15) + stvx v15, r1, SCRATCH_0_REGISTER + +.Laltivec_save_v16: + + bf 16, .Laltivec_save_continue + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(16) + stvx v16, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(17) + stvx v17, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(18) + stvx v18, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(19) + stvx v19, r1, SCRATCH_0_REGISTER + + b .Laltivec_save_continue + +.Laltivec_restore: + + /* Load VCSR using V0 */ + li SCRATCH_5_REGISTER, PPC_EXC_MIN_VSCR_OFFSET + lvewx v0, r1, SCRATCH_5_REGISTER + + /* See comment at .Laltivec_save */ + lis SCRATCH_5_REGISTER, 0x7777 + ori SCRATCH_5_REGISTER, SCRATCH_5_REGISTER, 0x7777 + and SCRATCH_6_REGISTER, SCRATCH_0_REGISTER, SCRATCH_5_REGISTER + add SCRATCH_6_REGISTER, SCRATCH_5_REGISTER, SCRATCH_6_REGISTER + or SCRATCH_0_REGISTER, SCRATCH_0_REGISTER, SCRATCH_6_REGISTER + mtcr SCRATCH_0_REGISTER + + /* Restore VCR using V0 */ + mtvscr v0 + + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(0) + lvx v0, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(1) + lvx v1, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(2) + lvx v2, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(3) + lvx v3, r1, SCRATCH_0_REGISTER + + bf 4, .Laltivec_restore_v8 + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(4) + lvx v4, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(5) + lvx v5, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(6) + lvx v6, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(7) + lvx v7, r1, SCRATCH_0_REGISTER + +.Laltivec_restore_v8: + + bf 8, .Laltivec_restore_v12 + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(8) + lvx v8, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(9) + lvx v9, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(10) + lvx v10, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(11) + lvx v11, r1, SCRATCH_0_REGISTER + +.Laltivec_restore_v12: + + bf 12, .Laltivec_restore_v16 + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(12) + lvx v12, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(13) + lvx v13, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(14) + lvx v14, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(15) + lvx v15, r1, SCRATCH_0_REGISTER + +.Laltivec_restore_v16: + + bf 16, .Laltivec_restore_continue + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(16) + lvx v16, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(17) + lvx v17, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(18) + lvx v18, r1, SCRATCH_0_REGISTER + li SCRATCH_0_REGISTER, PPC_EXC_MIN_VR_OFFSET(19) + lvx v19, r1, SCRATCH_0_REGISTER + + b .Laltivec_restore_continue +#endif /* PPC_MULTILIB_ALTIVEC && __PPC_VRSAVE__ */ + /* Symbol provided for debugging and tracing */ ppc_exc_interrupt_end: diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_categories.c b/bsps/powerpc/shared/exceptions/ppc_exc_categories.c index 46508abcdf..9f7f638959 100644 --- a/bsps/powerpc/shared/exceptions/ppc_exc_categories.c +++ b/bsps/powerpc/shared/exceptions/ppc_exc_categories.c @@ -10,7 +10,7 @@ * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) * Canon Centre Recherche France. * - * Copyright (C) 2009-2011 embedded brains GmbH. + * Copyright (C) 2009, 2011 embedded brains GmbH & Co. KG * * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> * to support 603, 603e, 604, 604e exceptions diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_fatal.S b/bsps/powerpc/shared/exceptions/ppc_exc_fatal.S index 46e1e373b7..f8cb282e09 100644 --- a/bsps/powerpc/shared/exceptions/ppc_exc_fatal.S +++ b/bsps/powerpc/shared/exceptions/ppc_exc_fatal.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2011, 2017 embedded brains GmbH. All rights reserved. + * Copyright (C) 2011, 2017 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_initialize.c b/bsps/powerpc/shared/exceptions/ppc_exc_initialize.c index 46b72524ea..d47519b742 100644 --- a/bsps/powerpc/shared/exceptions/ppc_exc_initialize.c +++ b/bsps/powerpc/shared/exceptions/ppc_exc_initialize.c @@ -12,7 +12,7 @@ * * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> * - * Copyright (C) 2009-2012 embedded brains GmbH. + * Copyright (C) 2009, 2012 embedded brains GmbH & Co. KG * * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/vectors_init.c". * Derived from file "libcpu/powerpc/new-exceptions/e500_raw_exc_init.c". diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_naked.S b/bsps/powerpc/shared/exceptions/ppc_exc_naked.S index 95c9e7bf8e..b6960d7f46 100644 --- a/bsps/powerpc/shared/exceptions/ppc_exc_naked.S +++ b/bsps/powerpc/shared/exceptions/ppc_exc_naked.S @@ -9,7 +9,7 @@ */ /* - * Copyright (c) 2009 embedded brains GmbH. All rights reserved. + * Copyright (c) 2009 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_print.c b/bsps/powerpc/shared/exceptions/ppc_exc_print.c index e4fcc73cb1..ff231beff9 100644 --- a/bsps/powerpc/shared/exceptions/ppc_exc_print.c +++ b/bsps/powerpc/shared/exceptions/ppc_exc_print.c @@ -42,18 +42,23 @@ typedef struct LRFrameRec_ { static uint32_t ppc_exc_get_DAR_dflt(void) { - if (ppc_cpu_is_60x()) - return PPC_SPECIAL_PURPOSE_REGISTER(PPC_DAR); - else + uint32_t val; + if (ppc_cpu_is_60x()) { + PPC_SPECIAL_PURPOSE_REGISTER(PPC_DAR, val); + return val; + } else { switch (ppc_cpu_is_bookE()) { default: break; case PPC_BOOKE_STD: case PPC_BOOKE_E500: - return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_DEAR); + PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_DEAR, val); + return val; case PPC_BOOKE_405: - return PPC_SPECIAL_PURPOSE_REGISTER(PPC405_DEAR); + PPC_SPECIAL_PURPOSE_REGISTER(PPC405_DEAR, val); + return val; } + } return 0xdeadbeef; } @@ -170,13 +175,13 @@ void _CPU_Exception_frame_print(const CPU_Exception_frame *excPtr) printk(" %s = 0x%08" PRIx32 "\n", reg, ppc_exc_get_DAR()); } if (ppc_cpu_is_bookE()) { - unsigned esr, mcsr; + uint32_t esr, mcsr; if (ppc_cpu_is_bookE() == PPC_BOOKE_405) { - esr = PPC_SPECIAL_PURPOSE_REGISTER(PPC405_ESR); - mcsr = PPC_SPECIAL_PURPOSE_REGISTER(PPC405_MCSR); + PPC_SPECIAL_PURPOSE_REGISTER(PPC405_ESR, esr); + PPC_SPECIAL_PURPOSE_REGISTER(PPC405_MCSR, mcsr); } else { - esr = PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_ESR); - mcsr = PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_MCSR); + PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_ESR, esr); + PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_MCSR, mcsr); } printk(" ESR = 0x%08x\n", esr); printk(" MCSR = 0x%08x\n", mcsr); diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_prologue.c b/bsps/powerpc/shared/exceptions/ppc_exc_prologue.c index 09307cd944..6e99fa7681 100644 --- a/bsps/powerpc/shared/exceptions/ppc_exc_prologue.c +++ b/bsps/powerpc/shared/exceptions/ppc_exc_prologue.c @@ -9,7 +9,7 @@ /* * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> * - * Copyright (C) 2009-2012 embedded brains GmbH. + * Copyright (C) 2009, 2012 embedded brains GmbH & Co. KG * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at diff --git a/bsps/powerpc/shared/irq/irq_init.c b/bsps/powerpc/shared/irq/irq_init.c index 233c659b85..ecbff9bb19 100644 --- a/bsps/powerpc/shared/irq/irq_init.c +++ b/bsps/powerpc/shared/irq/irq_init.c @@ -98,7 +98,7 @@ static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={ }; #if BSP_PCI_IRQ_NUMBER > 0 -#if defined(mvme2100) +#if defined(mot_ppc_mvme2100) static unsigned char mvme2100_openpic_initpolarities[16] = { 0, /* Not used - should be disabled */ 0, /* DEC21143 Controller */ @@ -276,7 +276,7 @@ loop_exit: */ void BSP_rtems_irq_mng_init(unsigned cpuId) { -#if BSP_ISA_IRQ_NUMBER > 0 && !defined(mvme2100) +#if BSP_ISA_IRQ_NUMBER > 0 && !defined(mot_ppc_mvme2100) int known_cpi_isa_bridge = 0; #endif int i; @@ -285,7 +285,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) /* * First initialize the Interrupt management hardware */ -#if defined(mvme2100) +#if defined(mot_ppc_mvme2100) #ifdef TRACE_IRQ_INIT printk("Going to initialize EPIC interrupt controller (openpic compliant)\n"); #endif diff --git a/bsps/powerpc/shared/pci/detect_raven_bridge.c b/bsps/powerpc/shared/pci/detect_raven_bridge.c index 0a1c04a2e2..a3f03e0acd 100644 --- a/bsps/powerpc/shared/pci/detect_raven_bridge.c +++ b/bsps/powerpc/shared/pci/detect_raven_bridge.c @@ -30,7 +30,7 @@ extern const pci_config_access_functions pci_direct_functions; extern const pci_config_access_functions pci_indirect_functions; -#if defined(mvme2100) +#if defined(mot_ppc_mvme2100) /* FIXME - this should really be in a separate file - the 2100 doesn't * have a raven chip so there is no point having 2100 code here */ diff --git a/bsps/powerpc/shared/rtc/todcfg.c b/bsps/powerpc/shared/rtc/todcfg.c index 17ef18d5b5..95d75216a2 100644 --- a/bsps/powerpc/shared/rtc/todcfg.c +++ b/bsps/powerpc/shared/rtc/todcfg.c @@ -11,7 +11,7 @@ #include <libchip/m48t08.h> /* Forward function declaration */ -#if !defined(mvme2100) +#if !defined(mot_ppc_mvme2100) uint32_t mvmertc_get_register( uintptr_t, uint8_t ); void mvmertc_set_register( uintptr_t, uint8_t, uint32_t ); #endif @@ -24,7 +24,7 @@ rtc_tbl RTC_Table[] = { &m48t08_fns, /* pDeviceFns */ rtc_probe, /* deviceProbe */ NULL, /* pDeviceParams */ -#if defined(mvme2100) +#if defined(mot_ppc_mvme2100) 0xFFE81ff8, /* ulCtrlPort1 */ 0x00, /* ulDataPort */ m48t08_get_register, /* getRegister */ @@ -44,7 +44,7 @@ rtc_tbl RTC_Table[] = { size_t RTC_Count = NUM_RTCS; -#if !defined(mvme2100) +#if !defined(mot_ppc_mvme2100) #include <rtems/bspIo.h> void mvmertc_set_register( uintptr_t base, diff --git a/bsps/powerpc/shared/start/bsp-start-zero.S b/bsps/powerpc/shared/start/bsp-start-zero.S index 5242b01c13..aee2a6f5c4 100644 --- a/bsps/powerpc/shared/start/bsp-start-zero.S +++ b/bsps/powerpc/shared/start/bsp-start-zero.S @@ -9,7 +9,7 @@ */ /* - * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. + * Copyright (C) 2010, 2014 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/powerpc/shared/start/linkcmds.base b/bsps/powerpc/shared/start/linkcmds.base index 21fa729e38..4f626b13cc 100644 --- a/bsps/powerpc/shared/start/linkcmds.base +++ b/bsps/powerpc/shared/start/linkcmds.base @@ -9,7 +9,7 @@ */ /* - * Copyright (c) 2011, 2016 embedded brains GmbH. All rights reserved. + * Copyright (C) 2011, 2016 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -180,7 +180,7 @@ SECTIONS { KEEP (*(.jcr)) } > REGION_RODATA AT > REGION_RODATA_LOAD .data.rel.ro : ALIGN_WITH_INPUT { - *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) + *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) } > REGION_RODATA AT > REGION_RODATA_LOAD .fixup : ALIGN_WITH_INPUT { *(.fixup) diff --git a/bsps/powerpc/shared/start/memcpy.c b/bsps/powerpc/shared/start/memcpy.c index eb91e90f72..55605f2ecf 100644 --- a/bsps/powerpc/shared/start/memcpy.c +++ b/bsps/powerpc/shared/start/memcpy.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * Copyright (c) 2011 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/powerpc/shared/start/rtems_crti.S b/bsps/powerpc/shared/start/rtems_crti.S index 132a0473f4..7ef7998bd4 100644 --- a/bsps/powerpc/shared/start/rtems_crti.S +++ b/bsps/powerpc/shared/start/rtems_crti.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * Copyright (c) 2017 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/powerpc/shared/start/rtems_crtn.S b/bsps/powerpc/shared/start/rtems_crtn.S index fe9c48d6ea..792c9d7aa6 100644 --- a/bsps/powerpc/shared/start/rtems_crtn.S +++ b/bsps/powerpc/shared/start/rtems_crtn.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /* - * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * Copyright (c) 2017 embedded brains GmbH & Co. KG * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/bsps/powerpc/shared/start/tictac.c b/bsps/powerpc/shared/start/tictac.c index fdf97ae20f..25fd8f0cce 100644 --- a/bsps/powerpc/shared/start/tictac.c +++ b/bsps/powerpc/shared/start/tictac.c @@ -9,7 +9,7 @@ */ /* - * Copyright (c) 2008 embedded brains GmbH. All rights reserved. + * Copyright (c) 2008 embedded brains GmbH & Co. KG * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/bsps/powerpc/shared/vme/doxygen.h b/bsps/powerpc/shared/vme/doxygen.h index c87183464b..8e458ffd88 100644 --- a/bsps/powerpc/shared/vme/doxygen.h +++ b/bsps/powerpc/shared/vme/doxygen.h @@ -1,4 +1,12 @@ /** + * @file + * + * @ingroup RTEMSImplDoxygen + * + * @brief This header file defines VME-specific groups. + */ + +/** * @defgroup shared_vmeuniverse VME Universe Modules * * @brief VME Universe Modules diff --git a/bsps/powerpc/shared/vme/vmeTsi148.c b/bsps/powerpc/shared/vme/vmeTsi148.c index 78b939717c..aaabb1b28d 100644 --- a/bsps/powerpc/shared/vme/vmeTsi148.c +++ b/bsps/powerpc/shared/vme/vmeTsi148.c @@ -53,10 +53,12 @@ #include <stdlib.h> #include <rtems/bspIo.h> /* printk */ #include <rtems/error.h> /* printk */ +#include <rtems/irq.h> #include <rtems/pci.h> #include <rtems/score/sysstate.h> #include <bsp.h> #include <libcpu/byteorder.h> +#include <libcpu/io.h> #define __INSIDE_RTEMS_BSP__ #define _VME_TSI148_DECLARE_SHOW_ROUTINES @@ -1104,13 +1106,9 @@ vmeTsi148XlateAddr( } -/* printk cannot format %llx */ static void uprintfllx(FILE *f, unsigned long long v) { - if ( v >= ((unsigned long long)1)<<32 ) - uprintf(f,"0x%lx%08lx ", (unsigned long)(v>>32), (unsigned long)(v & 0xffffffff)); - else - uprintf(f,"0x%08lx ", (unsigned long)(v & 0xffffffff)); + uprintf(f,"0x%08llx ", v); } void diff --git a/bsps/powerpc/shared/vme/vmeUniverse.c b/bsps/powerpc/shared/vme/vmeUniverse.c index d0cd8e95e3..f636cfea09 100644 --- a/bsps/powerpc/shared/vme/vmeUniverse.c +++ b/bsps/powerpc/shared/vme/vmeUniverse.c @@ -1708,6 +1708,7 @@ LERegister1 dcpp = ld_le32(&d->dcpp); /* RTEMS interrupt subsystem */ #include <bsp/irq.h> +#include <rtems/irq.h> typedef struct UniverseIRQEntryRec_ { |