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-rw-r--r--bsps/powerpc/psim/include/bsp.h90
-rw-r--r--bsps/powerpc/psim/include/bsp/irq.h74
-rw-r--r--bsps/powerpc/psim/include/psim.h90
-rw-r--r--bsps/powerpc/psim/include/tm27.h66
4 files changed, 320 insertions, 0 deletions
diff --git a/bsps/powerpc/psim/include/bsp.h b/bsps/powerpc/psim/include/bsp.h
new file mode 100644
index 0000000000..cffc9632e7
--- /dev/null
+++ b/bsps/powerpc/psim/include/bsp.h
@@ -0,0 +1,90 @@
+/* bsp.h
+ *
+ * This include file contains all Papyrus board IO definitions.
+ *
+ * Author: Andrew Bray <andy@i-cubed.co.uk>
+ *
+ * COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ * To anyone who acknowledges that this file is provided "AS IS"
+ * without any express or implied warranty:
+ * permission to use, copy, modify, and distribute this file
+ * for any purpose is hereby granted without fee, provided that
+ * the above copyright notice and this notice appears in all
+ * copies, and that the name of i-cubed limited not be used in
+ * advertising or publicity pertaining to distribution of the
+ * software without specific, written prior permission.
+ * i-cubed limited makes no representations about the suitability
+ * of this software for any purpose.
+ *
+ * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h
+ *
+ * COPYRIGHT (c) 1989-1999.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_PSIM_BSP_H
+#define LIBBSP_POWERPC_PSIM_BSP_H
+
+#include <bspopts.h>
+
+#ifdef ASM
+/* Definition of where to store registers in alignment handler */
+#define ALIGN_REGS 0x0140
+
+#else
+#include <rtems.h>
+#include <libcpu/io.h>
+#include <bsp/vectors.h>
+#include <bsp/default-initial-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Constants */
+
+/*
+ * Information placed in the linkcmds file.
+ */
+
+extern int end; /* last address in the program */
+extern int RAM_END;
+
+extern uint32_t BSP_mem_size;
+
+#define BSP_Convert_decrementer( _value ) ( (unsigned long long) _value )
+
+/* macros */
+#define Processor_Synchronize() \
+ __asm__ (" eieio ")
+
+/*
+ * Network configuration
+ */
+struct rtems_bsdnet_ifconfig;
+
+int rtems_ifsim_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching);
+
+#define RTEMS_BSP_NETWORK_DRIVER_NAME "ifsim1"
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_ifsim_attach
+
+/*
+ * Interfaces to required Clock Driver support methods
+ */
+int BSP_disconnect_clock_handler(void);
+int BSP_connect_clock_handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ASM */
+
+#define BSP_HAS_NO_VME
+
+#endif
diff --git a/bsps/powerpc/psim/include/bsp/irq.h b/bsps/powerpc/psim/include/bsp/irq.h
new file mode 100644
index 0000000000..376c95a627
--- /dev/null
+++ b/bsps/powerpc/psim/include/bsp/irq.h
@@ -0,0 +1,74 @@
+/* irq.h
+ *
+ * This include file describe the data structure and the functions implemented
+ * by rtems to write interrupt handlers.
+ *
+ * CopyRight (C) 1999 valette@crf.canon.fr
+ *
+ * This code is heavilly inspired by the public specification of STREAM V2
+ * that can be found at :
+ *
+ * <http://www.chorus.com/Documentation/index.html> by following
+ * the STREAM API Specification Document link.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_IRQ_H
+#define LIBBSP_POWERPC_IRQ_H
+
+#define BSP_SHARED_HANDLER_SUPPORT 1
+
+#ifndef ASM
+
+#include <rtems/irq.h>
+
+
+/*
+ * Symblolic IRQ names and related definitions.
+ */
+
+/*
+ * PCI IRQ handlers related definitions
+ * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
+ */
+#define BSP_PCI_IRQ_NUMBER (16)
+#define BSP_PCI_IRQ_LOWEST_OFFSET (0)
+#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
+
+#define BSP_PROCESSOR_IRQ_NUMBER (1)
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET)
+#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1)
+
+
+ /*
+ * Summary
+ */
+#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
+#define BSP_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET)
+#define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1)
+
+ /*
+ * Some Processor execption handled as rtems IRQ symbolic name definition
+ */
+#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
+
+#include <bsp/irq_supp.h>
+
+#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
+#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void BSP_rtems_irq_mng_init(unsigned cpuId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+#endif
diff --git a/bsps/powerpc/psim/include/psim.h b/bsps/powerpc/psim/include/psim.h
new file mode 100644
index 0000000000..e7b6fa7578
--- /dev/null
+++ b/bsps/powerpc/psim/include/psim.h
@@ -0,0 +1,90 @@
+/*
+ * PSIM addresses and constants based upon the configuration
+ * of devices used in the script provided by RTEMS.
+ */
+
+#ifndef __PSIM_h
+#define __PSIM_h
+
+/*
+ * RAM Information
+ */
+
+extern char RamBase[];
+extern char RamSize[];
+
+/*
+ * RamBase/RamSize is defined by the linker script;
+ * CPP symbols are AFAIK unused and deprecated.
+ */
+#define PSIM_RAM_SIZE ((unsigned long)RamSize)
+#define PSIM_RAM_BASE ((void*)RamBase)
+
+/*
+ * NVRAM/RTC Structure and Information
+ */
+
+#define PSIM_RTC_FREEZE 0xc0
+#define PSIM_RTC_UPDATE 0x00
+
+typedef struct {
+ volatile uint8_t Control; /* 0x04 */
+ volatile uint8_t Second; /* 0x05 */
+ volatile uint8_t Minute; /* 0x06 */
+ volatile uint8_t Hour; /* 0x07 */
+ volatile uint8_t Day; /* 0x08 */
+ volatile uint8_t Date; /* 0x09 */
+ volatile uint8_t Month; /* 0x0a */
+ volatile uint8_t Year; /* 0x0b */
+} psim_rtc_t;
+
+/*
+ * System V IPC Semaphore -- Read Only
+ */
+
+typedef struct {
+ volatile uint32_t obtain_value; /* 0x00 */
+ volatile uint32_t lock; /* 0x04 */
+ volatile uint32_t unlock; /* 0x08 */
+} psim_sysv_sem_t;
+
+typedef struct {
+ /* 0x0c000000 - 0x0c007FFF - AMD 29F040 */
+ volatile uint8_t Flash[ 512 * 1024 ];
+
+ /* 0x0c080000 - 0x0c0FFFFF - NVRAM/NVRAM */
+ volatile uint8_t nvram[ 512 * 1024 ];
+
+ /* 0x0c100000 - 0x0c100007 - NVRAM/RTC */
+ psim_rtc_t RTC;
+
+ /* 0x0c100008 - 0x0c10000F - NVRAM/RTC */
+ uint8_t gap1[8];
+
+ /* 0x0c100010 - 0x0c10001b - System V IPC Semaphore */
+ psim_sysv_sem_t Semaphore;
+
+ /* 0x0c10001c - 0x0c10001f - NVRAM/RTC */
+ uint8_t gap2[4];
+
+ /* 0x0c100020 - 0x0c10005F - Ethernet */
+ volatile uint8_t Ethtap[ 64 ];
+
+ /* 0x0c100060 - 0x0c10FFFF - NVRAM/RTC */
+ uint8_t gap3[65440];
+
+ /* 0x0c110000 - 0x0c12FFFF - System V IPC Shared Memory */
+ uint8_t SharedMemory[ 128 * 1024 ];
+
+ /* 0x0c130000 - 0x0c170000 - OpenPIC IRQ Controller */
+ volatile uint8_t OpenPIC[ 256 * 1024 ];
+
+} psim_registers_t;
+
+/*
+ * Data Structure Overlay for Registers. See linkcmds for placement.
+ */
+extern psim_registers_t PSIM;
+
+#endif
+/* end of include file */
diff --git a/bsps/powerpc/psim/include/tm27.h b/bsps/powerpc/psim/include/tm27.h
new file mode 100644
index 0000000000..3a41283a13
--- /dev/null
+++ b/bsps/powerpc/psim/include/tm27.h
@@ -0,0 +1,66 @@
+/*
+ * @file
+ * @ingroup powerpc_psim
+ * @brief Implementations for interrupt mechanisms for Time Test 27
+ */
+
+/*
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+#include <bsp/irq.h>
+
+/*
+ * Stuff for Time Test 27
+ */
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+void nullFunc() {}
+static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
+ 0,
+ (rtems_irq_enable)nullFunc,
+ (rtems_irq_disable)nullFunc,
+ (rtems_irq_is_enabled) nullFunc};
+
+void Install_tm27_vector(void (*_handler)())
+{
+ clockIrqData.hdl = _handler;
+ if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
+ printk("Error installing clock interrupt handler!\n");
+ rtems_fatal_error_occurred(1);
+ }
+}
+
+#define Cause_tm27_intr() \
+ do { \
+ uint32_t _clicks = 1; \
+ __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
+ } while (0)
+
+
+#define Clear_tm27_intr() \
+ do { \
+ uint32_t _clicks = 0xffffffff; \
+ __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
+ } while (0)
+
+#define Lower_tm27_intr() \
+ do { \
+ uint32_t _msr = 0; \
+ _ISR_Set_level( 0 ); \
+ __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
+ _msr |= 0x8002; \
+ __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
+ } while (0)
+
+#endif
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