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-rw-r--r--bsps/powerpc/mpc55xxevb/headers.am15
-rw-r--r--bsps/powerpc/mpc55xxevb/include/bsp.h104
-rw-r--r--bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h57
-rw-r--r--bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h81
-rw-r--r--bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h64
-rw-r--r--bsps/powerpc/mpc55xxevb/include/bsp/irq.h499
-rw-r--r--bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h170
-rw-r--r--bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h704
-rw-r--r--bsps/powerpc/mpc55xxevb/include/tm27.h1
9 files changed, 1695 insertions, 0 deletions
diff --git a/bsps/powerpc/mpc55xxevb/headers.am b/bsps/powerpc/mpc55xxevb/headers.am
new file mode 100644
index 0000000000..6dffbe060c
--- /dev/null
+++ b/bsps/powerpc/mpc55xxevb/headers.am
@@ -0,0 +1,15 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/tm27.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/irq.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h
diff --git a/bsps/powerpc/mpc55xxevb/include/bsp.h b/bsps/powerpc/mpc55xxevb/include/bsp.h
new file mode 100644
index 0000000000..eee5d208c1
--- /dev/null
+++ b/bsps/powerpc/mpc55xxevb/include/bsp.h
@@ -0,0 +1,104 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief Global BSP variables and functions
+ */
+
+/*
+ * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_MPC55XXEVB_BSP_H
+#define LIBBSP_POWERPC_MPC55XXEVB_BSP_H
+
+#include <bspopts.h>
+
+#define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+#define MPC55XX_PERIPHERAL_CLOCK \
+ (MPC55XX_SYSTEM_CLOCK / MPC55XX_SYSTEM_CLOCK_DIVIDER)
+
+#ifndef ASM
+
+#include <rtems.h>
+
+#include <libcpu/powerpc-utility.h>
+
+#include <bsp/tictac.h>
+#include <bsp/linker-symbols.h>
+#include <bsp/default-initial-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/** @brief System clock frequency */
+extern unsigned int bsp_clock_speed;
+
+/** @brief Time base clicks per micro second */
+extern uint32_t bsp_clicks_per_usec;
+
+/** @brief Convert Decrementer ticks to microseconds */
+#define BSP_Convert_decrementer( _value ) \
+ (((unsigned long long) (_value)) / ((unsigned long long)bsp_clicks_per_usec))
+
+rtems_status_code mpc55xx_sd_card_init( bool mount);
+
+/* Network driver configuration */
+
+struct rtems_bsdnet_ifconfig;
+
+int smsc9218i_attach_detach(
+ struct rtems_bsdnet_ifconfig *config,
+ int attaching
+);
+
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH smsc9218i_attach_detach
+
+#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
+
+rtems_status_code bsp_register_i2c(void);
+
+void bsp_restart(void *addr);
+
+void *bsp_idle_thread(uintptr_t arg);
+
+#define BSP_IDLE_TASK_BODY bsp_idle_thread
+
+LINKER_SYMBOL(bsp_section_dsram_begin)
+LINKER_SYMBOL(bsp_section_dsram_end)
+LINKER_SYMBOL(bsp_section_dsram_size)
+LINKER_SYMBOL(bsp_section_dsram_load_begin)
+LINKER_SYMBOL(bsp_section_dsram_load_end)
+
+#define BSP_DSRAM_SECTION __attribute__((section(".bsp_dsram")))
+
+LINKER_SYMBOL(bsp_section_sysram_begin)
+LINKER_SYMBOL(bsp_section_sysram_end)
+LINKER_SYMBOL(bsp_section_sysram_size)
+LINKER_SYMBOL(bsp_section_sysram_load_begin)
+LINKER_SYMBOL(bsp_section_sysram_load_end)
+
+#define BSP_SYSRAM_SECTION __attribute__((section(".bsp_sysram")))
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+#endif /* LIBBSP_POWERPC_MPC55XXEVB_BSP_H */
diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h b/bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h
new file mode 100644
index 0000000000..4be6788141
--- /dev/null
+++ b/bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * @brief Console ESCI API.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H
+#define LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H
+
+#include "console-generic.h"
+
+#undef CR0
+#undef CR1
+#undef CR2
+#undef CR3
+
+#include <mpc55xx/regs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef MPC55XX_HAS_ESCI
+
+extern const console_generic_callbacks mpc55xx_esci_callbacks;
+
+typedef struct {
+ volatile struct ESCI_tag *regs;
+ struct rtems_termios_tty *tty;
+ int transmit_nest_level;
+ bool transmit_in_progress;
+ rtems_vector_number irq;
+} mpc55xx_esci_context;
+
+extern mpc55xx_esci_context mpc55xx_esci_devices [];
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H */
diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h b/bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h
new file mode 100644
index 0000000000..c3f7a4628f
--- /dev/null
+++ b/bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h
@@ -0,0 +1,81 @@
+/**
+ * @file
+ *
+ * @brief Generic console driver API.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_SHARED_CONSOLE_GENERIC_H
+#define LIBBSP_SHARED_CONSOLE_GENERIC_H
+
+#include <rtems/libio.h>
+#include <rtems/termiostypes.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef struct {
+ rtems_termios_callbacks termios_callbacks;
+ int (*poll_read)(int minor);
+ void (*poll_write)(int minor, char c);
+} console_generic_callbacks;
+
+typedef struct {
+ void *context;
+ const console_generic_callbacks *callbacks;
+ const char *device_path;
+} console_generic_info;
+
+extern const console_generic_info console_generic_info_table [];
+
+extern const size_t console_generic_info_count;
+
+extern const rtems_device_minor_number console_generic_minor;
+
+#define CONSOLE_GENERIC_INFO_TABLE \
+ const console_generic_info console_generic_info_table []
+
+#define CONSOLE_GENERIC_INFO(context, callbacks, device_path) \
+ { context, callbacks, device_path }
+
+#define CONSOLE_GENERIC_INFO_COUNT \
+ const size_t console_generic_info_count = \
+ sizeof(console_generic_info_table) / sizeof(console_generic_info_table [0])
+
+#define CONSOLE_GENERIC_MINOR(minor) \
+ const rtems_device_minor_number console_generic_minor = (minor)
+
+static inline void *console_generic_get_context(int minor)
+{
+ return console_generic_info_table [minor].context;
+}
+
+static inline struct rtems_termios_tty *console_generic_get_tty_at_open(
+ void *arg
+)
+{
+ const rtems_libio_open_close_args_t *oc =
+ (const rtems_libio_open_close_args_t *) arg;
+
+ return (struct rtems_termios_tty *) oc->iop->data1;
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_SHARED_CONSOLE_GENERIC_H */
diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h b/bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h
new file mode 100644
index 0000000000..c70f36d13b
--- /dev/null
+++ b/bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h
@@ -0,0 +1,64 @@
+/**
+ * @file
+ *
+ * @brief Console LINFlexD API.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H
+#define LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H
+
+#include "console-generic.h"
+
+#undef CR0
+#undef CR1
+#undef CR2
+#undef CR3
+
+#include <mpc55xx/regs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef MPC55XX_HAS_LINFLEX
+
+extern const console_generic_callbacks mpc55xx_linflex_callbacks;
+
+typedef struct {
+ volatile LINFLEX_tag *regs;
+ struct rtems_termios_tty *tty;
+ rtems_vector_number irq_rxi;
+ rtems_vector_number irq_txi;
+ rtems_vector_number irq_err;
+ volatile SIU_PCR_tag *tx_pcr_register;
+ uint8_t tx_pa_value:2;
+ volatile SIU_PCR_tag *rx_pcr_register;
+ volatile SIUL_PSMI_8B_tag *rx_psmi_register;
+ uint8_t rx_padsel_value:4;
+ int transmit_nest_level;
+ bool transmit_in_progress;
+} mpc55xx_linflex_context;
+
+extern mpc55xx_linflex_context mpc55xx_linflex_devices [];
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H */
diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/irq.h b/bsps/powerpc/mpc55xxevb/include/bsp/irq.h
new file mode 100644
index 0000000000..4efa92219e
--- /dev/null
+++ b/bsps/powerpc/mpc55xxevb/include/bsp/irq.h
@@ -0,0 +1,499 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief IRQ
+ */
+
+/*
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_IRQ_H
+#define LIBBSP_POWERPC_IRQ_H
+
+#include <rtems/irq-extension.h>
+#include <rtems/irq.h>
+
+#include <bspopts.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*
+ * Interrupt numbers
+ */
+
+#define MPC55XX_IRQ_INVALID 0x10000U
+#define MPC55XX_IRQ_MIN 0U
+
+/* Software interrupts */
+#define MPC55XX_IRQ_SOFTWARE_MIN 0U
+#define MPC55XX_IRQ_SOFTWARE_MAX 7U
+#define MPC55XX_IRQ_SOFTWARE_GET_INDEX(v) (v)
+#define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i)
+#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U)
+
+#if MPC55XX_CHIP_FAMILY == 551
+ #define MPC55XX_IRQ_MAX 293U
+
+ /* eDMA */
+ #define MPC55XX_IRQ_EDMA_ERROR(group) \
+ ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
+ #define MPC55XX_IRQ_EDMA(ch) \
+ ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
+
+ /* I2C */
+ #define MPC55XX_IRQ_I2C(mod) \
+ ((mod) == 0 ? 48U : MPC55XX_IRQ_INVALID)
+
+ /* SIU external interrupts */
+ #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U
+
+ /* PIT */
+ #define MPC55XX_IRQ_RTI 148U
+ #define MPC55XX_IRQ_PIT(timer) (148U + (timer))
+
+ /* eTPU */
+ #define MPC55XX_IRQ_ETPU_BASE(mod) MPC55XX_IRQ_INVALID
+
+ /* DSPI */
+ #define MPC55XX_IRQ_DSPI_BASE(mod) \
+ ((mod) == 0 ? 117U : \
+ ((mod) == 1 ? 122U : \
+ ((mod) == 2 ? 274U : \
+ ((mod) == 3 ? 279U : MPC55XX_IRQ_INVALID))))
+
+ /* eMIOS */
+ #define MPC55XX_IRQ_EMIOS(ch) \
+ ((unsigned) (ch) < 24U ? 58U + (ch) : MPC55XX_IRQ_INVALID)
+
+ /* eQADC */
+ #define MPC55XX_IRQ_EQADC_BASE(mod) \
+ ((mod) == 0 ? 82U : MPC55XX_IRQ_INVALID)
+
+ /* eSCI */
+ #define MPC55XX_IRQ_ESCI(mod) \
+ ((mod) == 0 ? 113U : \
+ ((mod) == 1 ? 114U : \
+ ((mod) == 2 ? 115U : \
+ ((mod) == 3 ? 116U : \
+ ((mod) == 4 ? 270U : \
+ ((mod) == 5 ? 271U : \
+ ((mod) == 6 ? 272U : \
+ ((mod) == 7 ? 273U : MPC55XX_IRQ_INVALID))))))))
+
+ /* FlexCAN */
+ #define MPC55XX_IRQ_CAN_BASE(mod) \
+ ((mod) == 0 ? 127U : \
+ ((mod) == 1 ? 157U : \
+ ((mod) == 2 ? 178U : \
+ ((mod) == 3 ? 199U : \
+ ((mod) == 4 ? 220U : \
+ ((mod) == 5 ? 241U : MPC55XX_IRQ_INVALID))))))
+
+ /* FlexRay */
+ #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
+ ((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID)
+#elif MPC55XX_CHIP_FAMILY == 564
+ #define MPC55XX_IRQ_MAX 255U
+
+ /* eDMA */
+ #define MPC55XX_IRQ_EDMA_ERROR(group) \
+ ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
+ #define MPC55XX_IRQ_EDMA(ch) \
+ ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
+
+ /* SWT */
+ #define MPC55XX_IRQ_SWT_0 28U
+ #define MPC55XX_IRQ_SWT_1 29U
+
+ /* STM */
+ #define MPC55XX_IRQ_STM_CHANNEL(ch) ((ch) + 30U)
+
+ /* ECSM */
+ #define MPC55XX_IRQ_ECSM_FAS 9U
+ #define MPC55XX_IRQ_ECSM_NCE 35U
+ #define MPC55XX_IRQ_ECSM_COR 36U
+
+ /* MC */
+ #define MPC55XX_IRQ_MC_ME_SAFE_MODE 51U
+ #define MPC55XX_IRQ_MC_ME_MODE_TRANSITION 52U
+ #define MPC55XX_IRQ_MC_ME_INVALID_MODE 53U
+ #define MPC55XX_IRQ_MC_ME_INVALID_CONFIG 54U
+ #define MPC55XX_IRQ_MC_RGM_FRAE 56U
+
+ /* XOSC */
+ #define MPC55XX_IRQ_XOSC 57U
+
+ /* PIT */
+ #define MPC55XX_IRQ_PIT_CHANNEL(ch) \
+ ((ch) == 3 ? 127U : ((ch) + 59U))
+
+ /* SIU external interrupts */
+ #define MPC55XX_IRQ_SIU_EXTERNAL_0 41U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_1 42U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_2 43U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_3 44U
+
+ /* ADC */
+ #define MPC55XX_IRQ_ADC_BASE(mod) \
+ ((mod) == 0 ? 62U : \
+ ((mod) == 1 ? 82U : MPC55XX_IRQ_INVALID))
+
+ /* DSPI */
+ #define MPC55XX_IRQ_DSPI_BASE(mod) \
+ ((mod) == 0 ? 74U : \
+ ((mod) == 1 ? 94U : \
+ ((mod) == 2 ? 114U : MPC55XX_IRQ_INVALID)))
+
+ /* FlexCAN */
+ #define MPC55XX_IRQ_CAN_BASE(mod) \
+ ((mod) == 0 ? 65U : \
+ ((mod) == 1 ? 85U : MPC55XX_IRQ_INVALID))
+
+ /* FlexPWM */
+ #define MPC55XX_IRQ_FLEXPWM_BASE(mod) \
+ ((mod) == 0 ? 179U : \
+ ((mod) == 1 ? 233U : MPC55XX_IRQ_INVALID))
+
+ /* FlexRay */
+ #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
+ ((mod) == 0 ? 131U : MPC55XX_IRQ_INVALID)
+
+ /* LINFlexD */
+ #define MPC55XX_IRQ_LINFLEX_BASE(mod) \
+ ((mod) == 0 ? 79U : \
+ ((mod) == 1 ? 99U : MPC55XX_IRQ_INVALID))
+
+ /* eTimer */
+ #define MPC55XX_IRQ_ETIMER_BASE(mod) \
+ ((mod) == 0 ? 157U : \
+ ((mod) == 1 ? 168U : \
+ ((mod) == 2 ? 222U : MPC55XX_IRQ_INVALID)))
+
+ /* CTU */
+ #define MPC55XX_IRQ_CTU_MRS 193U
+ #define MPC55XX_IRQ_CTU_T(idx) ((idx) + 194U)
+ #define MPC55XX_IRQ_CTU_FIFO(idx) ((idx) + 202U)
+ #define MPC55XX_IRQ_CTU_ADC 206U
+ #define MPC55XX_IRQ_CTU_ERR 207U
+
+ /* SEMA */
+ #define MPC55XX_IRQ_SEMA_0 247U
+ #define MPC55XX_IRQ_SEMA_1 248U
+
+ /* FCCU */
+ #define MPC55XX_IRQ_FCCU_ALRM 250U
+ #define MPC55XX_IRQ_FCCU_CFG_TO 251U
+ #define MPC55XX_IRQ_FCCU_SC_RCC0_F 252U
+ #define MPC55XX_IRQ_FCCU_SC_RCC1_F 253U
+
+ /* PMU */
+ #define MPC55XX_IRQ_PMU 254U
+
+ /* SWG */
+ #define MPC55XX_IRQ_SWG 255U
+#elif MPC55XX_CHIP_FAMILY == 566
+ #define MPC55XX_IRQ_MAX 315U
+
+ /* eDMA */
+ #define MPC55XX_IRQ_EDMA_ERROR(group) \
+ ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
+ #define MPC55XX_IRQ_EDMA(ch) \
+ ((unsigned) (ch) < 32U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
+
+ /* PIT */
+ #define MPC55XX_IRQ_PIT_CHANNEL(ch) \
+ ((unsigned) (ch) < 9U ? 148U + (ch) : MPC55XX_IRQ_INVALID)
+
+ /* SIU external interrupts */
+ #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
+
+ /* eMIOS */
+ #define MPC55XX_IRQ_EMIOS(ch) \
+ ((unsigned) (ch) < 24U ? 58U + (ch) : \
+ ((unsigned) (ch) < 32U ? 262U + (ch) : MPC55XX_IRQ_INVALID))
+
+ /* eSCI */
+ #define MPC55XX_IRQ_ESCI(mod) \
+ ((unsigned) (mod) < 4U ? 113U + (mod) : \
+ ((unsigned) (mod) < 8U ? 270U + (mod) : \
+ ((unsigned) (mod) < 12U ? 306U + (mod) : MPC55XX_IRQ_INVALID)))
+#else
+ #if MPC55XX_CHIP_FAMILY == 555
+ #define MPC55XX_IRQ_MAX 307U
+ #elif MPC55XX_CHIP_FAMILY == 556
+ #define MPC55XX_IRQ_MAX 360U
+ #elif MPC55XX_CHIP_FAMILY == 567
+ #define MPC55XX_IRQ_MAX 479U
+ #else
+ #error "unsupported chip type"
+ #endif
+
+ /* eDMA */
+ #define MPC55XX_IRQ_EDMA_ERROR(group) \
+ ((group) == 0 ? 10U : \
+ ((group) == 1 ? 210U : \
+ ((group) == 2 ? 425U : MPC55XX_IRQ_INVALID)))
+ #define MPC55XX_IRQ_EDMA(ch) \
+ ((unsigned) (ch) < 32U ? 11U + (ch) : \
+ ((unsigned) (ch) < 64U ? 179U + (ch) : \
+ ((unsigned) (ch) < 96U ? 362U + (ch) : MPC55XX_IRQ_INVALID)))
+
+ /* I2C */
+ #define MPC55XX_IRQ_I2C(mod) MPC55XX_IRQ_INVALID
+
+ /* SIU external interrupts */
+ #define MPC55XX_IRQ_SIU_EXTERNAL_0 46U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_1 47U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_2 48U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_3 49U
+ #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U
+
+ /* PIT */
+ #define MPC55XX_IRQ_RTI 305U
+ #define MPC55XX_IRQ_PIT(ch) (301U + (ch))
+
+ /* eTPU */
+ #define MPC55XX_IRQ_ETPU_BASE(mod) \
+ ((mod) == 0 ? 67U : \
+ ((mod) == 1 ? 243U : MPC55XX_IRQ_INVALID))
+
+ /* DSPI */
+ #define MPC55XX_IRQ_DSPI_BASE(mod) \
+ ((mod) == 0 ? 275U : \
+ ((mod) == 1 ? 131U : \
+ ((mod) == 2 ? 136U : \
+ ((mod) == 3 ? 141U : MPC55XX_IRQ_INVALID))))
+
+ /* eMIOS */
+ #define MPC55XX_IRQ_EMIOS(ch) \
+ ((unsigned) (ch) < 16U ? 51U + (ch) : \
+ ((unsigned) (ch) < 24U ? 186U + (ch) : \
+ ((unsigned) (ch) < 32U ? 435U + (ch) : MPC55XX_IRQ_INVALID)))
+
+ /* eQADC */
+ #define MPC55XX_IRQ_EQADC_BASE(mod) \
+ ((mod) == 0 ? 100U : \
+ ((mod) == 1 ? 394U : MPC55XX_IRQ_INVALID))
+
+ /* eSCI */
+ #define MPC55XX_IRQ_ESCI(mod) \
+ ((mod) == 0 ? 146U : \
+ ((mod) == 1 ? 149U : \
+ ((mod) == 2 ? 473U : MPC55XX_IRQ_INVALID)))
+
+ /* FlexCAN */
+ #define MPC55XX_IRQ_CAN_BASE(mod) \
+ ((mod) == 0 ? 152U : \
+ ((mod) == 1 ? 280U : \
+ ((mod) == 2 ? 173U : \
+ ((mod) == 3 ? 308U : \
+ ((mod) == 4 ? 329U : MPC55XX_IRQ_INVALID)))))
+
+ /* FlexRay */
+ #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
+ ((mod) == 0 ? 350U : MPC55XX_IRQ_INVALID)
+#endif
+
+#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
+
+/* ADC */
+#define MPC55XX_IRQ_ADC_EOC(mod) \
+ (MPC55XX_IRQ_ADC_BASE(mod) + 0U)
+#define MPC55XX_IRQ_ADC_ER(mod) \
+ (MPC55XX_IRQ_ADC_BASE(mod) + 1U)
+#define MPC55XX_IRQ_ADC_WD(mod) \
+ (MPC55XX_IRQ_ADC_BASE(mod) + 2U)
+
+/* eTimer */
+#define MPC55XX_IRQ_ETIMER_TC(mod, ch) \
+ (MPC55XX_IRQ_ETIMER_BASE(mod) + (ch))
+#define MPC55XX_IRQ_ETIMER_WTIF(mod) \
+ (MPC55XX_IRQ_ETIMER_BASE(mod) + 8U)
+#define MPC55XX_IRQ_ETIMER_RCF(mod) \
+ (MPC55XX_IRQ_ETIMER_BASE(mod) + 10U)
+
+/* eTPU */
+#define MPC55XX_IRQ_ETPU(mod) \
+ (MPC55XX_IRQ_ETPU_BASE(mod) + 0U)
+#define MPC55XX_IRQ_ETPU_CHANNEL(mod, ch) \
+ (MPC55XX_IRQ_ETPU_BASE(mod) + 1U + (ch))
+
+/* DSPI */
+#define MPC55XX_IRQ_DSPI_TFUF_RFOF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 0U)
+#define MPC55XX_IRQ_DSPI_EOQF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 1U)
+#define MPC55XX_IRQ_DSPI_TFFF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 2U)
+#define MPC55XX_IRQ_DSPI_TCF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 3U)
+#define MPC55XX_IRQ_DSPI_RFDF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 4U)
+
+/* eQADC */
+#define MPC55XX_IRQ_EQADC_TORF_RFOF_CFUF(mod) \
+ (MPC55XX_IRQ_EQADC_BASE(mod) + 0U)
+#define MPC55XX_IRQ_EQADC_NCF(mod, fifo) \
+ (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 0U)
+#define MPC55XX_IRQ_EQADC_PF(mod, fifo) \
+ (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 1U)
+#define MPC55XX_IRQ_EQADC_EOQF(mod, fifo) \
+ (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 2U)
+#define MPC55XX_IRQ_EQADC_CFFF(mod, fifo) \
+ (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 3U)
+#define MPC55XX_IRQ_EQADC_RFDF(mod, fifo) \
+ (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 4U)
+
+/* FlexCAN */
+#if MPC55XX_CHIP_FAMILY == 564
+ #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
+ #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
+ #define MPC55XX_IRQ_CAN_BUF_0_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
+ #define MPC55XX_IRQ_CAN_BUF_4_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
+ #define MPC55XX_IRQ_CAN_BUF_8_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
+ #define MPC55XX_IRQ_CAN_BUF_12_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
+ #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
+#else
+ #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U)
+ #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U)
+ #define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U)
+ #define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U)
+ #define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U)
+ #define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U)
+ #define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U)
+ #define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U)
+ #define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U)
+ #define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U)
+ #define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
+ #define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U)
+ #define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U)
+ #define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U)
+ #define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U)
+ #define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U)
+ #define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U)
+ #define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U)
+ #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U)
+ #define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U)
+#endif
+
+/* FlexPWM */
+#define MPC55XX_IRQ_FLEXPWM_RF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 0U)
+#define MPC55XX_IRQ_FLEXPWM_COF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 1U)
+#define MPC55XX_IRQ_FLEXPWM_CAF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 2U)
+#define MPC55XX_IRQ_FLEXPWM_FFLAG(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 12U)
+#define MPC55XX_IRQ_FLEXPWM_REF(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 13U)
+
+/* FlexRay */
+#if MPC55XX_CHIP_FAMILY == 564
+ #define MPC55XX_IRQ_FLEXRAY_LRNEIF_DRNEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
+ #define MPC55XX_IRQ_FLEXRAY_LRCEIF_DRCEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
+ #define MPC55XX_IRQ_FLEXRAY_FAFAIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
+ #define MPC55XX_IRQ_FLEXRAY_FAFVIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
+ #define MPC55XX_IRQ_FLEXRAY_WUPIEF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
+ #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
+ #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
+ #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
+ #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 8U)
+ #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 9U)
+#else
+ #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
+ #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
+ #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
+ #define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
+ #define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
+ #define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
+ #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
+ #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
+#endif
+
+/* LINFlexD */
+#define MPC55XX_IRQ_LINFLEX_RXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 0U)
+#define MPC55XX_IRQ_LINFLEX_TXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 1U)
+#define MPC55XX_IRQ_LINFLEX_ERR(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 2U)
+
+/* Checks */
+#define MPC55XX_IRQ_IS_VALID(v) \
+ ((v) >= MPC55XX_IRQ_MIN && \
+ (v) <= MPC55XX_IRQ_MAX)
+#define MPC55XX_IRQ_IS_SOFTWARE(v) \
+ ((v) >= MPC55XX_IRQ_SOFTWARE_MIN && \
+ (v) <= MPC55XX_IRQ_SOFTWARE_MAX)
+
+/*
+ * Interrupt controller
+ */
+
+#define MPC55XX_INTC_MIN_PRIORITY 1U
+#define MPC55XX_INTC_MAX_PRIORITY 15U
+#define MPC55XX_INTC_DISABLED_PRIORITY 0U
+#define MPC55XX_INTC_INVALID_PRIORITY (MPC55XX_INTC_MAX_PRIORITY + 1)
+#define MPC55XX_INTC_DEFAULT_PRIORITY (MPC55XX_INTC_MIN_PRIORITY + 1)
+#define MPC55XX_INTC_IS_VALID_PRIORITY(p) \
+ ((p) >= MPC55XX_INTC_DISABLED_PRIORITY && (p) <= MPC55XX_INTC_MAX_PRIORITY)
+
+rtems_status_code mpc55xx_interrupt_handler_install(
+ rtems_vector_number vector,
+ const char *info,
+ rtems_option options,
+ unsigned priority,
+ rtems_interrupt_handler handler,
+ void *arg
+);
+
+rtems_status_code mpc55xx_intc_get_priority(
+ rtems_vector_number vector,
+ unsigned *priority
+);
+
+rtems_status_code mpc55xx_intc_set_priority(
+ rtems_vector_number vector,
+ unsigned priority
+);
+
+rtems_status_code mpc55xx_intc_raise_software_irq(rtems_vector_number vector);
+
+rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector);
+
+/**
+ * @addtogroup bsp_interrupt
+ *
+ * @{
+ */
+
+#define BSP_INTERRUPT_VECTOR_MIN MPC55XX_IRQ_MIN
+
+#define BSP_INTERRUPT_VECTOR_MAX MPC55XX_IRQ_MAX
+
+#ifdef BSP_INTERRUPT_HANDLER_TABLE_SIZE
+ #define BSP_INTERRUPT_USE_INDEX_TABLE
+ #define BSP_INTERRUPT_NO_HEAP_USAGE
+#endif
+
+/** @} */
+
+/* Legacy API */
+#define MPC55XX_IRQ_EDMA_GET_REQUEST(ch) MPC55XX_IRQ_EDMA(ch)
+#define MPC55XX_IRQ_EMIOS_GET_REQUEST(ch) MPC55XX_IRQ_EMIOS(ch)
+
+#ifdef __cplusplus
+};
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_IRQ_H */
diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h b/bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h
new file mode 100644
index 0000000000..b432b9cecd
--- /dev/null
+++ b/bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h
@@ -0,0 +1,170 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief Low-level configuration.
+ */
+
+/*
+ * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H
+#define LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H
+
+#include <stddef.h>
+
+#include <libcpu/powerpc-utility.h>
+
+#include <bsp/start.h>
+
+#include <mpc55xx/regs.h>
+#include <mpc55xx/regs-mmu.h>
+#include <mpc55xx/siu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef struct {
+ uint32_t index : 10;
+ uint32_t count : 10;
+ uint32_t output : 1;
+ union SIU_PCR_tag pcr;
+} mpc55xx_siu_pcr_config;
+
+extern BSP_START_DATA_SECTION const mpc55xx_siu_pcr_config
+ mpc55xx_start_config_siu_pcr [];
+
+extern BSP_START_DATA_SECTION const size_t
+ mpc55xx_start_config_siu_pcr_count [];
+
+extern BSP_START_DATA_SECTION const struct
+ MMU_tag mpc55xx_start_config_mmu_early [];
+
+extern BSP_START_DATA_SECTION const size_t
+ mpc55xx_start_config_mmu_early_count [];
+
+extern BSP_START_DATA_SECTION const struct
+ MMU_tag mpc55xx_start_config_mmu [];
+
+extern BSP_START_DATA_SECTION const size_t
+ mpc55xx_start_config_mmu_count [];
+
+#ifdef MPC55XX_HAS_FMPLL
+ typedef struct {
+ union FMPLL_SYNCR_tag syncr_tmp;
+ union FMPLL_SYNCR_tag syncr_final;
+ } mpc55xx_clock_config;
+#endif
+
+#ifdef MPC55XX_HAS_FMPLL_ENHANCED
+ typedef struct {
+ union FMPLL_ESYNCR2_tag esyncr2_tmp;
+ union FMPLL_ESYNCR2_tag esyncr2_final;
+ union FMPLL_ESYNCR1_tag esyncr1_final;
+ } mpc55xx_clock_config;
+#endif
+
+#ifdef MPC55XX_HAS_MODE_CONTROL
+ typedef struct {
+ struct {
+ PLLD_CR_32B_tag cr;
+ PLLD_MR_32B_tag mr;
+ } fmpll [2];
+ CGM_OC_EN_32B_tag oc_en;
+ CGM_OCDS_SC_32B_tag ocds_sc;
+ CGM_SC_DC0_3_32B_tag sc_dc0_3;
+ CGM_AUXCLK_tag auxclk [5];
+ } mpc55xx_clock_config;
+#endif
+
+extern BSP_START_DATA_SECTION const mpc55xx_clock_config
+ mpc55xx_start_config_clock [];
+
+#ifdef MPC55XX_HAS_EBI
+ typedef struct {
+ union EBI_MCR_tag ebi_mcr;
+ uint32_t siu_eccr_ebdf;
+ } mpc55xx_ebi_config;
+
+ extern BSP_START_DATA_SECTION const mpc55xx_ebi_config
+ mpc55xx_start_config_ebi [];
+
+ extern BSP_START_DATA_SECTION const size_t
+ mpc55xx_start_config_ebi_count [];
+
+ extern BSP_START_DATA_SECTION const struct EBI_CS_tag
+ mpc55xx_start_config_ebi_cs [];
+
+ extern BSP_START_DATA_SECTION const size_t
+ mpc55xx_start_config_ebi_cs_count [];
+
+ extern BSP_START_DATA_SECTION const struct EBI_CAL_CS_tag
+ mpc55xx_start_config_ebi_cal_cs [];
+
+ extern BSP_START_DATA_SECTION const size_t
+ mpc55xx_start_config_ebi_cal_cs_count [];
+#endif
+
+/**
+ * @brief Start prologue.
+ *
+ * In case the BSP enabled the MPC55XX_ENABLE_START_PROLOGUE option, then this
+ * function will be called directly after the Boot Assist Module (BAM) jumped
+ * to the start entry defined by the reset configuration.
+ *
+ * This function executes in the context initialized by the BAM. There exists
+ * no valid stack pointer and the internal RAM has an invalid ECC state.
+ *
+ * The default implementation does nothing. The application may provide its
+ * own implementation.
+ */
+void mpc55xx_start_prologue(void);
+
+void mpc55xx_start_early(void);
+
+void mpc55xx_start_flash(void);
+
+void mpc55xx_start_cache(void);
+
+void mpc55xx_start_clock(void);
+
+void mpc55xx_start_watchdog(void);
+
+void mpc55xx_start_mmu_apply_config(const struct MMU_tag *config, size_t count);
+
+uint32_t mpc55xx_get_system_clock(void);
+
+LINKER_SYMBOL(bsp_ram_start)
+LINKER_SYMBOL(bsp_ram_end)
+LINKER_SYMBOL(bsp_ram_size)
+
+LINKER_SYMBOL(bsp_ram_1_start)
+LINKER_SYMBOL(bsp_ram_1_end)
+LINKER_SYMBOL(bsp_ram_1_size)
+
+LINKER_SYMBOL(bsp_rom_start)
+LINKER_SYMBOL(bsp_rom_end)
+LINKER_SYMBOL(bsp_rom_size)
+
+#ifdef MPC55XX_BOOTFLAGS
+ extern uint32_t mpc55xx_bootflag_0 [];
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H */
diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h b/bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h
new file mode 100644
index 0000000000..e4366b039c
--- /dev/null
+++ b/bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h
@@ -0,0 +1,704 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief SMSC - LAN9218i
+ */
+
+/*
+ * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+
+/**
+ * @name Memory Map
+ * @{
+ */
+
+typedef struct {
+ uint32_t rx_fifo_data;
+ uint32_t rx_fifo_data_aliases [7];
+ uint32_t tx_fifo_data;
+ uint32_t tx_fifo_data_aliases [7];
+ uint32_t rx_fifo_status;
+ uint32_t rx_fifo_status_peek;
+ uint32_t tx_fifo_status;
+ uint32_t tx_fifo_status_peek;
+ uint32_t id_rev;
+ uint32_t irq_cfg;
+ uint32_t int_sts;
+ uint32_t int_en;
+ uint32_t reserved_0;
+ uint32_t byte_test;
+ uint32_t fifo_int;
+ uint32_t rx_cfg;
+ uint32_t tx_cfg;
+ uint32_t hw_cfg;
+ uint32_t rx_dp_ctl;
+ uint32_t rx_fifo_inf;
+ uint32_t tx_fifo_inf;
+ uint32_t pmt_ctrl;
+ uint32_t gpio_cfg;
+ uint32_t gpt_cfg;
+ uint32_t gpt_cnt;
+ uint32_t reserved_1;
+ uint32_t word_swap;
+ uint32_t free_run;
+ uint32_t rx_drop;
+ uint32_t mac_csr_cmd;
+ uint32_t mac_csr_data;
+ uint32_t afc_cfg;
+ uint32_t e2p_cmd;
+ uint32_t e2p_data;
+} smsc9218i_registers;
+
+/*
+ * SMSC9218 registers are accessed little-endian (address 0x3fff8000, A22 used
+ * as END_SEL).
+ */
+#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
+ volatile smsc9218i_registers *const smsc9218i =
+ (volatile smsc9218i_registers *) 0x3fff8000;
+ volatile smsc9218i_registers *const smsc9218i_dma =
+ (volatile smsc9218i_registers *) 0x3fff8200;
+#else
+ volatile smsc9218i_registers *const smsc9218i =
+ (volatile smsc9218i_registers *) 0x3fff8000;
+ volatile smsc9218i_registers *const smsc9218i_dma =
+ (volatile smsc9218i_registers *) 0x3fff8000;
+#endif
+
+/** @} */
+
+#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
+ #define SMSC9218I_BIT_POS(pos) (pos)
+#else
+ #define SMSC9218I_BIT_POS(pos) \
+ ((pos) > 15 ? \
+ ((pos) > 23 ? (pos) - 24 : (pos) - 8) \
+ : ((pos) > 7 ? (pos) + 8 : (pos) + 24))
+#endif
+
+#define SMSC9218I_FLAG(pos) \
+ (1U << SMSC9218I_BIT_POS(pos))
+
+#define SMSC9218I_FIELD_8(val, pos) \
+ (((val) & 0xff) << SMSC9218I_BIT_POS(pos))
+
+#define SMSC9218I_GET_FIELD_8(reg, pos) \
+ (((reg) >> SMSC9218I_BIT_POS(pos)) & 0xff)
+
+#define SMSC9218I_FIELD_16(val, pos) \
+ (SMSC9218I_FIELD_8((val) >> 8, (pos) + 8) \
+ | SMSC9218I_FIELD_8((val), pos))
+
+#define SMSC9218I_GET_FIELD_16(reg, pos) \
+ ((SMSC9218I_GET_FIELD_8(reg, (pos) + 8) << 8) \
+ | SMSC9218I_GET_FIELD_8(reg, pos))
+
+#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT
+ #define SMSC9218I_SWAP(val) (val)
+#else
+ #define SMSC9218I_SWAP(val) \
+ ((((val) >> 24) & 0xff) \
+ | ((((val) >> 16) & 0xff) << 8) \
+ | ((((val) >> 8) & 0xff) << 16) \
+ | (((val) & 0xff) << 24))
+#endif
+
+/**
+ * @name Receive Status
+ * @{
+ */
+
+#define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30)
+#define SMSC9218I_RX_STS_GET_LENGTH(reg) (SMSC9218I_GET_FIELD_16(reg, 16) & 0x3fff)
+#define SMSC9218I_RX_STS_ERROR SMSC9218I_FLAG(15)
+#define SMSC9218I_RX_STS_BROADCAST SMSC9218I_FLAG(13)
+#define SMSC9218I_RX_STS_ERROR_LENGTH SMSC9218I_FLAG(12)
+#define SMSC9218I_RX_STS_ERROR_RUNT_FRAME SMSC9218I_FLAG(11)
+#define SMSC9218I_RX_STS_MULTICAST SMSC9218I_FLAG(10)
+#define SMSC9218I_RX_STS_ERROR_TOO_LONG SMSC9218I_FLAG(7)
+#define SMSC9218I_RX_STS_ERROR_COLLISION SMSC9218I_FLAG(6)
+#define SMSC9218I_RX_STS_TYPE SMSC9218I_FLAG(5)
+#define SMSC9218I_RX_STS_WATCHDOG SMSC9218I_FLAG(4)
+#define SMSC9218I_RX_STS_ERROR_MII SMSC9218I_FLAG(3)
+#define SMSC9218I_RX_STS_DRIBBLING_BIT SMSC9218I_FLAG(2)
+#define SMSC9218I_RX_STS_ERROR_CRC SMSC9218I_FLAG(1)
+
+/** @} */
+
+/**
+ * @name Transmit Status
+ * @{
+ */
+
+#define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
+#define SMSC9218I_TX_STS_ERROR SMSC9218I_FLAG(15)
+#define SMSC9218I_TX_STS_ERROR_LOSS_OF_CARRIER SMSC9218I_FLAG(11)
+#define SMSC9218I_TX_STS_ERROR_NO_CARRIER SMSC9218I_FLAG(10)
+#define SMSC9218I_TX_STS_ERROR_LATE_COLLISION SMSC9218I_FLAG(9)
+#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_COLLISIONS SMSC9218I_FLAG(8)
+#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_DEFERRAL SMSC9218I_FLAG(2)
+#define SMSC9218I_TX_STS_ERROR_DEFERRED SMSC9218I_FLAG(0)
+
+/** @} */
+
+/**
+ * @name Transmit Command A
+ * @{
+ */
+
+#define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31)
+#define SMSC9218I_TX_A_END_ALIGN_4 0
+#define SMSC9218I_TX_A_END_ALIGN_16 SMSC9218I_FLAG(24)
+#define SMSC9218I_TX_A_END_ALIGN_32 SMSC9218I_FLAG(25)
+#define SMSC9218I_TX_A_DOFF(val) SMSC9218I_FIELD_8(val, 16)
+#define SMSC9218I_TX_A_FIRST SMSC9218I_FLAG(13)
+#define SMSC9218I_TX_A_LAST SMSC9218I_FLAG(12)
+#define SMSC9218I_TX_A_FRAGMENT_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
+
+/** @} */
+
+/**
+ * @name Transmit Command B
+ * @{
+ */
+
+#define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16)
+#define SMSC9218I_TX_B_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
+#define SMSC9218I_TX_B_DISABLE_CRC SMSC9218I_FLAG(13)
+#define SMSC9218I_TX_B_DISABLE_PAD SMSC9218I_FLAG(12)
+#define SMSC9218I_TX_B_FRAME_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
+
+/** @} */
+
+/**
+ * @name Chip ID and Revision
+ * @{
+ */
+
+#define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16)
+#define SMSC9218I_ID_REV_GET_REV(reg) SMSC9218I_GET_FIELD_16(reg, 0)
+#define SMSC9218I_ID_REV_ID_CHIP_118 0x0118U
+#define SMSC9218I_ID_REV_ID_CHIP_218 0x118aU
+
+/** @} */
+
+/**
+ * @name Interrupt Configuration
+ * @{
+ */
+
+#define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24)
+#define SMSC9218I_IRQ_CFG_GET_INT_DEAS(reg) SMSC9218I_GET_FIELD_8(reg, 24)
+#define SMSC9218I_IRQ_CFG_INT_DEAS_CLR SMSC9218I_FLAG(14)
+#define SMSC9218I_IRQ_CFG_INT_DEAS_STS SMSC9218I_FLAG(13)
+#define SMSC9218I_IRQ_CFG_IRQ_INT SMSC9218I_FLAG(12)
+#define SMSC9218I_IRQ_CFG_IRQ_EN SMSC9218I_FLAG(8)
+#define SMSC9218I_IRQ_CFG_IRQ_POL SMSC9218I_FLAG(4)
+#define SMSC9218I_IRQ_CFG_IRQ_TYPE SMSC9218I_FLAG(0)
+
+/** @} */
+
+/**
+ * @name Interrupt Enable and Status
+ * @{
+ */
+
+#define SMSC9218I_INT_SW SMSC9218I_FLAG(31)
+#define SMSC9218I_INT_TXSTOP SMSC9218I_FLAG(25)
+#define SMSC9218I_INT_RXSTOP SMSC9218I_FLAG(24)
+#define SMSC9218I_INT_RXDFH SMSC9218I_FLAG(23)
+#define SMSC9218I_INT_TIOC SMSC9218I_FLAG(21)
+#define SMSC9218I_INT_RXD SMSC9218I_FLAG(20)
+#define SMSC9218I_INT_GPT SMSC9218I_FLAG(19)
+#define SMSC9218I_INT_PHY SMSC9218I_FLAG(18)
+#define SMSC9218I_INT_PME SMSC9218I_FLAG(17)
+#define SMSC9218I_INT_TXSO SMSC9218I_FLAG(16)
+#define SMSC9218I_INT_RWT SMSC9218I_FLAG(15)
+#define SMSC9218I_INT_RXE SMSC9218I_FLAG(14)
+#define SMSC9218I_INT_TXE SMSC9218I_FLAG(13)
+#define SMSC9218I_INT_TDFO SMSC9218I_FLAG(10)
+#define SMSC9218I_INT_TDFA SMSC9218I_FLAG(9)
+#define SMSC9218I_INT_TSFF SMSC9218I_FLAG(8)
+#define SMSC9218I_INT_TSFL SMSC9218I_FLAG(7)
+#define SMSC9218I_INT_RSFF SMSC9218I_FLAG(4)
+#define SMSC9218I_INT_RSFL SMSC9218I_FLAG(3)
+#define SMSC9218I_INT_GPIO2 SMSC9218I_FLAG(2)
+#define SMSC9218I_INT_GPIO1 SMSC9218I_FLAG(1)
+#define SMSC9218I_INT_GPIO0 SMSC9218I_FLAG(0)
+
+/** @} */
+
+/**
+ * @name Byte Order Testing
+ * @{
+ */
+
+#define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U)
+
+/** @} */
+
+/**
+ * @name FIFO Level Interrupts
+ * @{
+ */
+
+#define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24)
+#define SMSC9218I_FIFO_INT_GET_TDAL(reg) SMSC9218I_GET_FIELD_8(reg, 24)
+#define SMSC9218I_FIFO_INT_TSL(val) SMSC9218I_FIELD_8(val, 16)
+#define SMSC9218I_FIFO_INT_GET_TSL(reg) SMSC9218I_GET_FIELD_8(reg, 16)
+#define SMSC9218I_FIFO_INT_RSL(val) SMSC9218I_FIELD_8(val, 0)
+#define SMSC9218I_FIFO_INT_GET_RSL(reg) SMSC9218I_GET_FIELD_8(reg, 0)
+
+/** @} */
+
+/**
+ * @name Receive Configuration
+ * @{
+ */
+
+#define SMSC9218I_RX_CFG_END_ALIGN_4 0
+#define SMSC9218I_RX_CFG_END_ALIGN_16 SMSC9218I_FLAG(30)
+#define SMSC9218I_RX_CFG_END_ALIGN_32 SMSC9218I_FLAG(31)
+#define SMSC9218I_RX_CFG_DMA_CNT(val) SMSC9218I_FIELD_8(val, 24)
+#define SMSC9218I_RX_CFG_GET_DMA_CNT(reg) SMSC9218I_GET_FIELD_8(reg, 24)
+#define SMSC9218I_RX_CFG_DUMP SMSC9218I_FLAG(15)
+#define SMSC9218I_RX_CFG_DOFF(val) SMSC9218I_FIELD_8(val, 8)
+#define SMSC9218I_RX_CFG_GET_DOFF(reg) SMSC9218I_GET_FIELD_8(reg, 8)
+
+/** @} */
+
+/**
+ * @name Transmit Configuration
+ * @{
+ */
+
+#define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15)
+#define SMSC9218I_TX_CFG_DDUMP SMSC9218I_FLAG(14)
+#define SMSC9218I_TX_CFG_SAO SMSC9218I_FLAG(2)
+#define SMSC9218I_TX_CFG_ON SMSC9218I_FLAG(1)
+#define SMSC9218I_TX_CFG_STOP SMSC9218I_FLAG(0)
+
+/** @} */
+
+/**
+ * @name Hardware Configuration
+ * @{
+ */
+
+#define SMSC9218I_HW_CFG_LED_3 SMSC9218I_FLAG(30)
+#define SMSC9218I_HW_CFG_LED_2 SMSC9218I_FLAG(29)
+#define SMSC9218I_HW_CFG_LED_1 SMSC9218I_FLAG(28)
+#define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24)
+#define SMSC9218I_HW_CFG_MBO SMSC9218I_FLAG(20)
+#define SMSC9218I_HW_CFG_TX_FIF_SZ(val) SMSC9218I_FIELD_8(val, 16)
+#define SMSC9218I_HW_CFG_GET_TX_FIF_SZ(reg) SMSC9218I_GET_FIELD_8(reg, 16)
+#define SMSC9218I_HW_CFG_BITMD_32 SMSC9218I_FLAG(2)
+#define SMSC9218I_HW_CFG_SRST_TO SMSC9218I_FLAG(1)
+#define SMSC9218I_HW_CFG_SRST SMSC9218I_FLAG(0)
+
+/** @} */
+
+/**
+ * @name Receive Datapath Control
+ * @{
+ */
+
+#define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31)
+
+/** @} */
+
+/**
+ * @name Receive FIFO Information
+ * @{
+ */
+
+#define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
+#define SMSC9218I_RX_FIFO_INF_GET_DUSED(reg) SMSC9218I_GET_FIELD_16(reg, 0)
+
+/** @} */
+
+/**
+ * @name Transmit FIFO Information
+ * @{
+ */
+
+#define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
+#define SMSC9218I_TX_FIFO_INF_GET_FREE(reg) SMSC9218I_GET_FIELD_16(reg, 0)
+
+/** @} */
+
+/**
+ * @name Power Management Control
+ * @{
+ */
+
+#define SMSC9218I_PMT_CTRL_PM_MODE_D0 0
+#define SMSC9218I_PMT_CTRL_PM_MODE_D1 SMSC9218I_FLAG(12)
+#define SMSC9218I_PMT_CTRL_PM_MODE_D2 SMSC9218I_FLAG(13)
+#define SMSC9218I_PMT_CTRL_PHY_RST SMSC9218I_FLAG(10)
+#define SMSC9218I_PMT_CTRL_WOL_EN SMSC9218I_FLAG(9)
+#define SMSC9218I_PMT_CTRL_ED_EN SMSC9218I_FLAG(8)
+#define SMSC9218I_PMT_CTRL_PME_TYPE_PUPU SMSC9218I_FLAG(6)
+#define SMSC9218I_PMT_CTRL_WUPS_NO 0
+#define SMSC9218I_PMT_CTRL_WUPS_ENERGY SMSC9218I_FLAG(4)
+#define SMSC9218I_PMT_CTRL_WUPS_MAGIC SMSC9218I_FLAG(5)
+#define SMSC9218I_PMT_CTRL_PME_IND SMSC9218I_FLAG(3)
+#define SMSC9218I_PMT_CTRL_PME_POL SMSC9218I_FLAG(2)
+#define SMSC9218I_PMT_CTRL_PME_EN SMSC9218I_FLAG(1)
+#define SMSC9218I_PMT_CTRL_READY SMSC9218I_FLAG(0)
+
+/** @} */
+
+/**
+ * @name General Purpose IO Configuration
+ * @{
+ */
+
+#define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30)
+#define SMSC9218I_GPIO_CFG_LED2 SMSC9218I_FLAG(29)
+#define SMSC9218I_GPIO_CFG_LED1 SMSC9218I_FLAG(28)
+#define SMSC9218I_GPIO_CFG_GPIO2_INT_POL SMSC9218I_FLAG(26)
+#define SMSC9218I_GPIO_CFG_GPIO1_INT_POL SMSC9218I_FLAG(25)
+#define SMSC9218I_GPIO_CFG_GPIO0_INT_POL SMSC9218I_FLAG(24)
+#define SMSC9218I_GPIO_CFG_GPIOBUF2 SMSC9218I_FLAG(18)
+#define SMSC9218I_GPIO_CFG_GPIOBUF1 SMSC9218I_FLAG(17)
+#define SMSC9218I_GPIO_CFG_GPIOBUF0 SMSC9218I_FLAG(16)
+#define SMSC9218I_GPIO_CFG_GPIODIR2 SMSC9218I_FLAG(10)
+#define SMSC9218I_GPIO_CFG_GPIODIR1 SMSC9218I_FLAG(9)
+#define SMSC9218I_GPIO_CFG_GPIODIR0 SMSC9218I_FLAG(8)
+#define SMSC9218I_GPIO_CFG_GPO4 SMSC9218I_FLAG(4)
+#define SMSC9218I_GPIO_CFG_GPO3 SMSC9218I_FLAG(3)
+#define SMSC9218I_GPIO_CFG_GPIO0 SMSC9218I_FLAG(0)
+#define SMSC9218I_GPIO_CFG_GPIO2 SMSC9218I_FLAG(2)
+#define SMSC9218I_GPIO_CFG_GPIO1 SMSC9218I_FLAG(1)
+
+/** @} */
+
+/**
+ * @name General Purpose Timer Configuration
+ * @{
+ */
+
+#define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29)
+#define SMSC9218I_GPT_CFG_LOAD(val) SMSC9218I_FIELD_16(val, 0)
+#define SMSC9218I_GPT_CFG_GET_LOAD(reg) SMSC9218I_GET_FIELD_16(reg, 0)
+
+/** @} */
+
+/**
+ * @name General Purpose Timer Count
+ * @{
+ */
+
+#define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0)
+
+/** @} */
+
+/**
+ * @name Word Swap
+ * @{
+ */
+
+#define SMSC9218I_ENDIAN_BIG 0xffffffffU
+
+/** @} */
+
+/**
+ * @name Free Run Counter
+ * @{
+ */
+
+#define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg)
+
+/** @} */
+
+/**
+ * @name Receiver Dropped Frames Counter
+ * @{
+ */
+
+#define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg)
+
+/** @} */
+
+/**
+ * @name EEPROM Command Register
+ * @{
+ */
+
+#define SMSC9218I_E2P_CMD_EPC_BUSY SMSC9218I_FLAG(31)
+
+/** @} */
+
+/**
+ * @name MAC Control and Status Synchronizer Command
+ * @{
+ */
+
+#define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31)
+#define SMSC9218I_MAC_CSR_CMD_READ SMSC9218I_FLAG(30)
+#define SMSC9218I_MAC_CSR_CMD_ADDR(val) SMSC9218I_FIELD_8(val, 0)
+#define SMSC9218I_MAC_CSR_CMD_GET_ADDR(reg) SMSC9218I_GET_FIELD_8(reg, 0)
+
+/** @} */
+
+/**
+ * @name MAC Control Register
+ * @{
+ */
+
+#define SMSC9218I_MAC_CR 0x00000001U
+#define SMSC9218I_MAC_CR_RXALL 0x80000000U
+#define SMSC9218I_MAC_CR_HBDIS 0x10000000U
+#define SMSC9218I_MAC_CR_RCVOWN 0x00800000U
+#define SMSC9218I_MAC_CR_LOOPBK 0x00200000U
+#define SMSC9218I_MAC_CR_FDPX 0x00100000U
+#define SMSC9218I_MAC_CR_MCPAS 0x00080000U
+#define SMSC9218I_MAC_CR_PRMS 0x00040000U
+#define SMSC9218I_MAC_CR_INVFILT 0x00020000U
+#define SMSC9218I_MAC_CR_PASSBAD 0x00010000U
+#define SMSC9218I_MAC_CR_HFILT 0x00008000U
+#define SMSC9218I_MAC_CR_HPFILT 0x00002000U
+#define SMSC9218I_MAC_CR_LCOLL 0x00001000U
+#define SMSC9218I_MAC_CR_BCAST 0x00000800U
+#define SMSC9218I_MAC_CR_DISRTY 0x00000400U
+#define SMSC9218I_MAC_CR_PADSTR 0x00000100U
+#define SMSC9218I_MAC_CR_BOLMT_MASK 0x000000c0U
+#define SMSC9218I_MAC_CR_BOLMT_10 0x00000000U
+#define SMSC9218I_MAC_CR_BOLMT_8 0x00000040U
+#define SMSC9218I_MAC_CR_BOLMT_4 0x00000080U
+#define SMSC9218I_MAC_CR_BOLMT_1 0x000000c0U
+#define SMSC9218I_MAC_CR_DFCHK 0x00000020U
+#define SMSC9218I_MAC_CR_TXEN 0x00000008U
+#define SMSC9218I_MAC_CR_RXEN 0x00000004U
+
+/** @} */
+
+/**
+ * @name MAC Address High
+ * @{
+ */
+
+#define SMSC9218I_MAC_ADDRH 0x00000002U
+#define SMSC9218I_MAC_ADDRH_MASK 0x0000ffffU
+
+/** @} */
+
+/**
+ * @name MAC Address Low
+ * @{
+ */
+
+#define SMSC9218I_MAC_ADDRL 0x00000003U
+#define SMSC9218I_MAC_ADDRL_MASK 0xffffffffU
+
+/** @} */
+
+/**
+ * @name Multicast Hash Table High
+ * @{
+ */
+
+#define SMSC9218I_MAC_HASHH 0x00000004U
+#define SMSC9218I_MAC_HASHH_MASK 0xffffffffU
+
+/** @} */
+
+/**
+ * @name Multicast Hash Table Low
+ * @{
+ */
+
+#define SMSC9218I_MAC_HASHL 0x00000005U
+#define SMSC9218I_MAC_HASHL_MASK 0xffffffffU
+
+/** @} */
+
+/**
+ * @name MII Access
+ * @{
+ */
+
+#define SMSC9218I_MAC_MII_ACC 0x00000006U
+#define SMSC9218I_MAC_MII_ACC_PHY_DEFAULT (1U << 11)
+#define SMSC9218I_MAC_MII_ACC_WRITE (1U << 1)
+#define SMSC9218I_MAC_MII_ACC_BUSY (1U << 0)
+#define SMSC9218I_MAC_MII_ACC_ADDR(addr) ((addr) << 6)
+
+/** @} */
+
+/**
+ * @name MII Data
+ * @{
+ */
+
+#define SMSC9218I_MAC_MII_DATA 0x00000007U
+
+/** @} */
+
+/**
+ * @name Flow Control
+ * @{
+ */
+
+#define SMSC9218I_MAC_FLOW 0x00000008U
+#define SMSC9218I_MAC_FLOW_FCPT_MASK 0xffff0000U
+#define SMSC9218I_MAC_FLOW_FCPASS 0x00000004U
+#define SMSC9218I_MAC_FLOW_FCEN 0x00000002U
+#define SMSC9218I_MAC_FLOW_FCBSY 0x00000001U
+
+/** @} */
+
+/**
+ * @name VLAN1 Tag
+ * @{
+ */
+
+#define SMSC9218I_MAC_VLAN1 0x00000009U
+
+/** @} */
+
+/**
+ * @name VLAN2 Tag
+ * @{
+ */
+
+#define SMSC9218I_MAC_VLAN2 0x0000000aU
+
+/** @} */
+
+/**
+ * @name Wake-up Frame Filter
+ * @{
+ */
+
+#define SMSC9218I_MAC_WUFF 0x0000000bU
+
+/** @} */
+
+/**
+ * @name Wake-up Control and Status
+ * @{
+ */
+
+#define SMSC9218I_MAC_WUCSR 0x0000000cU
+#define SMSC9218I_MAC_WUCSR_GUE 0x00000200U
+#define SMSC9218I_MAC_WUCSR_WUFR 0x00000040U
+#define SMSC9218I_MAC_WUCSR_MPR 0x00000020U
+#define SMSC9218I_MAC_WUCSR_WUEN 0x00000004U
+#define SMSC9218I_MAC_WUCSR_MPEN 0x00000002U
+
+/** @} */
+
+/**
+ * @name PHY Identifier 1
+ * @{
+ */
+
+#define SMSC9218I_PHY_ID1_LAN9118 0x7
+
+/** @} */
+
+/**
+ * @name PHY Identifier 2
+ * @{
+ */
+
+#define SMSC9218I_PHY_ID2_LAN9218 0xc0c3
+
+/** @} */
+
+/**
+ * @name Mode Control and Status
+ * @{
+ */
+
+#define SMSC9218I_PHY_MCSR 0x00000011U
+#define SMSC9218I_PHY_MCSR_EDPWRDOWN 0x00002000U
+#define SMSC9218I_PHY_MCSR_ENERGYON 0x00000002U
+
+/** @} */
+
+/**
+ * @name Special Modes
+ * @{
+ */
+
+#define SMSC9218I_PHY_SPMODES 0x00000012U
+
+/** @} */
+
+/**
+ * @name Special Control and Status Indications
+ * @{
+ */
+
+#define SMSC9218I_PHY_CSIR 0x0000001bU
+#define SMSC9218I_PHY_CSIR_SQEOFF 0x00000800U
+#define SMSC9218I_PHY_CSIR_FEFIEN 0x00000020U
+#define SMSC9218I_PHY_CSIR_XPOL 0x00000010U
+
+/** @} */
+
+/**
+ * @name Interrupt Source Flag
+ * @{
+ */
+
+#define SMSC9218I_PHY_ISR 0x0000001dU
+#define SMSC9218I_PHY_ISR_INT7 0x00000080U
+#define SMSC9218I_PHY_ISR_INT6 0x00000040U
+#define SMSC9218I_PHY_ISR_INT5 0x00000020U
+#define SMSC9218I_PHY_ISR_INT4 0x00000010U
+#define SMSC9218I_PHY_ISR_INT3 0x00000008U
+#define SMSC9218I_PHY_ISR_INT2 0x00000004U
+#define SMSC9218I_PHY_ISR_INT1 0x00000002U
+
+/** @} */
+
+/**
+ * @name Interrupt Mask
+ * @{
+ */
+
+#define SMSC9218I_PHY_IMR 0x0000001eU
+#define SMSC9218I_PHY_IMR_INT7 0x00000080U
+#define SMSC9218I_PHY_IMR_INT6 0x00000040U
+#define SMSC9218I_PHY_IMR_INT5 0x00000020U
+#define SMSC9218I_PHY_IMR_INT4 0x00000010U
+#define SMSC9218I_PHY_IMR_INT3 0x00000008U
+#define SMSC9218I_PHY_IMR_INT2 0x00000004U
+#define SMSC9218I_PHY_IMR_INT1 0x00000002U
+
+/** @} */
+
+/**
+ * @name PHY Special Control and Status
+ * @{
+ */
+
+#define SMSC9218I_PHY_PHYSCSR 0x0000001fU
+#define SMSC9218I_PHY_PHYSCSR_ANDONE 0x00001000U
+#define SMSC9218I_PHY_PHYSCSR_4B5B_EN 0x00000040U
+#define SMSC9218I_PHY_PHYSCSR_SPEED_MASK 0x0000001cU
+#define SMSC9218I_PHY_PHYSCSR_SPEED_10HD 0x00000004U
+#define SMSC9218I_PHY_PHYSCSR_SPEED_10FD 0x00000014U
+#define SMSC9218I_PHY_PHYSCSR_SPEED_100HD 0x00000008U
+#define SMSC9218I_PHY_PHYSCSR_SPEED_100FD 0x00000018U
+
+/** @} */
diff --git a/bsps/powerpc/mpc55xxevb/include/tm27.h b/bsps/powerpc/mpc55xxevb/include/tm27.h
new file mode 100644
index 0000000000..0dfa7bf628
--- /dev/null
+++ b/bsps/powerpc/mpc55xxevb/include/tm27.h
@@ -0,0 +1 @@
+#include <rtems/tm27-default.h>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-02 08:27:00 +0000