2 files changed, 405 insertions, 0 deletions
diff --git a/bsps/powerpc/include/ppc4xx/ppc405ex.h b/bsps/powerpc/include/ppc4xx/ppc405ex.h
new file mode 100644
index 0000000000..98ebbe28a2
--- /dev/null
+++ b/bsps/powerpc/include/ppc4xx/ppc405ex.h
@@ -0,0 +1,191 @@
+/*
+
+Constants for manipulating system registers of PPC 405EX in C
+
+Michael Hamel ADInstruments May 2008
+
+*/
+
+#include <libcpu/powerpc-utility.h>
+/* Indirect access to Clocking/Power-On registers */
+#define CPR0_DCR_BASE	0x0C
+#define cprcfga		(CPR0_DCR_BASE+0x0)
+#define cprcfgd		(CPR0_DCR_BASE+0x1)
+
+#define mtcpr(reg, d)					\
+  do {							\
+    PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg);	\
+    PPC_SET_DEVICE_CONTROL_REGISTER(cprcfgd,d);		\
+  } while (0)
+
+#define mfcpr(reg, d)					\
+  do {							\
+    PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg);	\
+    d = PPC_DEVICE_CONTROL_REGISTER(cprcfgd);		\
+  } while (0)
+
+
+/* Indirect access to System registers */
+#define SDR_DCR_BASE	0x0E
+#define sdrcfga		(SDR_DCR_BASE+0x0)
+#define sdrcfgd		(SDR_DCR_BASE+0x1)
+
+#define mtsdr(reg, d)					\
+  do {							\
+    PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg);	\
+    PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfgd,d);		\
+  } while (0)
+
+#define mfsdr(reg, d)					\
+    do {						\
+      PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg);	\
+      d = PPC_DEVICE_CONTROL_REGISTER(sdrcfgd);		\
+    } while (0)
+
+/* Indirect access to EBC registers */
+#define EBC_DCR_BASE	0x12
+#define ebccfga		(EBC_DCR_BASE+0x0)
+#define ebccfgd		(EBC_DCR_BASE+0x1)
+
+#define mtebc(reg, d)					\
+  do {							\
+    PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg);	\
+    PPC_SET_DEVICE_CONTROL_REGISTER(ebccfgd,d);		\
+  } while (0)
+
+#define mfebc(reg, d)					\
+  do {							\
+    PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg);	\
+    d = PPC_DEVICE_CONTROL_REGISTER(ebccfgd);		\
+  } while (0)
+
+/* EBC DCRs */
+enum {
+	/*
+	EBC0_B0CR	=	0,
+	EBC0_B1CR	=	1,
+	EBC0_B2CR	=	2,
+	EBC0_B3CR	=	3,
+	EBC0_B0AP	=	0x10,
+	EBC0_B1AP	=	0x11,
+	EBC0_B2AP	=	0x12,
+	EBC0_B3AP	=	0x13,
+	EBC0_BEAR	=	0x20,
+	EBC0_BESR	=	0x21,
+	EBC0_CFG	=	0x23,
+	*/
+	EBC0_CID	=	0x24
+};
+
+enum {
+	SDR0_PINSTP = 0x40,
+	SDR0_UART0	= 0x120,
+	SDR0_UART1  = 0x121,
+	SDR0_C405	= 0x180,
+	SDR0_SRST0  = 0x200,
+	SDR0_MALTBL = 0x280,
+	SDR0_MALRBL = 0x2A0,
+	SDR0_MALTBS = 0x2C0,
+	SDR0_MALRBS = 0x2E0,
+	SDR0_PFC2   = 0x4102,
+	SDR0_MFR    = 0x4300,
+	SDR0_EMAC0RXST = 0x4301,
+	SDR0_HSF    = 0x4400
+};
+
+enum {
+	CPR0_CLKUPD = 0x20,
+	CPR0_PLLC = 0x40,
+	CPR0_PLLD = 0x60,
+	CPR0_CPUD = 0x80,
+	CPR0_PLBD = 0xA0,
+	CPR0_OPBD = 0xC0,
+	CPR0_PERD = 0xE0,
+	CPR0_AHBD = 0x100,
+	CPR0_ICFG = 0x140
+};
+
+/* Memory-mapped registers */
+
+
+/*======================= Ethernet =================== */
+
+enum {
+	EMAC0EXAddress = 0xEF600900,
+	EMAC1EXAddress = 0xEF600A00,
+	
+	/* 405EX-specific bits in EMAC_MR1 */
+	keEMAC1000Mbps = 0x00800000,
+	keEMAC16KRxFIFO = 0x00280000,
+	keEMAC8KRxFIFO  = 0x00200000,
+	keEMAC4KRxFIFO  = 0x00180000,
+	keEMAC2KRxFIFO  = 0x00100000,
+	keEMAC1KRxFIFO  = 0x00080000,
+	keEMAC16KTxFIFO = 0x00050000,
+	keEMAC8KTxFIFO  = 0x00040000,
+	keEMAC4KTxFIFO  = 0x00030000,
+	keEMAC2KTxFIFO  = 0x00020000,
+	keEMAC1KTxFIFO  = 0x00010000,
+	keEMACJumbo	    = 0x00000800,
+	keEMACIPHYAddr4 = 0x180,
+	keEMACOPB50MHz  = 0x00,
+	keEMACOPB66MHz  = 0x08,
+	keEMACOPB83MHz  = 0x10,
+	keEMACOPB100MHz = 0x18,
+	keEMACOPBGt100  = 0x20,
+	
+	/* 405EX-specific bits in MAL0_CFG */
+	keMALRdMaxBurst4  = 0,
+	keMALRdMaxBurst8  = 0x00100000,
+	keMALRdMaxBurst16 = 0x00200000,
+	keMALRdMaxBurst32 = 0x00300000,
+	
+	keMALWrLowPriority    = 0,
+	keMALWrMedLowPriority = 0x00040000,
+	keMALWrMedHiPriority  = 0x00080000,
+	keMALWrHighPriority   = 0x000C0000,
+
+	keMALWrMaxBurst4  = 0,
+	keMALWrMaxBurst8  = 0x00010000,
+	keMALWrMaxBurst16 = 0x00020000,
+	keMALWrMaxBurst32 = 0x00030000,
+	
+	/* 405EX-specific STA bits */
+	keSTARun	  = 0x8000,
+	keSTADirectRd = 0x1000,
+	keSTADirectWr = 0x0800,
+	keSTAIndirAddr = 0x2000,
+	keSTAIndirRd  = 0x3000,
+	keSTAIndirWr  = 0x2800
+};
+
+typedef struct GPIORegisters {
+	uint32_t OR;
+	uint32_t GPIO_TCR;		/* Note that TCR is defined as a DCR name */
+	uint32_t OSRL;
+	uint32_t OSRH;
+	uint32_t TSRL;
+	uint32_t TSRH;
+	uint32_t ODR;
+	uint32_t IR;
+	uint32_t RR1;
+	uint32_t RR2;
+	uint32_t RR3;
+	uint32_t unknown;
+	uint32_t ISR1L;
+	uint32_t ISR1H;
+	uint32_t ISR2L;
+	uint32_t ISR2H;
+	uint32_t ISR3L;
+	uint32_t ISR3H;
+} GPIORegisters;
+
+enum { GPIOAddress = 0xEF600800 };
+
+typedef struct RGMIIRegisters {
+	uint32_t FER;
+	uint32_t SSR;
+} RGMIIRegisters;
+
+enum { RGMIIAddress = 0xEF600B00 };
+
diff --git a/bsps/powerpc/include/ppc4xx/ppc405gp.h b/bsps/powerpc/include/ppc4xx/ppc405gp.h
new file mode 100644
index 0000000000..9cf46a780a
--- /dev/null
+++ b/bsps/powerpc/include/ppc4xx/ppc405gp.h
@@ -0,0 +1,214 @@
+
+/* SDRAM DCRs */
+enum {
+	SDRAM0_BESR0	=	0,
+	SDRAM0_BESR1	=	8,
+	SDRAM0_BEAR		=	0x10,
+	SDRAM0_CFG		=	0x20,
+	SDRAM0_STATUS	=	0x24,
+	SDRAM0_RTR		=	0x30,
+	SDRAM0_PMIT		=	0x34,
+	SDRAM0_TR		=	0x80
+};
+
+
+/* EBC DCRs */
+enum {
+	EBC0_B0CR	=	0,
+	EBC0_B1CR	=	1,
+	EBC0_B2CR	=	2,
+	EBC0_B3CR	=	3,
+	EBC0_B4CR	=	4,
+	EBC0_B5CR	=	5,
+	EBC0_B6CR	=	6,
+	EBC0_B7CR	=	7,
+	EBC0_B0AP	=	0x10,
+	EBC0_B1AP	=	0x11,
+	EBC0_B2AP	=	0x12,
+	EBC0_B3AP	=	0x13,
+	EBC0_B4AP	=	0x14,
+	EBC0_B5AP	=	0x15,
+	EBC0_B6AP	=	0x16,
+	EBC0_B7AP	=	0x17,
+	EBC0_BEAR	=	0x20,
+	EBC0_BESR0	=	0x21,
+	EBC0_BESR1	=	0x22,
+	EBC0_CFG	=	0x23
+};
+
+/* MAL DCRs, have to be #defines */
+#define	MAL0_CFG		0x180
+#define	MAL0_ESR		0x181
+#define	MAL0_IER		0x182
+#define	MAL0_TXCASR		0x184
+#define	MAL0_TXCARR		0x185
+#define	MAL0_TXEOBISR	0x186
+#define	MAL0_TXDEIR		0x187
+#define	MAL0_RXCASR		0x190
+#define	MAL0_RXCARR		0x191
+#define	MAL0_RXEOBISR	0x192
+#define	MAL0_RXDEIR		0x193
+#define	MAL0_TXCTP0R	0x1A0
+#define	MAL0_TXCTP1R	0x1A1
+#define	MAL0_RXCTP0R	0x1C0
+#define	MAL0_RXCTP1R	0x1C1
+#define	MAL0_RCBS0		0x1E0
+#define	MAL0_RCBS1		0x1E1
+
+/* Memory-mapped registers */
+
+typedef struct EthernetRegisters_GP {
+	uint32_t mode0;
+	uint32_t mode1;
+	uint32_t xmtMode0;
+	uint32_t xmtMode1;
+	uint32_t rcvMode;
+	uint32_t intStatus;
+	uint32_t intEnable;
+	uint32_t addrHi;
+	uint32_t addrLo;
+	uint32_t VLANTPID;
+	uint32_t VLANTCI;
+	uint32_t pauseTimer;
+	uint32_t g_indivHash[4];  /* EX non-IP multicast addr/mask */
+	uint32_t g_groupHash[4];
+	uint32_t lastSrcLo;
+	uint32_t lastSrcHi;
+	uint32_t IPGap;
+	uint32_t STAcontrol;
+	uint32_t xmtReqThreshold;
+	uint32_t rcvWatermarks;
+	uint32_t bytesXmtd;
+	uint32_t bytesRcvd;
+	uint32_t e_unused2;
+	uint32_t e_revID;
+	uint32_t e_unused3[2];
+	uint32_t e_indivHash[8];
+	uint32_t e_groupHash[8];
+	uint32_t e_xmtPause;
+} EthernetRegisters_GP;
+
+typedef struct EthernetRegisters_GP EthernetRegisters_EX;
+
+enum { EMACAddress = 0xEF600800 };
+enum { EMAC0GPAddress = 0xEF600800 };
+
+enum {
+	// Mode 0 bits
+	kEMACRxIdle   = 0x80000000,
+	kEMACTxIdle   = 0x40000000,
+	kEMACSoftRst  = 0x20000000,
+	kEMACTxEnable = 0x10000000,
+	kEMACRxEnable = 0x08000000,
+
+	// Mode 1 bits
+	kEMACFullDuplex = 0x80000000,
+	kEMACDoFlowControl = 0x10000000,
+	kEMACIgnoreSQE  = 0x01000000,
+	kEMAC100MBbps	 = 0x00400000,
+	kEMAC4KRxFIFO   = 0x00300000,
+	kEMAC2KTxFIFO	 = 0x00080000,
+	kEMACTx0Multi	 = 0x00008000,
+	kEMACTxDependent= 0x00014000,
+	kEMAC100Mbps	 = 0x00400000,
+	kgEMAC4KRxFIFO   = 0x00300000,
+	kgEMAC2KTxFIFO	 = 0x00080000,
+	kgEMACTx0Multi	 = 0x00008000,
+	kgEMACTxDependent= 0x00014000,
+
+
+	// Tx mode bits
+	kEMACNewPacket0	= 0x80000000,
+	kEMACNewPacket1	= 0x40000000,
+
+	// Receive mode bits
+	kEMACStripPadding = 0x80000000,
+	kEMACStripFCS     = 0x40000000,
+	kEMACRcvRunts		= 0x20000000,
+	kEMACRcvFCSErrs	= 0x10000000,
+	kEMACRcvOversize  = 0x08000000,
+	kEMACPromiscRcv	= 0x01000000,
+	kEMACPromMultRcv  = 0x00800000,
+	kEMACIndivRcv		= 0x00400000,
+	kEMACHashRcv		= 0x00200000,
+	kEMACBrcastRcv		= 0x00100000,
+	kEMACMultcastRcv	= 0x00080000,
+	keEMACNonIPMultcast = 0x00040000,
+	keEMACRxFIFOAFMax   = 7,
+	
+	// EMAC_STACR bits
+	kgSTAComplete   = 0x8000,
+	kSTAErr		= 0x4000,
+	
+	// Interrupt status bits
+	kEMACIOverrun = 0x02000000,
+	kEMACIPause   = 0x01000000,
+	kEMACIBadPkt  = 0x00800000,
+	kEMACIRuntPkt = 0x00400000,
+	kEMACIShortEvt= 0x00200000,
+	kEMACIAlignErr= 0x00100000,
+	kEMACIBadFCS  = 0x00080000,
+	kEMACIOverSize= 0x00040000,
+	kEMACILLCRange= 0x00020000,
+	kEMACISQEErr  = 0x00000080,
+	kEMACITxErr   = 0x00000040,
+
+	// Buffer descriptor control bits
+	kMALTxReady			= 0x8000,
+	kMALRxEmpty			= 0x8000,
+	kMALWrap				= 0x4000,
+	kMALContinuous		= 0x2000,
+	kMALLast				= 0x1000,
+	kMALRxFirst			= 0x0800,
+	kMALInterrupt		= 0x0400,
+
+	kMALReset			= 0x80000000,
+	kMALLowPriority    = 0,
+	kMALMedLowPriority = 0x00400000,
+	kMALMedHiPriority  = 0x00800000,
+	kMALHighPriority   = 0x00C00000,
+	kMALLatency8       = 0x00040000,
+	kMALLockErr	    = 0x8000,
+	kMALCanBurst	= 0x4000,
+	kMALLocksOPB    = 0x80,
+	kMALLocksErrs	= 0x2,
+	
+	// MAL channel masks
+	kMALChannel0 = 0x80000000,
+	kMALChannel1 = 0x40000000,
+
+	// EMAC Tx descriptor bits sent
+	kEMACGenFCS			= 0x200,
+	kEMACGenPad			= 0x100,
+	kEMACInsSrcAddr	= 0x080,
+	kEMACRepSrcAddr	= 0x040,
+	kEMACInsVLAN		= 0x020,
+	kEMACRepVLAN		= 0x010,
+
+	// EMAC TX descriptor bits returned
+	kEMACErrMask      = 0x3FF,
+	kEMACFCSWrong		= 0x200,
+	kEMACBadPrev		= 0x100,
+	kEMACLostCarrier	= 0x080,
+	kEMACDeferred		= 0x040,
+	kEMACCollFail		= 0x020,
+	kEMACLateColl		= 0x010,
+	kEMACMultColl		= 0x008,
+	kEMACOneColl		= 0x004,
+	kEMACUnderrun		= 0x002,
+	kEMACSQEFail		= 0x001,
+
+	// EMAC Rx descriptor bits returned
+	kEMACOverrun  		= 0x200,
+	kEMACPausePkt 		= 0x100,
+	kEMACBadPkt	  		= 0x080,
+	kEMACRuntPkt  		= 0x040,
+	kEMACShortEvt 		= 0x020,
+	kEMACAlignErr 		= 0x010,
+	kEMACBadFCS   		= 0x008,
+	kEMACPktLong  		= 0x004,
+	kEMACPktOOR   		= 0x002,
+	kEMACPktIRL   		= 0x001
+};
+
+